From patchwork Wed Nov 13 09:58:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 13873401 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 583C5D41C27 for ; Wed, 13 Nov 2024 10:07:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=N7dWDcKVEIAR1uJKHPabKsVtTp+3VOI5259uT1+UY98=; b=gQCyikF9WCcOq4 /eGE/8tZxfSo+3VkZvngOPVn1Tmx7mAsceukl6ZhiQ/JAJPt0oK+FffHP4kPpfLRqdLEKr+YKeIc1 SvnlMINHZpGjBawmXoFM+J5tgc/QeB3eDA6e77IuHnGxuHF2pAiMEbCNvw2YXlO0SmeZXVW9iZPY4 MBSaoNEaFXGWjsUacTXN4r35xTxyhEzateTF2qUR/ZvAFIkf8738QBDhExzS4eRn3Klmq5grEPPwi idOWZIxjL+QRNN22Pu3vCd3i/DaP6dQiwiZxmENtbGjKfEUw5pMKNher85hYZTAvhYGk3JiuMyImG K/iPdauO+36F3BzdncMw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBAHL-00000006NC6-3gQ9; Wed, 13 Nov 2024 10:07:15 +0000 Received: from smtp84.cstnet.cn ([159.226.251.84] helo=cstnet.cn) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBAGC-00000006Mz6-1yaR for linux-riscv@lists.infradead.org; Wed, 13 Nov 2024 10:07:15 +0000 Received: from ubt.. (unknown [210.73.53.31]) by APP-05 (Coremail) with SMTP id zQCowADHr7p4eDRnlmI4Ag--.57753S3; Wed, 13 Nov 2024 17:59:21 +0800 (CST) From: Chunyan Zhang To: Palmer Dabbelt , Albert Ou , Paul Walmsley , Alexandre Ghiti , Andrew Morton Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: [PATCH V5 1/3] riscv: mm: Prepare for reusing PTE RSW bit(9) Date: Wed, 13 Nov 2024 17:58:31 +0800 Message-Id: <20241113095833.1805746-2-zhangchunyan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> References: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowADHr7p4eDRnlmI4Ag--.57753S3 X-Coremail-Antispam: 1UD129KBjvJXoW7ZFW8uFykAr4DZF1UuF1fCrg_yoW8AryDpF s5CF9YkFWrCrySkay2yFn2gr4UA398K34agry8ur4UJas8t3yUZ39xK347Xay8Xa1vvF93 GFWvg345ury3Jw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPFb7Iv0xC_Zr1lb4IE77IF4wAFF20E14v26ryj6rWUM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUGwA2048vs2IY020Ec7CjxVAFwI0_JFI_Gr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIE c7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I 8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCF s4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCY02Avz4 vE14v_GFWl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG 67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MI IYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E 14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJV W8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUsNBM UUUUU X-Originating-IP: [210.73.53.31] X-CM-SenderInfo: x2kd0wxfkx051dq6x2xfdvhtffof0/1tbiBgsAB2c0cpgTSwAAsr X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241113_020604_886340_0F854343 X-CRM114-Status: GOOD ( 10.77 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The PTE bit(9) on RISC-V is reserved for software, it is used by devmap now which has to be disabled if we want to use bit(9) for other features, since there's no more free PTE bit on RISC-V now. So to make ARCH_HAS_PTE_DEVMAP selectable, this patch uses it as the build condition of devmap definitions. Signed-off-by: Chunyan Zhang --- arch/riscv/include/asm/pgtable-64.h | 2 +- arch/riscv/include/asm/pgtable-bits.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 0897dd99ab8d..babb8d2b0f0b 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -398,7 +398,7 @@ static inline struct page *pgd_page(pgd_t pgd) #define p4d_offset p4d_offset p4d_t *p4d_offset(pgd_t *pgd, unsigned long address); -#ifdef CONFIG_TRANSPARENT_HUGEPAGE +#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_ARCH_HAS_PTE_DEVMAP) static inline int pte_devmap(pte_t pte); static inline pte_t pmd_pte(pmd_t pmd); diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index a8f5205cea54..5bcc73430829 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -19,7 +19,13 @@ #define _PAGE_SOFT (3 << 8) /* Reserved for software */ #define _PAGE_SPECIAL (1 << 8) /* RSW: 0x1 */ + +#ifdef CONFIG_ARCH_HAS_PTE_DEVMAP #define _PAGE_DEVMAP (1 << 9) /* RSW, devmap */ +#else +#define _PAGE_DEVMAP 0 +#endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */ + #define _PAGE_TABLE _PAGE_PRESENT /* From patchwork Wed Nov 13 09:58:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 13873403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 225F1D41C27 for ; Wed, 13 Nov 2024 10:07:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZEHCShypuUULqK6BJzmzsp+OcXXqZlgjp8q51CF6F2I=; b=r7XNCQZvQSNEMA bx2kWhpjz2ZKXHXiWwP49CJyBOG2zoEBawj2bNyCIP9xwwdglahMr64q2RK8kBjK63/KayUrdrjKT G6t9ksSw71s1xpBOHw21UbsQFw3Y1D6Yp6sDsGxJPn7uvkYd305LXrjhdvJnhkvd+8mkejE3SJZqw oHpXOnRMJOUAje1TdplhWc3DlA9wMGvv3MVnfyt6c1/8tdP5ZQnaf+/KVFyVuDapSHjPPUFFcgs3j aqnOr629zcokLPeNajvR4zcS19RRSTPyrKRIY9SmnxO9gfj88HnkQHjDkR+Bs1JaRUHbIcJ5PHqCn jfDkMZ8FZkk6U5o/cy5w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBAHR-00000006NEV-2kxS; Wed, 13 Nov 2024 10:07:21 +0000 Received: from smtp84.cstnet.cn ([159.226.251.84] helo=cstnet.cn) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBAGC-00000006Mz8-2049 for linux-riscv@lists.infradead.org; Wed, 13 Nov 2024 10:07:19 +0000 Received: from ubt.. (unknown [210.73.53.31]) by APP-05 (Coremail) with SMTP id zQCowADHr7p4eDRnlmI4Ag--.57753S4; Wed, 13 Nov 2024 17:59:22 +0800 (CST) From: Chunyan Zhang To: Palmer Dabbelt , Albert Ou , Paul Walmsley , Alexandre Ghiti , Andrew Morton Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: [PATCH V5 2/3] riscv: mm: Add soft-dirty page tracking support Date: Wed, 13 Nov 2024 17:58:32 +0800 Message-Id: <20241113095833.1805746-3-zhangchunyan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> References: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowADHr7p4eDRnlmI4Ag--.57753S4 X-Coremail-Antispam: 1UD129KBjvJXoW3AF4fXF13Cr4rKw1kWry5XFb_yoW7ZrWDpF s5GF1rZayFyFn3Kayftr4qgrWYywn3Way5Xry3Ca1kJayUGrWUXFZ0gr13X345XFykZa4f ZrZ5Kay5CrsrJr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPFb7Iv0xC_tr1lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUXwA2048vs2IY020Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIE c7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I 8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCF s4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCY02Avz4 vE14v_GFWl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG 67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MI IYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E 14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJV W8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxU37PE UUUUU X-Originating-IP: [210.73.53.31] X-CM-SenderInfo: x2kd0wxfkx051dq6x2xfdvhtffof0/1tbiBwkAB2c0ciEVcgAAsu X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241113_020604_910981_0EE943EB X-CRM114-Status: GOOD ( 14.85 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The PTE bit(9) is reserved for software, now used by devmap, this patch reuses bit(9) for soft-dirty which is enabled only if !CONFIG_ARCH_HAS_PTE_DEVMAP, in other words, soft-dirty and devmap will be mutually exclusive on RISC-V. To add swap PTE soft-dirty tracking, we borrow bit(4) which is available for swap PTEs on RISC-V systems. Reviewed-by: Alexandre Ghiti Signed-off-by: Chunyan Zhang --- arch/riscv/Kconfig | 27 ++++++++++- arch/riscv/include/asm/pgtable-bits.h | 12 +++++ arch/riscv/include/asm/pgtable.h | 69 ++++++++++++++++++++++++++- 3 files changed, 106 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index f4c570538d55..3bccdcae9445 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -40,7 +40,6 @@ config RISCV select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE select ARCH_HAS_PMEM_API select ARCH_HAS_PREPARE_SYNC_CORE_CMD - select ARCH_HAS_PTE_DEVMAP if 64BIT && MMU select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU @@ -966,6 +965,32 @@ config RANDOMIZE_BASE If unsure, say N. +choice + prompt "PTE RSW bit(9) usage" + default RISCV_HAS_PTE_DEVMAP + depends on MMU && 64BIT + help + RISC-V PTE bit(9) is reserved for software, and used by more than + one kernel feature which cannot be supported at the same time. + So we have to select one for it. + +config RISCV_HAS_PTE_DEVMAP + bool "devmap" + select ARCH_HAS_PTE_DEVMAP + help + The PTE bit(9) is used for devmap mark. ZONE_DEVICE pages need devmap + PTEs support to function. + + So if you want to use ZONE_DEVICE, select this. + +config RISCV_HAS_SOFT_DIRTY + bool "soft-dirty" + select HAVE_ARCH_SOFT_DIRTY + help + The PTE bit(9) is used for soft-dirty tracking. + +endchoice + endmenu # "Kernel features" menu "Boot options" diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index 5bcc73430829..c6d51fe9fc6f 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -26,6 +26,18 @@ #define _PAGE_DEVMAP 0 #endif /* CONFIG_ARCH_HAS_PTE_DEVMAP */ +#ifdef CONFIG_MEM_SOFT_DIRTY +#define _PAGE_SOFT_DIRTY (1 << 9) /* RSW: 0x2 for software dirty tracking */ +/* + * BIT 4 is not involved into swap entry computation, so we + * can borrow it for swap page soft-dirty tracking. + */ +#define _PAGE_SWP_SOFT_DIRTY _PAGE_USER +#else +#define _PAGE_SOFT_DIRTY 0 +#define _PAGE_SWP_SOFT_DIRTY 0 +#endif /* CONFIG_MEM_SOFT_DIRTY */ + #define _PAGE_TABLE _PAGE_PRESENT /* diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index e79f15293492..1779eae5cb49 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -424,7 +424,7 @@ static inline pte_t pte_mkwrite_novma(pte_t pte) static inline pte_t pte_mkdirty(pte_t pte) { - return __pte(pte_val(pte) | _PAGE_DIRTY); + return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); } static inline pte_t pte_mkclean(pte_t pte) @@ -457,6 +457,38 @@ static inline pte_t pte_mkhuge(pte_t pte) return pte; } +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY +static inline int pte_soft_dirty(pte_t pte) +{ + return pte_val(pte) & _PAGE_SOFT_DIRTY; +} + +static inline pte_t pte_mksoft_dirty(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); +} + +static inline pte_t pte_clear_soft_dirty(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_SOFT_DIRTY)); +} + +static inline int pte_swp_soft_dirty(pte_t pte) +{ + return pte_val(pte) & _PAGE_SWP_SOFT_DIRTY; +} + +static inline pte_t pte_swp_mksoft_dirty(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); +} + +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_SWP_SOFT_DIRTY)); +} +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ + #ifdef CONFIG_RISCV_ISA_SVNAPOT #define pte_leaf_size(pte) (pte_napot(pte) ? \ napot_cont_size(napot_cont_order(pte)) :\ @@ -757,6 +789,40 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) return pte_pmd(pte_mkdevmap(pmd_pte(pmd))); } +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY +static inline int pmd_soft_dirty(pmd_t pmd) +{ + return pte_soft_dirty(pmd_pte(pmd)); +} + +static inline pmd_t pmd_mksoft_dirty(pmd_t pmd) +{ + return pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))); +} + +static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd) +{ + return pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))); +} + +#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION +static inline int pmd_swp_soft_dirty(pmd_t pmd) +{ + return pte_swp_soft_dirty(pmd_pte(pmd)); +} + +static inline pmd_t pmd_swp_mksoft_dirty(pmd_t pmd) +{ + return pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))); +} + +static inline pmd_t pmd_swp_clear_soft_dirty(pmd_t pmd) +{ + return pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))); +} +#endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */ +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ + static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, pmd_t pmd) { @@ -847,6 +913,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, * Format of swap PTE: * bit 0: _PAGE_PRESENT (zero) * bit 1 to 3: _PAGE_LEAF (zero) + * bit 4: _PAGE_SWP_SOFT_DIRTY * bit 5: _PAGE_PROT_NONE (zero) * bit 6: exclusive marker * bits 7 to 11: swap type From patchwork Wed Nov 13 09:58:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 13873402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B779FD41C27 for ; Wed, 13 Nov 2024 10:07:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MCJzpZQNok6xQYP/QNnvyLY6HjCGTepEoDltfyUgrqM=; b=bgqKjb9E5mmoxz SiUXubPQsL3oX7W1KZm9ib6Df63MCFN7opyFkxO/u3r+8bP9gC7RpXC+iU2UXOQ+Mz9zAQJL+g80G jGFlaxSzEE3iHPHE9A719MX2aEjZkA6wywYvBVKwW+ajAJOKadv0z8jc7ITj78B6CzbdHDmvDgx4U PyHiN3RNOI4uaXT3Cip3DQoG/s9POV5Oze8pCaqmlhD5XaAik3evTwOFifMNYYUtKrHwxcbHvYH6i n05QIh/sCa3OwZHqpMsf3vznuekoqnNj2bIZHG6X1C/bGhJlW9Ec9XyNaNFepbfbmD9noAPJZ2u8i QDEosxYa/dp+xSls5C8g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBAHO-00000006NCx-2tc6; Wed, 13 Nov 2024 10:07:18 +0000 Received: from smtp84.cstnet.cn ([159.226.251.84] helo=cstnet.cn) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBAGC-00000006Mz7-1yih for linux-riscv@lists.infradead.org; Wed, 13 Nov 2024 10:07:17 +0000 Received: from ubt.. (unknown [210.73.53.31]) by APP-05 (Coremail) with SMTP id zQCowADHr7p4eDRnlmI4Ag--.57753S5; Wed, 13 Nov 2024 17:59:22 +0800 (CST) From: Chunyan Zhang To: Palmer Dabbelt , Albert Ou , Paul Walmsley , Alexandre Ghiti , Andrew Morton Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: [PATCH V5 3/3] riscv: mm: Add uffd write-protect support Date: Wed, 13 Nov 2024 17:58:33 +0800 Message-Id: <20241113095833.1805746-4-zhangchunyan@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> References: <20241113095833.1805746-1-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowADHr7p4eDRnlmI4Ag--.57753S5 X-Coremail-Antispam: 1UD129KBjvJXoWxGw1UAFW7AF1kZF13WryDWrg_yoWrZr43pr s5Ga1ru3yDJFn7KayftrWxKrWrZw43Wa4DXr9xua1kJFyUKrWDXFyrK34aqryrXFWvv34x JrWrKryrCw47JF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPFb7Iv0xC_tr1lb4IE77IF4wAFF20E14v26rWj6s0DM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI 8067AKxVWUWwA2048vs2IY020Ec7CjxVAFwI0_Xr0E3s1l8cAvFVAK0II2c7xJM28CjxkF 64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcV CY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIE c7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I 8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCF s4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262kKe7AKxVWUAVWUtwCY02Avz4 vE14v_GFWl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG 67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MI IYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E 14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJV W8JwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjxUI8nY UUUUU X-Originating-IP: [210.73.53.31] X-CM-SenderInfo: x2kd0wxfkx051dq6x2xfdvhtffof0/1tbiBwkAB2c0ciEVcgABsv X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241113_020604_886840_BBCB6A74 X-CRM114-Status: GOOD ( 12.46 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Reuse PTE bit(9) to do uffd-wp tracking and make it mutually exclusive with soft-dirty and devmap which all use this PTE bit. Additionally for tracking the uffd-wp state as a PTE swap bit, we use swap entry pte bit(4) which is also used by swap soft-dirty tracking. Signed-off-by: Chunyan Zhang --- arch/riscv/Kconfig | 7 +++ arch/riscv/include/asm/pgtable-bits.h | 13 ++++++ arch/riscv/include/asm/pgtable.h | 66 ++++++++++++++++++++++++++- 3 files changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3bccdcae9445..920071a05512 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -989,6 +989,13 @@ config RISCV_HAS_SOFT_DIRTY help The PTE bit(9) is used for soft-dirty tracking. +config RISCV_HAS_USERFAULTFD_WP + bool "userfaultfd write protection" + select HAVE_ARCH_USERFAULTFD_WP + depends on USERFAULTFD + help + The PTE bit(9) is used for userfaultfd write-protected + tracking. endchoice endmenu # "Kernel features" diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h index c6d51fe9fc6f..7de16141c049 100644 --- a/arch/riscv/include/asm/pgtable-bits.h +++ b/arch/riscv/include/asm/pgtable-bits.h @@ -38,6 +38,19 @@ #define _PAGE_SWP_SOFT_DIRTY 0 #endif /* CONFIG_MEM_SOFT_DIRTY */ +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP +/* + * CONFIG_HAVE_ARCH_USERFAULTFD_WP is mutually exclusive with + * HAVE_ARCH_SOFT_DIRTY so we can use the same bit for uffd-wp + * and soft-dirty tracking. + */ +#define _PAGE_UFFD_WP (1 << 9) /* RSW: 0x2 for uffd-wp tracking */ +#define _PAGE_SWP_UFFD_WP _PAGE_USER +#else +#define _PAGE_UFFD_WP 0 +#define _PAGE_SWP_UFFD_WP 0 +#endif + #define _PAGE_TABLE _PAGE_PRESENT /* diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 1779eae5cb49..f241c444cebd 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -413,6 +413,38 @@ static inline pte_t pte_wrprotect(pte_t pte) return __pte(pte_val(pte) & ~(_PAGE_WRITE)); } +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP +static inline int pte_uffd_wp(pte_t pte) +{ + return pte_val(pte) & _PAGE_UFFD_WP; +} + +static inline pte_t pte_mkuffd_wp(pte_t pte) +{ + return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP)); +} + +static inline pte_t pte_clear_uffd_wp(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP)); +} + +static inline int pte_swp_uffd_wp(pte_t pte) +{ + return pte_val(pte) & _PAGE_SWP_UFFD_WP; +} + +static inline pte_t pte_swp_mkuffd_wp(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP); +} + +static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP)); +} +#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ + /* static inline pte_t pte_mkread(pte_t pte) */ static inline pte_t pte_mkwrite_novma(pte_t pte) @@ -789,6 +821,38 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) return pte_pmd(pte_mkdevmap(pmd_pte(pmd))); } +#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP +static inline int pmd_uffd_wp(pmd_t pmd) +{ + return pte_uffd_wp(pmd_pte(pmd)); +} + +static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) +{ + return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))); +} + +static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) +{ + return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))); +} + +static inline int pmd_swp_uffd_wp(pmd_t pmd) +{ + return pte_swp_uffd_wp(pmd_pte(pmd)); +} + +static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) +{ + return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))); +} + +static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) +{ + return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))); +} +#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ + #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY static inline int pmd_soft_dirty(pmd_t pmd) { @@ -913,7 +977,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, * Format of swap PTE: * bit 0: _PAGE_PRESENT (zero) * bit 1 to 3: _PAGE_LEAF (zero) - * bit 4: _PAGE_SWP_SOFT_DIRTY + * bit 4: _PAGE_SWP_SOFT_DIRTY or _PAGE_SWP_UFFD_WP * bit 5: _PAGE_PROT_NONE (zero) * bit 6: exclusive marker * bits 7 to 11: swap type