From patchwork Thu Nov 14 01:12:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874424 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68086D637D6 for ; Thu, 14 Nov 2024 01:14:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOQY-0007Rv-Ka; Wed, 13 Nov 2024 20:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOQX-0007Rc-52 for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:13:41 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOQV-0001uj-FO for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:13:40 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4315f24a6bbso941275e9.1 for ; Wed, 13 Nov 2024 17:13:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546817; x=1732151617; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JNM7lQQia63slkmiUAhjBzskGFuKTSllmSkbwj/sT+I=; b=R78ImOcxcigsPnj6v0IY4brbqmrynaGc4Vf3YMpmTC+8u6I+XVwkaC5V5HU9wq1j6N goBCzBJg4oN1dAQo/d+KSIpURFerbcT3eAwPWhWqCQfGVCelG8gAbkunvyrVFI2mjc0E M1KIfitx4Av34iSv4n9Xs3hYpeikWTeqJb6Y+mekef2UiBp/fgAVTkQn7V9zEsbG/GoD ZFGib+twNQF2dstgc1yaWTnBg6MrHROzymF0/j0OyuvrDnYuBK1OEseML1S57NDyNII2 7yMy0cfKGoE7m16FlklNkPW5gjLPkQbbTHA0nh5sxBtF0dAPBakbLifOxRqFhaFsT7y4 pVpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546817; x=1732151617; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JNM7lQQia63slkmiUAhjBzskGFuKTSllmSkbwj/sT+I=; b=FTCPZ9S9GrkGLONaNcZy7nyRWTphR6naDpBR9ewecr/7wQhE1taM64U6hDEAvXLZ13 JE0dy/VXQgI6PrGb43sAkd1r0MbVtoq4XBWE/gIs5DW4htBcW6s8/rhUS4SfprKVZMkt HBVazDAw5d/41LW8axBATg38Ek3BZbRO2emswqu2CyMj2YhkTZnf2X2YyUMUZeKq3xsB fasJoRyBzinIWgDaLoDec5BPiodjutnXi3//auISnwUbmlg5Z9fp2djEa8YJAhehgxID qwdplZGQdFjp30XjCTaVOpODzpuY/XJ/42JYRBOOxacyEDmermxYxDnWhEO6vzFo/oSU bxng== X-Forwarded-Encrypted: i=1; AJvYcCViDxfeUmYrfEFXslDOP9LqI59OAMzt1pHzQPQgzgTxVn1g+7Qdxhm6pwssK2EAI6jGsWmNlBIwpKak@nongnu.org X-Gm-Message-State: AOJu0YzlOVqW4KQnoJMW0/oESdSBeAXsKmcCKvA6YX9/Bnk5o+t8cAwT kOJD3FE9z21/89iG5LjGe4dUP+r1lMr6BuNC7Qs2MqVKON50gbHzJXvga4logcA= X-Google-Smtp-Source: AGHT+IGHZCPTq1Ky+i+zPEHV6OGPnrLZhJwIFC/QHlQ6UaCQcD+MtO44ZWUI0dTARLdzbNxkS3YCfA== X-Received: by 2002:a05:6000:1f8c:b0:37d:4a80:c395 with SMTP id ffacd0b85a97d-381f186b313mr17332647f8f.21.1731546817266; Wed, 13 Nov 2024 17:13:37 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381eda05f89sm19611165f8f.98.2024.11.13.17.13.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:13:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 01/24] exec/cpu-all: Include missing 'exec/cpu-defs.h' header Date: Thu, 14 Nov 2024 02:12:46 +0100 Message-ID: <20241114011310.3615-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TARGET_PAGE_BITS is defined in "exec/cpu-defs.h". Include it in order to avoid when refactoring: In file included from ../../system/watchpoint.c:23: include/exec/cpu-all.h:356:19: error: use of undeclared identifier 'TARGET_PAGE_BITS' 356 | QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 45e6676938..1c40e27672 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -136,7 +136,7 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val #endif /* page related stuff */ - +#include "exec/cpu-defs.h" #ifdef TARGET_PAGE_BITS_VARY # include "exec/page-vary.h" extern const TargetPageBits target_page; From patchwork Thu Nov 14 01:12:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A39A6D637D6 for ; Thu, 14 Nov 2024 01:15:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOQf-0007VH-SE; Wed, 13 Nov 2024 20:13:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOQe-0007UL-OJ for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:13:48 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOQc-0001wn-Rs for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:13:48 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-431688d5127so1010245e9.0 for ; Wed, 13 Nov 2024 17:13:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546824; x=1732151624; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n4W2o+WVI2EW3XsW3lSsIks/9d2PO57Qya5v8Q7poU8=; b=LitgoMJUmq+gqemI4ODNsD9dB2joc/86+4Bm4D55FpaYIq3e1DyF0VyRTlNoPlsy5I qQ0v0P/SnY2dSch4f0h4YQfTZ7HVqsVyAoFY1PiUPiO5qrrF9CT0scM1L6TRsBCEgvaa bSnKWelY7q7pO5Y3V10Nr/TJpT1DDAdlnFQCWKkwZUz0Ylz2LHUaA4jRfI02gq1juL1A FKsb57f07L1k9Lc23Lk+5cwF9tgKFMZy3DBA2aZoL2p+0WW8GGQBFEw/rkRs8xOv/3n+ BG1pqZKtSQ285vHI2z+8Q1Ul7tPPCACfnz6RNuNlOgbGbbxgdIjBkBMmq+JqeOZM7r+2 /KkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546824; x=1732151624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n4W2o+WVI2EW3XsW3lSsIks/9d2PO57Qya5v8Q7poU8=; b=at0C7+Rro6qNY77ScRBF96m9aWKoWpsHqkubFR8cESEjMeG++gIOGbhza4e+dDKmX+ NoTy+evfvb+39zjT3foUQ+Jx3jE+tnTodktDvIBT1q3TBf2hI98rmEDprqfwM+8GxPIg psW/deQ/cW8fdcqEIQdTWMkoSTivTqzSxiHqBnE2vk+0Wtj3Hl6hg3YVM8fdv2jfam0G 55M1BvVxKxCnZOofcetX65RrXKL7BIac86AhrgJSwVLBGALYth9f7qNCWA8yGR4Ha7gC 1tsj2STTI9apixjqB7eecn3kDaz6sgPu9Id+1nHBoI/DbkG9i9nmwvstu0zHqFn5FRwm nVOA== X-Forwarded-Encrypted: i=1; AJvYcCWLxUZADKrBTj9Zstxhx1tExxC5dhbQX2d0Kf7iKUBpU8Bmlt9ywa1/v898PjTAgEIgEre2h0J0Y/LL@nongnu.org X-Gm-Message-State: AOJu0YxxKrl92poAi1G5MWL6UuQxwNHqWUii0Y38oi6YPUhezYnxlQT5 asyitIEUDqizqopuIrdKwNREriTT4bGJ7dKORsrkPFHdtolQnpBUtfJ4vYVR6oI= X-Google-Smtp-Source: AGHT+IEicPSPnx9VguO/9hRNFn0r+OGPnyAza34mmQJUkip7pZQ0zwk7xapErhg7/qyCllNdtkSLxg== X-Received: by 2002:a05:600c:3582:b0:428:ec2a:8c94 with SMTP id 5b1f17b1804b1-432b75035camr195067265e9.10.1731546824041; Wed, 13 Nov 2024 17:13:44 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab721d7sm1548395e9.9.2024.11.13.17.13.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:13:43 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 02/24] exec/cpu-defs: Remove unnecessary headers Date: Thu, 14 Nov 2024 02:12:47 +0100 Message-ID: <20241114011310.3615-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "exec/cpu-defs.h" should be kept as minimal as possible; besides these includes don't seem necessay. Remove them. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Tested-by: Thomas Huth Reviewed-by: Richard Henderson --- include/exec/cpu-defs.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0dbef3010c..ae18398fa9 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -23,14 +23,6 @@ #error cpu.h included from common code #endif -#include "qemu/host-utils.h" -#include "qemu/thread.h" -#ifndef CONFIG_USER_ONLY -#include "exec/hwaddr.h" -#endif -#include "exec/memattrs.h" -#include "hw/core/cpu.h" - #include "cpu-param.h" #ifndef TARGET_LONG_BITS From patchwork Thu Nov 14 01:12:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D234D637CF for ; Thu, 14 Nov 2024 01:19:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOQm-0007Z7-IF; Wed, 13 Nov 2024 20:13:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOQk-0007X8-QD for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:13:54 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOQi-0001yA-Ou for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:13:54 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4314f38d274so1272565e9.1 for ; Wed, 13 Nov 2024 17:13:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546830; x=1732151630; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5KW25vJBxhufCYPIMuRXQYWgykya5onuISdgtY2NESM=; b=BXCGhH1z6w8k5PQT6nBpqrxvkJ/+Ys2CUVoCDAx/jrBXMAWHIInNkvTw5c9dwIbkv1 riOKJe9YAPjcKhz8pgaTx/wry8uftqtXxKTnyTbXKDWN2J9YhgG4Ts2w7SR7Kuc0wqkL GMNA6hOiOKZM6ns1CXn31E04lAZlW/k7hZwc/d623TjkO2zNtyEW9NlJ1LTJqCk/x5ml vYCytQCkSJ8jL8Nv6gUg4Lfi5grE+Rn8FDrvfmaWDy2BkPf3PCdbyr3hQolRCemzbBg8 JSqhCxCdhEk19+9KN5QHpr52R6SiLLZIwQ0cAWjHpjGhaX0H4yusvi83Tcd/h2WJ7LhU 1rjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546830; x=1732151630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5KW25vJBxhufCYPIMuRXQYWgykya5onuISdgtY2NESM=; b=DwLS0XhRPOJ1GfTFliro0psWrdeBGpKr77c6MW7NMB4Q3Yb3xPkIamO5uY2O04N1Dx E8J9NyQX0vFSVysrdvxv7OsqSlpbel6psy5wAudnfxLd0QXmxu38bXEF0ULYIJEwfHbY gHL7HKv36WIKLLCvTG9NaiQD4f+RzSYZnCYwZwB4yZ4otnVB1JLnAdvCGCEtxf7CpywL 3t6Kn6CASdcIz39xQ2nFsmOGyPJIWGp/BWcQ6hvWqYWWa1GTHBZ39M2XVFBfE9l83ZLl RqDRhtMPw7mhUPzPGWEZdovAgS+83aVI6lgB69fmJU5jqV/JaRhEG+WT4LO6OWmCtvXr 23qg== X-Forwarded-Encrypted: i=1; AJvYcCXeNc2Nvp13fHaxgE5JZmlGXdmKXGnsl0b83kiZDbxVOBoTPD7gCUnhXRhU4nDwBu3BD4ONLuLuvI4o@nongnu.org X-Gm-Message-State: AOJu0YxmTrbEkJOoQOriYNBpw8l//Y1BLBmDBdPn0sS1bTvLtk9DFONX FnqCrfjHsdou9uyxoDhX1QvIS7Q1u8pc+fY2xlzV9DGSIzkKLsjEtg1GmQ0aOE4= X-Google-Smtp-Source: AGHT+IEC5JlJku6XdBSAUB2qj+Uz9Kq0z6gAZgWwRK2JCMYVh8ykSi7sKBQbjuLQEYGTHDnr+1RcEA== X-Received: by 2002:a05:600c:3d16:b0:431:5c7b:e939 with SMTP id 5b1f17b1804b1-432da790770mr2673155e9.18.1731546830113; Wed, 13 Nov 2024 17:13:50 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da298c97sm4649995e9.40.2024.11.13.17.13.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:13:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 03/24] exec/translation-block: Include missing 'exec/vaddr.h' header Date: Thu, 14 Nov 2024 02:12:48 +0100 Message-ID: <20241114011310.3615-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org 'vaddr' is declared in "exec/vaddr.h". Include it in order to avoid when refactoring: include/exec/translation-block.h:56:5: error: unknown type name 'vaddr' 56 | vaddr pc; | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/translation-block.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index a6d1af6e9b..b99afb0077 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -9,6 +9,7 @@ #include "qemu/thread.h" #include "exec/cpu-common.h" +#include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" #endif From patchwork Thu Nov 14 01:12:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81D32D637D6 for ; Thu, 14 Nov 2024 01:19:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOQs-0007dV-4R; Wed, 13 Nov 2024 20:14:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOQq-0007bp-Du for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:00 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOQo-0001zO-RM for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:00 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4319399a411so965915e9.2 for ; Wed, 13 Nov 2024 17:13:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546837; x=1732151637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X3oqMeHT71R3KdP9eZWoYcjlbOfOwEShX9l191wOq00=; b=n4+c/Fvo2dTX3JgaWSwTpv64eiLSaVvaJWy5x1ch0LlFGH6lVN/T2LLpSPUEHm2vd3 KULM1pv/8+TtEa4mheq2m/+QcoUPy78jZr3Gxg65p1UcwwKaEluP/yha0GtC8hdTRped +34trvYpmLM6Lrei/Zz9+D42M/xcKAkxTM72CnVg6ZC8FKBGmDTfyjp6iRAlUho1aSMC LB4GsQvr9NPKK2Qmsjt3HAM1Z9pnjgdFaGlcq77pWBqYrzcqoeuQ3xlDaTTTzaVjQUVx ue4o0hjUNgB23SOmv4Z0yR1LBt9AfmNm1vQtnuIASaIzOKuuDxc6BjGnByPHgKebmxny wLTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546837; x=1732151637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X3oqMeHT71R3KdP9eZWoYcjlbOfOwEShX9l191wOq00=; b=wl8FDGegvSJY5TO4IGCumR4FLCr3qLr649cldO+Iu0Ct0qrftJ/4o36LXppoJjSOXC xQkU3+KuaqTLHsVQ15+KRKvpPivRDI7iV1nkWWaA9+UKX4znnMhFTjUvsqNXHJVmFSvO ibgxwRgpFsyfzzvOfwoHjEpIcUgjzpsPp5wZ97hQfQiIX9OOjZ2fDNPLjaRjG+R5VhOP sDmtXODhcShY0AFhxjx5G8nrWu+tVET2m271j0wZgGMIINMrLNGhczwQPZUJXl6S4TC2 1sfre/opF+C8oD5KLPVG7OC1D2g7UCehe1CDy5cq9J1gVo+cOWDu9bz4C/ioqEf3QT8v 7I8w== X-Forwarded-Encrypted: i=1; AJvYcCUDBB8rHc8bCwigXfRSBPn5cXsiDya4O0a+K/2T9psT2BfjLeg4nh2WLXnivSeuQszJ2PyFgHmuFYVi@nongnu.org X-Gm-Message-State: AOJu0Ywo0bouQZXpXgozEgROP0gdp1yK6RM10+HBoU3A70tQCpUZMvFl NA+SiqWRHvqhHCd0mCfQfmNvAtYzLL30tRxIABOpjsdsGgL3z8LCxOmsds5zpmw= X-Google-Smtp-Source: AGHT+IFH/9CySRShC94nFw9UunKX2sRCoFuNlkS4DCoQU46r6V+s7M3YfRcJ8MxE5SjH5yjXwvy3Zg== X-Received: by 2002:a05:600c:a384:b0:431:1868:417f with SMTP id 5b1f17b1804b1-432d2730ce1mr69929325e9.17.1731546837008; Wed, 13 Nov 2024 17:13:57 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac0aea8sm1385325e9.31.2024.11.13.17.13.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:13:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 04/24] accel/tcg: Include missing 'exec/translation-block.h' header Date: Thu, 14 Nov 2024 02:12:49 +0100 Message-ID: <20241114011310.3615-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TB compile flags are defined in "exec/translation-block.h". Include it in order to avoid when refactoring: accel/tcg/tcg-accel-ops.c:62:36: error: use of undeclared identifier 'CF_CLUSTER_SHIFT' 62 | cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; | ^ accel/tcg/tcg-accel-ops.c:64:26: error: use of undeclared identifier 'CF_PARALLEL' 64 | cflags |= parallel ? CF_PARALLEL : 0; | ^ accel/tcg/tcg-accel-ops.c:65:34: error: use of undeclared identifier 'CF_USE_ICOUNT' 65 | cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- accel/tcg/tcg-accel-ops.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 3c19e68a79..22486c5dff 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -35,6 +35,7 @@ #include "exec/exec-all.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" +#include "exec/translation-block.h" #include "gdbstub/enums.h" #include "hw/core/cpu.h" From patchwork Thu Nov 14 01:12:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2807D637CF for ; Thu, 14 Nov 2024 01:17:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOR2-0007g7-4G; Wed, 13 Nov 2024 20:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOQy-0007fg-Fn for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:08 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOQw-00021J-Es for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:08 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-38207c86695so90421f8f.2 for ; Wed, 13 Nov 2024 17:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546844; x=1732151644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hctc3S/tg6amAjvlXZaTioZ5Yr338cGDDSPzRbh8Ywo=; b=vdmf4X3RwQzuywq2vM1eg7M7uUvpjcBujgcE0tO8OY4/uqEjWIICIc2+7OtRn9PL09 E4sXWIMeQAdOH9ClLSukEYTj8pjP0FfEA947E/fw9hMcB7scBa88ldt3Pd/RxjcdCRtl u13YutO51RF3tVTG2fUdgCrOX4GPijgcPU4bf9G1vZoRPtlRWNRdtXcCrW0T4q+7vlWG uv+J459WW4mi4r02ej+vi/ob4uLX9pj+0hHcdMAsRZhwCIoOLGDOIhpIjXO7hkpod61G UQFKDT5OIa9rveybUQ/L5Pg8GF0OBS41cWiP8U+OAkZdI7kp0mQSfM9TVeZo6z3CHUdl 900A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546844; x=1732151644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hctc3S/tg6amAjvlXZaTioZ5Yr338cGDDSPzRbh8Ywo=; b=BFgBB4dq5d29J59WS+qy7e34+vl9tk0oCUjC0tu0WSTrXLjEakX9U93Q7mC5vK9Pf8 HzKOPkvU0sNxbrtBHH3xZuF+53LVzKifvH0MwzcM1Gz/3dHYniGlsatQOb33+WC06QCH PoO9g7cHhG47YTGHYpcwNKy4YLcN2/aO3a42Lpop5BwqwYj5SP0nyAxdxrh3IpRYs/fM f1nUTbwONvatxe3rZqr/GhDW1i2k/mvanI3Mi1kiWASopckMvF5hq3DCLkS2iguDaiuG itSn0OTFLNLYvpHqsrgyOZYHMHqH9aGXT+Q4CuNJJe2O89r+dZy3Mos9C5BF6fMs4TjD SFIw== X-Forwarded-Encrypted: i=1; AJvYcCVnjvzZA+uZiebdIBhkKdvG86Z+aCghZJv0QqIDzdIcQbNYgC8Oef4iUBVsdhV/v0WltTrtQwyJKmXk@nongnu.org X-Gm-Message-State: AOJu0YzYtvZsRVIxBx1ZG9B+FMj36mr/KIPOrk4xeBdTefPh8rd9swuR xXxieuBY//N9x6KDPhX3DSEnz6TJOKU7u3GyCpkwzIy4C46JKPiBWWkX+YcdLKM= X-Google-Smtp-Source: AGHT+IEn2so/ixH18AvrpdZMy3nJh7glbi+y5QwToKvNKI1CwZqSHbNiU7EXqtTNTTpXjuGdZdx7cQ== X-Received: by 2002:a5d:648b:0:b0:37d:47ee:10d9 with SMTP id ffacd0b85a97d-381f1873485mr19654057f8f.34.1731546844586; Wed, 13 Nov 2024 17:14:04 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed97e46bsm19427592f8f.30.2024.11.13.17.14.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 05/24] target/i386/helper: Include missing 'exec/translation-block.h' header Date: Thu, 14 Nov 2024 02:12:50 +0100 Message-ID: <20241114011310.3615-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TB compile flags are defined in "exec/translation-block.h". Include it in order to avoid when refactoring: target/i386/helper.c:536:28: error: use of undeclared identifier 'CF_PCREL' 536 | if (tcg_cflags_has(cs, CF_PCREL)) { | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/i386/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/helper.c b/target/i386/helper.c index 01a268a30b..75c52e2143 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translation-block.h" #include "sysemu/runstate.h" #ifndef CONFIG_USER_ONLY #include "sysemu/hw_accel.h" From patchwork Thu Nov 14 01:12:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C29DD637D5 for ; Thu, 14 Nov 2024 01:16:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORG-0007sh-Gd; Wed, 13 Nov 2024 20:14:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORA-0007lt-8G for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:23 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOR4-00022X-6e for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:18 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-432d866f70fso952015e9.2 for ; Wed, 13 Nov 2024 17:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546852; x=1732151652; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YzuvHkgFNpoK/g6N/GhAbq9D9bCDxAJSB1ivyjDA1qE=; b=aQnfWdM9oUqbizCzYhJjNbp8xrFa9/tb4ZWqmgHal3+yBBjYNABz5XiRscg5VcdRcs ZRBaEqzw8j9k16cudcI0ZxdJANG3smrjOFEOsnmf2zIMAO8G5xjQNuKXS7k+tMtAimqB MUeIA+isXQhcvk6SFGvgr5ocv+8hWYfjhvhKx0rhLTx3Snw9tfwyI0c4DGuswcJVIevv MF8psvDNJLq4hlcdzUkB6L1OwnARYLtxuo8iuxxR+Lujs0MDgbv3EyIw4giX7Or9ORop qwYg88kWc3+rla9uVJWQht+omGJ3WnZ6zwqztwQklvk0IXtWl3r5b66xDlInTHw5f5ZK 2www== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546852; x=1732151652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YzuvHkgFNpoK/g6N/GhAbq9D9bCDxAJSB1ivyjDA1qE=; b=bl9c/dsEQ+OR4Zx3Nm+ZPFseNO3RnMuEFWNSMJ/lCNWZ2/Iw0fw6/W2X+dXASDgZhm tzSpQstwodTaDzpo/Pdi0PWhmzbtjMH9EmyUc2bLbX/kgOvLD9cPQ4EfRQB0Sm0OjXL2 7gHn7C7BznjFZnJLKACkqBBh5JNtiqaOXRHTIzGZZrqGIXYKhWksM/R2x3BUjL8LGWDt wALZqZ5pvuau2IvMT9iw4yQOZ1Gr4An6PwiIak6uxcrTV75iJwT60/oYta21WPZVokAw f+KCodHvATEQtgUi82uxZOMSBXm5f5lBnCSf+IOTHXd/0gXB8wiAYuoAQm/PDxs0BCC+ fkeg== X-Forwarded-Encrypted: i=1; AJvYcCWa1OjjnZCSOZSJ7j5bSca/wqISpyPLCfa5CSjEu8ELRpebyprKelTaJhq5hpZOeTJxOOkHNATqy0h1@nongnu.org X-Gm-Message-State: AOJu0YzIlVy+Sueeu6QDBDgDvVtAnc1itn0ipMgMxwXOg+iqikcSRMSg uPnr1Ac5okHDKsmKbHGhRGMzkKQ6+N6t+KiVHkWGgDzXBdYapSPzZLqqefLvJas= X-Google-Smtp-Source: AGHT+IGEpPcB2Ra92T20v+BX6rXD4nwtmCydz5vInWSdcDRLMyfilK5Pfw6s6wv0d0N8yzY4Z7WyWA== X-Received: by 2002:a05:600c:19c8:b0:42f:7ed4:4c26 with SMTP id 5b1f17b1804b1-432b75002b7mr202791785e9.12.1731546852174; Wed, 13 Nov 2024 17:14:12 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab78881sm1520105e9.13.2024.11.13.17.14.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 06/24] target/rx/cpu: Include missing 'exec/translation-block.h' header Date: Thu, 14 Nov 2024 02:12:51 +0100 Message-ID: <20241114011310.3615-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The TranslationBlock structure is declared in "exec/translation-block.h", along with the TB compile flag definitions. Include the header in order to avoid when refactoring: target/rx/cpu.c:50:42: error: use of undeclared identifier 'CF_PCREL' 50 | tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); | ^ target/rx/cpu.c:51:21: error: incomplete definition of type 'struct TranslationBlock' 51 | cpu->env.pc = tb->pc; | ~~^ include/qemu/typedefs.h:116:16: note: forward declaration of 'struct TranslationBlock' 116 | typedef struct TranslationBlock TranslationBlock; | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/rx/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720..945ae6e9e5 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -23,6 +23,7 @@ #include "migration/vmstate.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/translation-block.h" #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" From patchwork Thu Nov 14 01:12:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 79BE5D637D5 for ; Thu, 14 Nov 2024 01:16:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORI-0007wl-OR; Wed, 13 Nov 2024 20:14:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORF-0007qO-48 for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:25 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBORD-00023g-5p for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:24 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4315f24a6bbso946285e9.1 for ; Wed, 13 Nov 2024 17:14:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546859; x=1732151659; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IkMAKYtUsFK+2kHSHv5+o6ejmYyvsynMitsyE7ErdJE=; b=nMTLgNZuUNokikg1kST+CcEwOA9jPPKQev18C1iXymHiQo4wI+f+duzowWZTOG2/Lo jMdsxKkDYi/yYqyIbjzxlIyeQ4tY3mgmgXjolTw1gI2ZPwkVstBEaLGmzowFNjLGtIuP 4WXRbWqz8G9UdRpc5TdnVD48c9JBowxuwbpfGL0MKLAQHBPRIGU7rR3nCjlx7kZ8zgiL xAWaKSZ64ZqymV/IOxdo/m2xY78fbxtlk6rRBhuLhFfhttSWgHuRc2D5VaZsOIdUMUaE VXxzzj7QqwaWhgtVm0p+oxEaK01/BXXbyI+3FHo5duwM+auSM5S8bdveHTA/SgLn8X8U zMaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546859; x=1732151659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IkMAKYtUsFK+2kHSHv5+o6ejmYyvsynMitsyE7ErdJE=; b=GoCFchnCjDAKAwJ8urWncFkq2p9K+gtE0qZiUlqvs20TTiO507hZxKzP5LFtEwCLAm 63CiH/0JFQJ4hjPqaUtsr4ZtDIxZ+8F249zpTppwxntTn0YxfSAI5Zv5n62vnfQTHJos uYdhEL85c3FuyLdZde6wf34Z8QM8j2yFjYLk9PsMYpUfINkM216R/KTRslyNK2LmIpj5 XU+rmZXXFeVIQDt7G78Tv92q6InUMBoyoNn1QhXjSk7W36tObrKOiGcZBIEkfEUJfGLm K7etUQdL/FAqMPJhL8Hzxy1A8pu+6GkKtkFdh+nqrpbjA980fGp4UWdVigC50X14FLuO THaQ== X-Forwarded-Encrypted: i=1; AJvYcCVJEIpzL4fDX48UGj7/7ZeNptFlvwcmv4j0c4sHA2c5ICfxHr2MEF4RA+nQKLPCo3JktphXsEE7Ifkw@nongnu.org X-Gm-Message-State: AOJu0YzmkgV/BMp8cRH6pbtfW4xn85OgfQNI2eUo6xvF1SkJMvfRWq9O vwMHqx/P28gFJgx8ernIq6v5nOlZlnQxomCMB2js0b2SpmzUOfLParrgnuLGZeM= X-Google-Smtp-Source: AGHT+IGq7l4w9ev6D28X1Yepm7vUOOMFRow8CZfJhEURSVFhxjg71fxbtKf1kANyx9ZamVx3FRm1Lg== X-Received: by 2002:a05:600c:1d20:b0:426:5e91:3920 with SMTP id 5b1f17b1804b1-432b751dec4mr186860785e9.29.1731546859011; Wed, 13 Nov 2024 17:14:19 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27f4f8sm4766295e9.18.2024.11.13.17.14.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 07/24] system/watchpoint: Include missing 'exec/cpu-all.h' header Date: Thu, 14 Nov 2024 02:12:52 +0100 Message-ID: <20241114011310.3615-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TARGET_PAGE_MASK is defined in "exec/cpu-all.h". Include it in order to avoid when refactoring: system/watchpoint.c:52:24: error: use of undeclared identifier 'TARGET_PAGE_MASK' 52 | in_page = -(addr | TARGET_PAGE_MASK); | ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- system/watchpoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/system/watchpoint.c b/system/watchpoint.c index 2aa2a9ea63..f7366574a3 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "exec/exec-all.h" +#include "exec/cpu-all.h" #include "hw/core/cpu.h" /* Add a watchpoint. */ From patchwork Thu Nov 14 01:12:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C731D637D6 for ; Thu, 14 Nov 2024 01:18:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORM-00080w-Q4; Wed, 13 Nov 2024 20:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORK-0007yw-QT for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:30 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBORI-00025Z-7p for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:30 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-37d50fad249so77988f8f.1 for ; Wed, 13 Nov 2024 17:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546866; x=1732151666; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OzDo0drcf+l9FI9MFOgWksxtiPTKy7V4t/YiPF1FVxo=; b=xDaKBRynSr8JeDchNRXFzlr5P4Up95Wdv+eHiQ9jC66t08D5310uyNgC4Omw+ZX61O BGz6AH0v6qQjF5lEfA/lc2fMYunHf+AK370mDhqDvhPPqUUO/50hw7HncwkOgFI9fsVU M6GxGA3GvrGBDmaG0SkkV4/TZGbsc7HKRYIFw7bbej5PY5sPFmdkA03vDUGt+FczBi4j YhMO4jiUyYhm3MhZiOu2+AyRJ3jCwoMNz/iWStLyRif5riDAGZX6xi6UYNJy+LjzvKbr 1I5cQcoIDTlwrnhjaYYP1ynjrt8zMUW6dtYkRY+C+owL188HVT5CERjoCX89sRvLKJCj Ng0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546866; x=1732151666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OzDo0drcf+l9FI9MFOgWksxtiPTKy7V4t/YiPF1FVxo=; b=WPEbSPbTcnYtH8d33WOQtaQBP5AHQawTTTHorFyDnTElwlaC0W2gJm/Mq+jJGHwBnu BeXSBXzTgSYTvqjT/nFOVTtFjGWDrt94KvhD+aSAAWHePQGQ2bU2a9EC1N4tyI6v9CGY WVO/wwDvb5ROQNdjvLZSVTtcHnPr4U+Mz4/nXMeBCCYNgJlcCeggZc0nev593QR7kKc8 63yCVHkKew99YwOQT6KTlU8VkbYp6mojFbXkJTSWoPuvZUZQ7kUOADgEUVwamBtyod4K 2vgBOjgiB8GoCgqDA4+J7cEVUjlwkaP4FJhp/2NOiJwRmTuzPVDhpi4XINddlFebrRl2 itXw== X-Forwarded-Encrypted: i=1; AJvYcCX1VafjC4i8R4/zVaptcJRJdps+S5CvF3YSKbWFAEpMD5wzoPq95WFML3MWUhJN+34nu0AT8nof03QY@nongnu.org X-Gm-Message-State: AOJu0YzO2LacJdYRGcgYBteLe7CVTzeet8NFzIyJ9w98M0ffbdeaVogf gW8rs2rZUnzzwROBWS6qTSbe/JmCfd9+03YwyOv2DKNLoLyri0ntM9Vl0Qv02Uk= X-Google-Smtp-Source: AGHT+IGRAvO0UPawK2zfcCGO//9i8AmO6U7NK1zJgE+Z8dy6kuyS/IdN4ms2Ng8UXNa65KniwwxN/Q== X-Received: by 2002:a05:6000:401f:b0:37d:3e00:9a9b with SMTP id ffacd0b85a97d-381f186cafbmr19128225f8f.20.1731546865946; Wed, 13 Nov 2024 17:14:25 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed970f68sm19860449f8f.11.2024.11.13.17.14.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 08/24] linux-user/aarch64/mte: Include missing 'user/abitypes.h' header Date: Thu, 14 Nov 2024 02:12:53 +0100 Message-ID: <20241114011310.3615-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org abi_long type is defined in "user/abitypes.h". Include it in order to avoid when refactoring: linux-user/aarch64/mte_user_helper.h:30:42: error: unknown type name ‘abi_long’; did you mean ‘u_long’? 30 | void arm_set_mte_tcf0(CPUArchState *env, abi_long value); | ^~~~~~~~ | u_long Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- linux-user/aarch64/mte_user_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_user_helper.h index 8685e5175a..0c53abda22 100644 --- a/linux-user/aarch64/mte_user_helper.h +++ b/linux-user/aarch64/mte_user_helper.h @@ -9,6 +9,8 @@ #ifndef AARCH64_MTE_USER_HELPER_H #define AARCH64_MTE USER_HELPER_H +#include "user/abitypes.h" + #ifndef PR_MTE_TCF_SHIFT # define PR_MTE_TCF_SHIFT 1 # define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) From patchwork Thu Nov 14 01:12:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60A29D637D6 for ; Thu, 14 Nov 2024 01:17:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORk-0008Pn-3H; Wed, 13 Nov 2024 20:14:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORR-00082X-Fs for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:37 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBORP-00027D-D1 for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:37 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4315c1c7392so993885e9.1 for ; Wed, 13 Nov 2024 17:14:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546873; x=1732151673; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WwdhRXN0joprmzKwfGffR3OdfbOtF5yrdb8wFJrdlRk=; b=rTYxEk/qxNbE/AyiTlJfOQ88rnK0CdC7ZmU9ZgXVb8m0CRJjyGhM/KwtPgKbNz9klU HpNkbCXOK1E07G74Cx2ZnNEqAEGlj4bx6IVKAAdKX/NpSR/8Ghj2E/+JLpzxE4ACXQIu O/Co+04xnhlDNeQr6oUS4VXOERo9UbArcoR7Fs1dLLbF49K/ZW4yMLxUI2/lnN52cr4w zsSerUIEXRtDofoSxX+7i7CAVSvZixwxioH8reTp/R1z60X8X+2o4ZV0lWlW9gRuJC1u OoUyUBoJuLA0eum5VeCsywbwSkQWANYZTY/DEd8auRtVBeZciupVd19+7wjA4LVsVfQU HVmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546873; x=1732151673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WwdhRXN0joprmzKwfGffR3OdfbOtF5yrdb8wFJrdlRk=; b=YNZ1uojRH4wn8J9mxMAAv22RNAo65g0tgtcrAP69r8PIjbGNsFKRodREKf1txBX9Dj ekv6v22LNA7tj+LPIq5HX5XdXRRXZa5N2pP8zd09DZ6K9elpEwP56mnkekGSpcV4l20R X/06VaC51sk0MdwikxrFv6IzUz8HE8rDTp4n/MA897iCpy/CHCKgix5fS6ISWRP4b/Uy 7/GDtNB2S8PCMO9581SWHrD0bKocLZ7VUrML2andLUz/zNJEdJzbvTvlCRMq4fW1xT/B eLLYhQQ7dN2AuPZpXKCxlR8gdJ2d2bdVEmcceQl2LyW3vB3CTUHsrWIw4YDNffoQVcck wpQQ== X-Forwarded-Encrypted: i=1; AJvYcCUNIvcoGcz4iIqweYbronS34SvKvI1YyQRxFVm8CK4+uUNEcTcF3CmBa226GihGrdGrjpFBCWlpj8Jx@nongnu.org X-Gm-Message-State: AOJu0YyQEJJ2R08oMaaKOqxVVScciHBP6e/oZWZ/EKN5uw3scuEY1Eif oEU9ztsoDUUXm5ACzpABpuCSQNFqIbm16Dz8hg4MDV/J1puGf2f6/YPMNVUIHuo= X-Google-Smtp-Source: AGHT+IE3ms5xpjQHGWXmVlg3v8W+KzlHKEnbriHG+Xzyq9cJJh/6mR5hbnlsDRfww5BsPv6tn+pTYQ== X-Received: by 2002:a05:600c:1d1c:b0:426:6308:e2f0 with SMTP id 5b1f17b1804b1-432da7cbcefmr2174995e9.26.1731546872750; Wed, 13 Nov 2024 17:14:32 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432d48baa42sm33170825e9.1.2024.11.13.17.14.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 09/24] target/arm/mte: Restrict 'exec/ram_addr.h' to system emulation Date: Thu, 14 Nov 2024 02:12:54 +0100 Message-ID: <20241114011310.3615-10-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "exec/ram_addr.h" contains system specific declarations. Restrict its inclusion to sysemu to avoid build errors when refactoring. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9d2ba287ee..b017b26d07 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -23,7 +23,9 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#ifndef CONFIG_USER_ONLY #include "exec/ram_addr.h" +#endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "hw/core/tcg-cpu-ops.h" From patchwork Thu Nov 14 01:12:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75708D637D5 for ; Thu, 14 Nov 2024 01:19:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORt-0000CZ-Le; Wed, 13 Nov 2024 20:15:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORY-00089K-6r for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:48 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBORW-00028d-6l for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:43 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-431548bd1b4so890325e9.3 for ; Wed, 13 Nov 2024 17:14:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546880; x=1732151680; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Yi8oP/SEa8RdfPU0nVwuwaNWFqTgpMIdFqeiug4H/W4=; b=rfKfcX4JG07JMQDwwX+3GX4bIiEc2cze1LGAirRp3nriSbzvcuR2nLxcbUKapyQQcH lji8QagYzwRq4N3gD45ZNk0vtPsJ97rCk7TODdVBF1wF6JtEKwlWC+Yn6vql7eKVCxbg JsZaK7QWJE9UTaj9Atkr48aCAeNDp2eXibOnpu+dO0EyU0U4O4BcZ4gnrikAEd+EawSK ZGiNwnK5tVFkrCEeNsZAEUiqnyLWEf40s0s6jrFfUKSGTgHVoubDe2NNU1heDAU3FP/b ETwe/2eBrif4B05Cw4kDr3I62oj0cN4YNHfJLuChxIWBdzfE2RJRkrBWf6sExSgEsXM8 q/7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546880; x=1732151680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yi8oP/SEa8RdfPU0nVwuwaNWFqTgpMIdFqeiug4H/W4=; b=vfJoj8CO8D0IRvcZdn9/V0Qj0wev4JgNoXftdXWOOas4teMamgBpVMDDCLW7aYqWGm m/jtMYIcxvmL+jSVYnb/bkpcJrgsoXVmtQ/gya45AqcXLA1qnBVyB70f9oE1XNCG2unk yHCy0N/Zm6QIVh3fhw1wAtlyEzJNJWY9/SZEM+YMyW1f/5yXZJ0qta/CthQihcsaRuR1 ruI0zXwAJoY4ZsZddCLWd+sjg3cGKThsdWOjqqkRKH3CeQjrVpijgL/atqUYPVOBqtrp ipI2auGI97DnX0mfIdFBlEHIR5pgjqfC532PBnF8MK6jFwQF7yVHXD6YMPM3VmtgYUfV Ppew== X-Forwarded-Encrypted: i=1; AJvYcCVHQ2IhWLAApK3yhDt7SxGiUZ1SNerJbXZQGUEFmX1hQ2A/2PAjtUUIJZTfs3CRsdmxkwbHcjHQuuys@nongnu.org X-Gm-Message-State: AOJu0Yy6jb45gCncsJQ93j5GToc8s4AtxZ1iqz8NCyjcZgjHBvKSUWQ0 0OwuUYDI5lA1ALCg91YW+p5wG69/2d/datuw2B9OUxakiYdnrKXVhVXS/NUAb+Y= X-Google-Smtp-Source: AGHT+IHshN65SEUSiXRSla/0TLQwOrSSZwJsNVoNHIKZKVGyfpL2AdokvGedv4UPA15Nq3l2/qFYYA== X-Received: by 2002:a05:600c:384e:b0:431:3a6d:b84a with SMTP id 5b1f17b1804b1-432da767a27mr2552595e9.4.1731546880412; Wed, 13 Nov 2024 17:14:40 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265ca8sm4806795e9.14.2024.11.13.17.14.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 10/24] target/arm/cpu: Restrict cpu_untagged_addr() to user emulation Date: Thu, 14 Nov 2024 02:12:55 +0100 Message-ID: <20241114011310.3615-11-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move the #endif guard where it belongs to restrict the cpu_untagged_addr() implementation to user emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d86e641280..12b8466542 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3355,8 +3355,8 @@ extern const uint64_t pred_esz_masks[5]; #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) #ifdef CONFIG_USER_ONLY + #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) -#endif #ifdef TARGET_TAGGED_ADDRESSES /** @@ -3382,6 +3382,7 @@ static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x) } return x; } -#endif +#endif /* TARGET_TAGGED_ADDRESSES */ +#endif /* CONFIG_USER_ONLY */ #endif From patchwork Thu Nov 14 01:12:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94618D637D6 for ; Thu, 14 Nov 2024 01:16:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORw-0000Nn-LP; Wed, 13 Nov 2024 20:15:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORi-0008Ly-BG for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:55 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBORe-00029z-NX for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:53 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-382026ba43eso73396f8f.1 for ; Wed, 13 Nov 2024 17:14:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546888; x=1732151688; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b/Mwf2dMLIwY53Hwy+X6Y1uqRqRvCrR6xhY52hogfuU=; b=vvEQxboJFU8COX+Da+B/7SrRCGQSsmSO/mWq+PvuFHjPm+ysEVGKKCo+19vg+G6jE9 Gp9lXvBqEuFq0E4neXdYfTATS7/RoTss/o1loHLNooIDOhqUi5KkYUT/Oay/chG3soIU zp+MOcKVeWpg0+Bj8+QdkOe1me00R88Y8OZQLb3YyU8k2zKjlYE5OfVpzXd9UpdLNGn3 845jKDPMlwQbjKCHfbTKpaPjDRP5NMpduZq5fS6kDPK0oiA8SwxqfNieCrpuqTDoXlFD XI+DsXVG6aKTG/W7hVPgE7N3hFPUw6Kg3vjknOOBzKQwBQudLBXhxWMUcZXe5Crt9Gyw 1oDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546888; x=1732151688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b/Mwf2dMLIwY53Hwy+X6Y1uqRqRvCrR6xhY52hogfuU=; b=akbolGs6O53l8320c87QmoO9KDaWc5LJhn4o+qKmLANktUAwrBtu73cn55IsgbjjQV aCxfnbFTyWsetdvYBUxm4DvY54yLus0OxiJMIOyMhRl1Cr/nsibtNnzcU60myeeosII/ 1IG+sUEuHDEdZlNxw83jzA4/pqPbgUvLFIMYYsS5HO6bi3U77jeuiArLx7QTuDpSUjyU ZaovbKUOi/QMoHoIlYbFq/T5UbBC3SUT1LrYogxNKnZEjXPK7A/UiibwiH7hVdaBqP5w hyU8FuochkcVyaeZ4KN/SwDtQPBAxWSaWWFft7ojMRv/zrDvkcmss499mOzEj56yE3k4 cLeA== X-Forwarded-Encrypted: i=1; AJvYcCVcPW8PXGUkHYk6SRcpsv3r6/iSos+nXacxChssSe9/BsJpnOPh9SbymL5M9ebLuvyebq+6miCPuETU@nongnu.org X-Gm-Message-State: AOJu0YybClxl2YK8d0ljynSVYrKaK9YaRvqIOVvm4PtL8QV3e5U1waj4 YU1gUVNB8g9lJcbLE/92ANTBQQnLFs+knJ6s8zldHYxwT2h8jtVG2BwR1ufpF7BHFUaBaBL15PN p X-Google-Smtp-Source: AGHT+IGYsjllJjcWqtSFLvVfioihKxt7KGt6nILKJp1/7Hyu2p6hwA9EsQJ1WMNsoFs9SnNIT8G0og== X-Received: by 2002:a5d:598d:0:b0:380:54f2:3408 with SMTP id ffacd0b85a97d-3820812360bmr6334702f8f.25.1731546888217; Wed, 13 Nov 2024 17:14:48 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed970d05sm20012547f8f.1.2024.11.13.17.14.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 11/24] exec: Introduce 'user/guest-host.h' header Date: Thu, 14 Nov 2024 02:12:56 +0100 Message-ID: <20241114011310.3615-12-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract all declarations related to 'guest from/to host' address translation to a new "user/guest-host.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 34 +-------------- include/exec/cpu_ldst.h | 47 +-------------------- include/user/guest-host.h | 87 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 79 deletions(-) create mode 100644 include/user/guest-host.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1c40e27672..1c8e0446d0 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -64,39 +64,7 @@ /* MMU memory access macros */ -#if defined(CONFIG_USER_ONLY) -#include "user/abitypes.h" - -/* - * If non-zero, the guest virtual address space is a contiguous subset - * of the host virtual address space, i.e. '-R reserved_va' is in effect - * either from the command-line or by default. The value is the last - * byte of the guest address space e.g. UINT32_MAX. - * - * If zero, the host and guest virtual address spaces are intermingled. - */ -extern unsigned long reserved_va; - -/* - * Limit the guest addresses as best we can. - * - * When not using -R reserved_va, we cannot really limit the guest - * to less address space than the host. For 32-bit guests, this - * acts as a sanity check that we're not giving the guest an address - * that it cannot even represent. For 64-bit guests... the address - * might not be what the real kernel would give, but it is at least - * representable in the guest. - * - * TODO: Improve address allocation to avoid this problem, and to - * avoid setting bits at the top of guest addresses that might need - * to be used for tags. - */ -#define GUEST_ADDR_MAX_ \ - ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ - UINT32_MAX : ~0ul) -#define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) - -#else +#if !defined(CONFIG_USER_ONLY) #include "exec/hwaddr.h" diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index dac12bd8eb..a26ab49b0b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,52 +72,7 @@ #include "qemu/int128.h" #if defined(CONFIG_USER_ONLY) - -#include "user/guest-base.h" - -#ifndef TARGET_TAGGED_ADDRESSES -static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) -{ - return x; -} -#endif - -/* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -static inline void *g2h_untagged(abi_ptr x) -{ - return (void *)((uintptr_t)(x) + guest_base); -} - -static inline void *g2h(CPUState *cs, abi_ptr x) -{ - return g2h_untagged(cpu_untagged_addr(cs, x)); -} - -static inline bool guest_addr_valid_untagged(abi_ulong x) -{ - return x <= GUEST_ADDR_MAX; -} - -static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len) -{ - return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; -} - -#define h2g_valid(x) \ - (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \ - (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) - -#define h2g_nocheck(x) ({ \ - uintptr_t __ret = (uintptr_t)(x) - guest_base; \ - (abi_ptr)__ret; \ -}) - -#define h2g(x) ({ \ - /* Check if given address fits target address space */ \ - assert(h2g_valid(x)); \ - h2g_nocheck(x); \ -}) - +#include "user/guest-host.h" #endif /* CONFIG_USER_ONLY */ uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); diff --git a/include/user/guest-host.h b/include/user/guest-host.h new file mode 100644 index 0000000000..8d2079bbbb --- /dev/null +++ b/include/user/guest-host.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * guest <-> host helpers. + * + * Copyright (c) 2003 Fabrice Bellard + */ + +#ifndef USER_GUEST_HOST_H +#define USER_GUEST_HOST_H + +#include "user/abitypes.h" +#include "user/guest-base.h" +#include "cpu.h" + +/* + * If non-zero, the guest virtual address space is a contiguous subset + * of the host virtual address space, i.e. '-R reserved_va' is in effect + * either from the command-line or by default. The value is the last + * byte of the guest address space e.g. UINT32_MAX. + * + * If zero, the host and guest virtual address spaces are intermingled. + */ +extern unsigned long reserved_va; + +/* + * Limit the guest addresses as best we can. + * + * When not using -R reserved_va, we cannot really limit the guest + * to less address space than the host. For 32-bit guests, this + * acts as a sanity check that we're not giving the guest an address + * that it cannot even represent. For 64-bit guests... the address + * might not be what the real kernel would give, but it is at least + * representable in the guest. + * + * TODO: Improve address allocation to avoid this problem, and to + * avoid setting bits at the top of guest addresses that might need + * to be used for tags. + */ +#define GUEST_ADDR_MAX_ \ + ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32) ? \ + UINT32_MAX : ~0ul) +#define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) + +#ifndef TARGET_TAGGED_ADDRESSES +static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) +{ + return x; +} +#endif + +/* All direct uses of g2h and h2g need to go away for usermode softmmu. */ +static inline void *g2h_untagged(abi_ptr x) +{ + return (void *)((uintptr_t)(x) + guest_base); +} + +static inline void *g2h(CPUState *cs, abi_ptr x) +{ + return g2h_untagged(cpu_untagged_addr(cs, x)); +} + +static inline bool guest_addr_valid_untagged(abi_ulong x) +{ + return x <= GUEST_ADDR_MAX; +} + +static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len) +{ + return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1; +} + +#define h2g_valid(x) \ + (HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX) + +#define h2g_nocheck(x) ({ \ + uintptr_t __ret = (uintptr_t)(x) - guest_base; \ + (abi_ptr)__ret; \ +}) + +#define h2g(x) ({ \ + /* Check if given address fits target address space */ \ + assert(h2g_valid(x)); \ + h2g_nocheck(x); \ +}) + +#endif From patchwork Thu Nov 14 01:12:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18A27D637D5 for ; Thu, 14 Nov 2024 01:18:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBORy-0000UK-22; Wed, 13 Nov 2024 20:15:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBORn-0008Ub-6e for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:01 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBORl-0002BX-Gb for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:14:58 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4314b316495so892045e9.2 for ; Wed, 13 Nov 2024 17:14:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546895; x=1732151695; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bnHexH62EqsPqSCCVFJiR18Ut4gF1uO3ZfHgDoJH6Vo=; b=Vtgnp2ZhmF8mbg8qcgqwNbIlVSIJ0JROwNloGWHWPg7UWDMJs6uZCmiVhPCoeeHtku ZCjoIx7hOCx6TStfaK2xNsTFWDEM4Bhew9q4lgs24CrOsy/P6DGVnvPaNLVXX8APvhXS 3zqeQ3MXverlCxA7KjiZC1uTHmB/TZZgDd1n7A2Jic1s8A0mTKXdjGfDtZytdBcKv/JG 7pjwhy80jqUiF6VnKmywe60hTKFDjq7Kf9hDym7kSS8BOKUNVJrs1NpE9WfCOS5h3Mfz vucWTsYldH5hha835pGsissDbCA+C+AUeBAnxnYlscb5D4OcWXgCYr8A+PXtLUrFxYAi gnLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546895; x=1732151695; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bnHexH62EqsPqSCCVFJiR18Ut4gF1uO3ZfHgDoJH6Vo=; b=qXg9oiOt9+0kT6qU/Y0P2itAENdk0l33D5fUit5C4MJTk5RFI6aoZnp4frmVSGUqsP vysYmPPPH76M2DhdUpsMIoocjSqGmNV5bCMs3h3XsO4OEa1OgCWMGXkZlFY8G7iSsbYl dXbofk5uHSsLCeCpxnpmTyE0kO7JrPmI5lxvGAJisXlrcC0jTcGx/diG9pKeButepM71 zH/BVPB6SxbLpREA1kD8o/Y1QsLgjs2D6KbRLTfEept0uqUXHTPlJG7/1HN/nq/wneqX LWE4LNatDd1bJ7tN7FdpEYZOZiWu523lrnV6Nu2zZl8/3DfIoHJARt61jY+DXLzl22z3 JBng== X-Forwarded-Encrypted: i=1; AJvYcCW/1r32Hzwq48DY5WVepq06CvP1vZSpgn4nqMZRlFVyJ+dg8x/Es0kW+desdSVcQfJgUVxZAkiv9g/F@nongnu.org X-Gm-Message-State: AOJu0YzRrT3cDNbIGf58ebbzAEiy/4eXJly6ytjFHyQEoW5cDL93IFpg gXYVtyZXO++kuOVfwHrM6uLg97lInpkEZgLaZea/MqwA85tKT+te3rWj3tvQebY= X-Google-Smtp-Source: AGHT+IGRRIBLDqHxwGvygVd7DolZQGg3AA35b02RB8xxCyDjdgNLnjdc3+2vgRQgLmodm+ip4IylVg== X-Received: by 2002:a05:6000:18a3:b0:381:f443:21bf with SMTP id ffacd0b85a97d-3820df5bcafmr3699799f8f.2.1731546895166; Wed, 13 Nov 2024 17:14:55 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab80869sm1502515e9.22.2024.11.13.17.14.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:14:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 12/24] accel/tcg: Have tlb_vaddr_to_host() use vaddr type Date: Thu, 14 Nov 2024 02:12:57 +0100 Message-ID: <20241114011310.3615-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org abi_ptr is expected to be used in user emulation. tlb_vaddr_to_host() uses it, but can be used in system emulation. Replace the type by 'vaddr' which is equivalent on user emulation but also works on system. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu_ldst.h | 3 ++- accel/tcg/cputlb.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a26ab49b0b..769e9fc440 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -67,6 +67,7 @@ #endif #include "exec/memopidx.h" +#include "exec/vaddr.h" #include "exec/abi_ptr.h" #include "exec/mmu-access-type.h" #include "qemu/int128.h" @@ -330,7 +331,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, return g2h(env_cpu(env), addr); } #else -void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b76a4eac4e..080cbcb34d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1504,7 +1504,7 @@ void *probe_access(CPUArchState *env, vaddr addr, int size, return host; } -void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx) { CPUTLBEntryFull *full; From patchwork Thu Nov 14 01:12:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67491D637CF for ; Thu, 14 Nov 2024 01:15:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOS9-00010b-J5; Wed, 13 Nov 2024 20:15:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOS5-0000ir-Er for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:17 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOS3-0002Oi-Ic for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:17 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4316cce103dso1188905e9.3 for ; Wed, 13 Nov 2024 17:15:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546902; x=1732151702; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2hAfsLa5F/wTHTnThKWfes1iOEyMXfbHgC1xYE0xNjQ=; b=iMVlTWVyKpfHAhvxo6HbvZo3XEa73a1aJlyby1RrKCRzdX1ycvtezXP7MJ1dtUgsan Zc1X9hMhIjJPTUvmvizoRq4A/gStjmkZH68ZoCknj1QpZOUqysBn4DPxQR/PNVFCv0PC Qhx/MZ0TgblILs7CyE6qaw2t3maTCO5cY4hUu5+9Sq9VuWFAY8792e6PgQqICwDJvV3J OaNDdjxmDxjfmCI9QQJrSZxOBXFP3VBqT3P6MvT2kc6RNFacaAIyPtYrWuPG7O2XJvcv kx97TfOm1cky46dsCWHgvbopsS8EH0xTun6tqwP5gi4MjXa4NJeDNDbdkVxT2tjopord 4Irw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546902; x=1732151702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2hAfsLa5F/wTHTnThKWfes1iOEyMXfbHgC1xYE0xNjQ=; b=m3FCBOVZiChiqexEOZZuh8JsIbSYgVuJx5NCnlJiDxr56+I9k1JLs70CcXVgnAoeyl vYRVUDb8ZEXx/4PLgo1Fn79UAgiM6iNuM6bx4qNYZy7WX/Ml6d7TB1raM0WtbFFWBCdn ozK4Ba/qPNl7UYJ8HkJMGzWMkeZS76Kf2vrTIng4G1+j8l7Q8NaQ/nrsQd1t0nW8rCRF r1jqGXpgAY94EJquRdvjvHH6pSyKp9DSKihQwDadxhiPV9aDHyyUAOpiozSHjrJmjRkr CPj41Lmyn0G1oF+LH7Z/zaID6huHh34XNeiecNla7l6HFm+tUFclclpWyCqg641XLbsN 6rtw== X-Forwarded-Encrypted: i=1; AJvYcCWAkshsJ1HK2mkO8iXP6lYqGaOC6sewgIsTY6z8wynqExD9M5uK8g0Ih4UpJf2eRtoze9TKOu4m6Kdn@nongnu.org X-Gm-Message-State: AOJu0YxBJdzvdBz4vV334fovrjnEqKOAH4fb3/3isilWy9zncspwZjXn HjqfDKyAlsv5YF8TxTRtFCMeE6gR2BjERPK9afN+RGLxgbJyrKXxlL0S9t5eeMM= X-Google-Smtp-Source: AGHT+IH7RFWsMnakRg5GJlnl5zZr5zJQPCLqZOnOCy/xPwCBs6cxFICDeA4XzSDQuRyqlWzDDXypCA== X-Received: by 2002:a05:600c:444e:b0:431:52a3:d9d5 with SMTP id 5b1f17b1804b1-432da6d6676mr3323435e9.0.1731546902007; Wed, 13 Nov 2024 17:15:02 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac1fbf9sm1377125e9.41.2024.11.13.17.14.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 13/24] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:12:58 +0100 Message-ID: <20241114011310.3615-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 7 +++++++ include/exec/exec-all.h | 3 --- include/exec/ram_addr.h | 1 + system/physmem.c | 1 + 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ef18642a32..6cac7d530f 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -32,4 +32,11 @@ void tlb_unprotect_code(ram_addr_t ram_addr); #endif /* CONFIG_TCG */ +#ifndef CONFIG_USER_ONLY + +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); + +#endif + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2e4c4cc4b4..2c06e54387 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -589,9 +589,6 @@ static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} #define WITH_MMAP_LOCK_GUARD() -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); -void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 891c44cf2d..b6d5551549 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -23,6 +23,7 @@ #include "cpu.h" #include "sysemu/xen.h" #include "sysemu/tcg.h" +#include "exec/cputlb.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" diff --git a/system/physmem.c b/system/physmem.c index dc1db3a384..3f937a5e58 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -32,6 +32,7 @@ #endif /* CONFIG_TCG */ #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/qdev-core.h" From patchwork Thu Nov 14 01:12:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D60CBD637CF for ; Thu, 14 Nov 2024 01:16:22 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOS8-0000vh-Lz; Wed, 13 Nov 2024 20:15:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOS4-0000fW-Op for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:16 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOS1-0002O7-1d for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:16 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-37d50fad249so78289f8f.1 for ; Wed, 13 Nov 2024 17:15:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546909; x=1732151709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H8uiLmmGjHl/HLmoj7E2H8Y9eTAxD3FMaBkjbXtSXv0=; b=iQd6E1PLfhAmmSxaNkK7kRkbGpRAItX8KK1D+sz5Qu97I6dLfFRg622ZkReGncPSO7 BBb1kw+FiynOrlM0WmRktdp5zvz5a/8r78t1fq+b9XCREZiClIp+7QW/gQo5D9ugJfYv JK3mVKBq3s+ZZBNWv2FyKOi91opTSLqmA/huLfRiEEVMXt0h65Bm8MRdg3BHYLNfoWbO ffUwumYbalcDFV3sHUe7+cqYFnIma4AHh2UlWUj77T5qWMSx+fD0uER+cgEypiKvbHJH m9F/RFATzLE2g0cPm1deI4wWuHWE2SGFx40iihnfd0MgXYGLqugyiyju8suC/WHFdTMm U0pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546909; x=1732151709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H8uiLmmGjHl/HLmoj7E2H8Y9eTAxD3FMaBkjbXtSXv0=; b=qEBSdyaXf/ekgRbZMoWUFhpOw6QnBptEC9ttwpoPw1BoldE3dOO45S/s/X1sJwHf9H hQDfSsRDq+xmyan6qXhJvveOO31urYWb6v+U7UV+6ERIuwV1DZ9o4nvFBN83NITrs0WH 8C6TFTDAIjZI/B0tIc0oYFvqn6TnaDW4Sg0S1+FW8E50nfOqEUUm8n4iWtQ4gnV59GB1 g2FBxBV1MbuzNo7P71s+TUWUUudNzegknwqsvV5NvYYKegpT+y5xyYOgO4+61sdmmmmG 8B70lQ4s6x5+Ddn7+a8kzTlAcDQHRKvmvJUtEa7EL1LGeRRHom4mIkEoYKEiWYJK31Dd vVAQ== X-Forwarded-Encrypted: i=1; AJvYcCViNevRySIlCGqeEXvgQR1Efsu/BRfquuySH+19HepAPptoItVJR43jT/9xG3gBtiEMUwlTGcpbjtP2@nongnu.org X-Gm-Message-State: AOJu0YxLBFNnjJw785waP6i2xepPVtAebrDaBYJfgQZBP5KEqkBYa9r9 qdv6yy/ulb+cMjM87EgclY4rpzua7jbjYlfwOjbhNdY1vsOzcfWi2CHpFWXOv60= X-Google-Smtp-Source: AGHT+IHK50zmBoBB15u0Bg6EGMq2iWpXvibiYXl8HwVfa1E+/x1N83Vl6CClqN1LX+DTgZLH9wKKkA== X-Received: by 2002:a5d:59a6:0:b0:37d:4d3f:51e6 with SMTP id ffacd0b85a97d-381f186bf72mr19363024f8f.14.1731546908922; Wed, 13 Nov 2024 17:15:08 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed987d95sm19923679f8f.44.2024.11.13.17.15.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:08 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 14/24] exec: Declare tlb_init/destroy() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:12:59 +0100 Message-ID: <20241114011310.3615-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 28 +++++++++++++++++++++++----- include/exec/exec-all.h | 17 ----------------- accel/tcg/cpu-exec.c | 1 + 3 files changed, 24 insertions(+), 22 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 6cac7d530f..5386e53806 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -22,15 +22,33 @@ #include "exec/cpu-common.h" -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); + +/** + * tlb_destroy - destroy a CPU's TLB + * @cpu: CPU whose TLB should be destroyed + */ +void tlb_destroy(CPUState *cpu); -#if !defined(CONFIG_USER_ONLY) -/* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -#endif -#endif /* CONFIG_TCG */ +#else + +static inline void tlb_init(CPUState *cpu) +{ +} +static inline void tlb_destroy(CPUState *cpu) +{ +} + +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ #ifndef CONFIG_USER_ONLY diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2c06e54387..d792203773 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -47,17 +47,6 @@ static inline bool cpu_loop_exit_requested(CPUState *cpu) } #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* cputlb.c */ -/** - * tlb_init - initialize a CPU's TLB - * @cpu: CPU whose TLB should be initialized - */ -void tlb_init(CPUState *cpu); -/** - * tlb_destroy - destroy a CPU's TLB - * @cpu: CPU whose TLB should be destroyed - */ -void tlb_destroy(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -242,12 +231,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); #else -static inline void tlb_init(CPUState *cpu) -{ -} -static inline void tlb_destroy(CPUState *cpu) -{ -} static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8163295f34..8770493590 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -24,6 +24,7 @@ #include "hw/core/tcg-cpu-ops.h" #include "trace.h" #include "disas/disas.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/atomic.h" From patchwork Thu Nov 14 01:13:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D77ABD637D5 for ; Thu, 14 Nov 2024 01:20:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOSE-0001PT-Hv; Wed, 13 Nov 2024 20:15:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSA-00019G-EJ for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:22 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOS7-0002QH-V8 for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:21 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-431ac30d379so1004725e9.1 for ; Wed, 13 Nov 2024 17:15:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546917; x=1732151717; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ijxub0J6LSuaPkun5QktYbNZDFSQDSukz+hms+c1Ih0=; b=j8Wy1IKpWhbSGsE+4uzRK5uSblCZD17L68agSr7tqfki3RzMgzQ/9LlyDdsbViyXxI foFXN5L3kI1hfN50MEHH1uuJxXBDvdmmH954OyqQmiwaRQwzUFwLJz3Rq5bGpdv9k0dD 2axyG+I38ZHsONIuxVH9GxpdN7t7BrlA0I5IsnfioEGInOsmraycuIXymuB94pZF25lJ NacY8T4RUxJhpzZHwcbXVZ7uj8WjgeJEC4Q5I9qXZLEeYAaB5sv43S2wFR+zcQOw2xz2 eqd8/hhOk9ClRbzym+RHICjkl4J38EpVEV5ymfqRCkNyJfjDAIjGl8IiJR+dhMG8n6gU /cRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546917; x=1732151717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ijxub0J6LSuaPkun5QktYbNZDFSQDSukz+hms+c1Ih0=; b=CNj8NcCWdpon48/F81VNX2izHMIedilcPQt1QoMp3KE4XDQeRGxUy+qE+UxEu9O7W5 WKQ3WfxxWRz75nEn3aRIqyfxXnShvz5KzDeydDXab7mxYRlaKJQT5t2Ade9dZhfjXeCc 4WWYN7mSE9wRJVd6XL6LtVFgWDLL24jbrzfv9nnPfpcn8kpvt2Vr5aGslu5cIEg2lCu1 rFc5tWntkMSdT2YMry8dHz0qg6aeM12lGYs2aNTaH0RWbGKtBJzL8oa/TMSogRZIf0IT Q4VKshtE6pn6KlGqfO40HRoqgXJFKed1jGYzJ5g7kkHxsmql8fKicYOyZr5boAHGEx31 E51Q== X-Forwarded-Encrypted: i=1; AJvYcCWi4MfvjkGj+onKH5x1/B00hv7i926qpvgkOEElTH/H2PPoATAI3yx9QjykTQm63OI/tzbqnXfjiCxT@nongnu.org X-Gm-Message-State: AOJu0YxHf41LZrxwIh1lG+nATMdN1MXT4c7oQFnvcKz/seWYnK72LZYl gQcghOpkQMYOXvfig/GeGXQSjo57tuJsHiLbvGaxTYvFhbfe+DBrABhySZ/i1vHka8imOH/OBQq J X-Google-Smtp-Source: AGHT+IFREe/JrPjo0y0t9M2Yxcx4JMxB17tQX6TF3pVR/3qVRL4KfJoVIRyzbtQL0IXAATDBdsI/jg== X-Received: by 2002:a5d:6d83:0:b0:37d:49a1:40c7 with SMTP id ffacd0b85a97d-381f1872717mr19221825f8f.28.1731546916093; Wed, 13 Nov 2024 17:15:16 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed97c6b6sm19475690f8f.24.2024.11.13.17.15.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 15/24] exec: Declare tlb_set_page_full() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:00 +0100 Message-ID: <20241114011310.3615-16-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 23 +++++++++++++++++++++++ include/exec/exec-all.h | 22 ---------------------- target/sparc/mmu_helper.c | 2 +- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 5386e53806..f6205d5306 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,7 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/vaddr.h" #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) @@ -57,4 +58,26 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); #endif +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @addr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + CPUTLBEntryFull *full); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d792203773..79649537b0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,28 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_full: - * @cpu: CPU context - * @mmu_idx: mmu index of the tlb to modify - * @addr: virtual address of the entry to add - * @full: the details of the tlb entry - * - * Add an entry to @cpu tlb index @mmu_idx. All of the fields of - * @full must be filled, except for xlat_section, and constitute - * the complete description of the translated page. - * - * This is generally called by the target tlb_fill function after - * having performed a successful page table walk to find the physical - * address and attributes for the translation. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only - * used by tlb_flush_page. - */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, - CPUTLBEntryFull *full); - /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 9ff06026b8..7548d01777 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" From patchwork Thu Nov 14 01:13:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 116ABD637CF for ; Thu, 14 Nov 2024 01:18:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOSK-0001f8-6C; Wed, 13 Nov 2024 20:15:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSH-0001a6-Fu for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:29 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSD-0002Um-Us for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:29 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-37d47b38336so58246f8f.3 for ; Wed, 13 Nov 2024 17:15:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546924; x=1732151724; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rUDaBZRCGe5XV9UkQASFR3nCzZYDHP53JFnYTigMJ4o=; b=NYXwQxItPqJDdAsaYRcfhW55oxaVXkg/vhnwk5Vfy3WnClpXzH9wHtMlaICT+mKDxt SnorxN6UWtwMbpxCI0T8tSfRZS2SihVqysXma6Sng/RcO+u7p3r78LnxnsMkFlXVU3rH y7yEK85/q/qMGiRR83GvKI0JKEgAjei8YzeQ9z075OLWTljc1VPP3LLao6dFYphkQlKH cBC/7Ug8oNSiWSJ5lucVBUwSrF1hwm7O1P8wnIX9JAVvGRFexLTlMbPcWaHI8avD5AES tDhNonB94W7KS1CoynhfpoIZOs9ITmEEUzQ49fbq3e+DaS8FEgUgoLj/pmdcxnBXn0XZ 1FDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546924; x=1732151724; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rUDaBZRCGe5XV9UkQASFR3nCzZYDHP53JFnYTigMJ4o=; b=pS7KTGYlxcEmqM9FEtuIAeOKmIXNIeG7B/4VtalmfRoTgoTrvzHpbrcsYSIb+WkqZL iUWShkQkec2pBgGCOcCz/qJA7XyUeDXKtax8Q1XbUQQS7gevpNrm3xo7jPOL4rsi7SK0 /hwlhEuxeQ+cTMKmzb4OZ+cXOquB57X/2mhBmZNnTDm2HEBy5Ysiz7VJZzFJQ3GGHrEp SmHsioMIhrgYjuLDqkEMc3ZKO1/ncj3pIPQHFsgk/EHx3rIGY8ogmVVV7rAC1vzxHIRw ZNRGy0hUSBAnI1+XMXEFAaTpetiu9BL+w4hQ/3FBlL8FJ7uXr+vETdNyBHeQVh33J64a /PIA== X-Forwarded-Encrypted: i=1; AJvYcCWVEZmvljQcsloyhLFVL6YS8hXXHZ8bS9kvpPx9fl7Nv7gXagyNe9N1eCSi4V4TIb1LCluuVLGNfxjG@nongnu.org X-Gm-Message-State: AOJu0YzRtPPRudVG1uMYrRqiYqzZ/xbX0H9LRr9BX50lBxJmDNOR7HHr kfPsSZNxdqWueLB9PRA8E0rF2NBHDYHaFfgL+IxFLHRW+oNDO/Yu394qottJX3M= X-Google-Smtp-Source: AGHT+IHsnUDtCJjwswsvou+rSW6UUntSAN1M9ewjVg4bTB1KhLSGIABGdWRRaamvym5hsGHe6A5/Vw== X-Received: by 2002:a5d:6c64:0:b0:37d:528d:b8ad with SMTP id ffacd0b85a97d-381f1865423mr20754685f8f.6.1731546924040; Wed, 13 Nov 2024 17:15:24 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed987d95sm19924032f8f.44.2024.11.13.17.15.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 16/24] exec: Declare tlb_set_page_with_attrs() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:01 +0100 Message-ID: <20241114011310.3615-17-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- target/i386/tcg/sysemu/excp_helper.c | 2 +- target/microblaze/helper.c | 2 +- 4 files changed, 30 insertions(+), 27 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index f6205d5306..ae4798a017 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,8 @@ #define CPUTLB_H #include "exec/cpu-common.h" +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/vaddr.h" #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) @@ -80,4 +82,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 79649537b0..2b314d658b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,31 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index da187c8792..cda0152b80 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "tcg/helper-tcg.h" diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..27fc929bee 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" From patchwork Thu Nov 14 01:13:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D20D2D637CF for ; Thu, 14 Nov 2024 01:18:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOT3-0002Rz-NX; Wed, 13 Nov 2024 20:16:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSO-0001lR-9z for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:36 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSL-0002e4-J2 for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:36 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-37ed3bd6114so67741f8f.2 for ; Wed, 13 Nov 2024 17:15:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546932; x=1732151732; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qrrkoTna7tufOe6qwJFGaLdax+anmf+pXIEo/rEb9w0=; b=dZgLNgcozHtPt4OyJKjftjLFhPYewJeExpfQDlOrz7AETafJP1JvCVIA7gSjs8+orw MuMg7VDLfYT3WlEdCZLSWeYUvorA7PUHax7ZHcK9BgTomoDhcVjHGPLV3yXyMeEXTklL XF9CdEKKYWnVY84NBEXkq3WQXmL+CEDoQSoSqYIUf4wVGyWNpnm2UztTzLb9Qp37dV0r Pjh7aVWQakr0v3qxnBN1Az8ySiQfru9e3xAXCBVHMkFzmp+CT6LO5/tQysO8s0mucpTz umlrfLWkMrFMorRIh3b3/Y9QAyNMpuO8tExWOGUxZlnlesjXXZRx5liLoOCs77qGQwSu 0nOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546932; x=1732151732; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qrrkoTna7tufOe6qwJFGaLdax+anmf+pXIEo/rEb9w0=; b=Sd68eoSZk7aKjHiZdxC/PBtjYuiOFO5O1X5q0prDchHv52N4RnY/5Jym1W7qZpRgXr BaXmfyvlkXV/3+HMJiGcZ759meQD5CGor5ko9eJ+g/uC+n2T5Gd7TyZipK/bSDtDnTPm dHe6M/AkV5M/pNNgAqkiNcGuyr21N964N891vWs95A3mGxOtiE/3mRgMIELbHWat9DKE v7Mhe5qddDIBnU+sFkxD/9ItOA+Z/7xhQjP2iKUzu3e1CT8fyqkrVonooCxirJNh5Yva s6yfHxcAuEajKUD19hpuuKtfKGbV0gsmGRM0Jp1CvJhEuyhVgp+S+lngHbVb2x8u+wyH yZ2w== X-Forwarded-Encrypted: i=1; AJvYcCVFUcSP1Vvdt2QsZe/OsSozwHBeEyaaavDOCDpJxmVty1ksHuYZ6Wqmx4m0nKOf8gAM3tSdBuaIum/q@nongnu.org X-Gm-Message-State: AOJu0YwT7I5B/Pw3PVoLwbfnXLkD5xl8d962afYp7HUQvIg6yYTRAjsA ErNT/WkV8sTU20Nd1xpAqhbNs3BxHZ1ZD7WbsxFPS8o1x2L4O93euj34/yM8GMU= X-Google-Smtp-Source: AGHT+IHuhhAiEzkVHTWofBhBqgpOXZdBh/rWL7IMEM1ux8mz49czPs5z3Ayh4M4BEC57KqIzUKPO9A== X-Received: by 2002:a05:6000:186c:b0:381:cfea:2818 with SMTP id ffacd0b85a97d-3821851cc75mr155127f8f.30.1731546931624; Wed, 13 Nov 2024 17:15:31 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac0ae51sm1409755e9.34.2024.11.13.17.15.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 17/24] exec: Declare tlb_set_page() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:02 +0100 Message-ID: <20241114011310.3615-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ae4798a017..9075d94ec5 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -108,4 +108,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, vaddr size); +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2b314d658b..2e58540005 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,15 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap, unsigned bits); -/* tlb_set_page: - * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. - */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { From patchwork Thu Nov 14 01:13:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874446 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8905D637D5 for ; Thu, 14 Nov 2024 01:20:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTK-0003WG-N0; Wed, 13 Nov 2024 20:16:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSd-00028j-VY for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:56 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSW-0002pF-0c for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:50 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4316a44d1bbso883485e9.3 for ; Wed, 13 Nov 2024 17:15:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546940; x=1732151740; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uDUBQb+LxmlUYEklKQILqed81KQyLLFPtXCqT+KpbiI=; b=NJi5hp/o+RYFJPs4ddXr6H9banLmcktiO4rRRFZnaOADe7R5c0XlB7OLeAkPwv8wrf iUc6Knaknm00TIxoHm6m54V376otS/grGHPNUFNJx9w5Sq3/pgY1n64pD0bQjhCFC90e OqO3lc/qRying14xQox0lsBS5lK7zBw+MgaAW4ImjXNHwfGdYk05bbFOnDj25B5wWVPB D8dbKVzOUciyfHcvFI/csoKpxh7enrc6oC0IdVRR4CYZ3Vc+154OlS5qLB4frK+48FLQ Y1qm36x/wqlOiiyDe37wMHuMozeCFjBi3/BeAn7pmg+x9Oejmq2ZbM5XTelquIKiRafD kHqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546940; x=1732151740; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uDUBQb+LxmlUYEklKQILqed81KQyLLFPtXCqT+KpbiI=; b=Yp+WnbfdSe3O/UWqgUAtCCeg4Elp3E0zwT63V/NhOBb6UGuBJ7pv6n9Dy/Z2MZH6aG uQ+8iVK9W4QFBYaIypiCHj7Yziwfpckqy2tZ6todIcETYw/G9hfoYpKhdeEDNR3NXpev +7m5Obfc1mUXWWzkcIPAZ3tioSQ2G2+N3XmMS0XC0Ad4hXjaqb1Qoomm24jSG2u8MiY1 JiSoSme2Za9RqKHax3PYTe3oViUuHWs0XUEDfEPeUBPmABH3bblaUNNns0xJhniGVYCJ qD2HW/PeGD18PhwodMjYLFvX+lyk0Ja7oB9q8iy9Eo7i6PiB5439Mpl/Wi0+4gOW5Ajl RmqA== X-Forwarded-Encrypted: i=1; AJvYcCUWu9rbW+crDXBBzQVMkW12qNM/kBYgctC1I/AexwFLzyMtzEiAxwRUQ8CsqLfSwLoq9D0ssZ2D3Z9X@nongnu.org X-Gm-Message-State: AOJu0Yw+vkba+Kz8VyJ4AGOonbOanRTqWUN67zCkVwgyZh1p65FILtRH VA61oO4cZruDawxnFPtoNwS+xpBajLBruADgn7sqraUPXgjAsM4nKxO23+gGVsM= X-Google-Smtp-Source: AGHT+IE1pgEYEqJGScSPvTrOip5pjtAnThnKSK1k4RMPDyxAX2xOyGVmGe7ZEJEGkqa83irxnX/itQ== X-Received: by 2002:a05:600c:1c1d:b0:431:5957:27e8 with SMTP id 5b1f17b1804b1-432d4ad89a3mr36745965e9.28.1731546939922; Wed, 13 Nov 2024 17:15:39 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab7878esm1544405e9.14.2024.11.13.17.15.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 18/24] exec: Declare tlb_flush*() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:03 +0100 Message-ID: <20241114011310.3615-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cputlb.h | 187 +++++++++++++++++++++++++++ include/exec/exec-all.h | 183 -------------------------- accel/tcg/tcg-accel-ops.c | 1 + cpu-target.c | 1 + hw/intc/armv7m_nvic.c | 2 +- hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c | 1 + system/watchpoint.c | 2 +- target/alpha/helper.c | 2 +- target/alpha/sys_helper.c | 2 +- target/arm/helper.c | 1 + target/avr/helper.c | 2 +- target/hppa/mem_helper.c | 1 + target/i386/helper.c | 1 + target/i386/machine.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/misc_helper.c | 2 +- target/i386/tcg/sysemu/misc_helper.c | 2 +- target/i386/tcg/sysemu/svm_helper.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/mips/sysemu/cp0.c | 2 +- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/openrisc/mmu.c | 2 +- target/openrisc/sys_helper.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/misc_helper.c | 1 + target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/pmp.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/gdbstub.c | 2 +- target/s390x/sigp.c | 2 +- target/s390x/tcg/excp_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sh4/helper.c | 2 +- target/sparc/ldst_helper.c | 1 + target/tricore/helper.c | 2 +- target/xtensa/helper.c | 2 +- target/xtensa/mmu_helper.c | 1 + 46 files changed, 231 insertions(+), 210 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 9075d94ec5..07c4bc669e 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -39,6 +39,141 @@ void tlb_init(CPUState *cpu); */ void tlb_destroy(CPUState *cpu); +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page(CPUState *cpu, vaddr addr); + +/** + * tlb_flush_page_all_cpus_synced: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of all CPUs, for all + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); + +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for the specified CPU. Most CPU architectures + * allow the implementation to drop entries from the TLB at any time + * so this is generally safe. If more selective flushing is required + * use one of the other functions for efficiency. + */ +void tlb_flush(CPUState *cpu); + +/** + * tlb_flush_all_cpus_synced: + * @cpu: src CPU of the flush + * + * Flush the entire TLB for all CPUs, for all MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_all_cpus_synced(CPUState *src_cpu); + +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_page_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @wait: If true ensure synchronisation by exiting the cpu_loop + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_page_bits_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * Similar to tlb_flush_page_mask, but with a bitmap of indexes. + */ +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, + unsigned bits); + +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits); + void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); @@ -50,6 +185,58 @@ static inline void tlb_init(CPUState *cpu) static inline void tlb_destroy(CPUState *cpu) { } +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) +{ +} +static inline void tlb_flush(CPUState *cpu) +{ +} +static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ +} +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + vaddr addr, uint16_t idxmap) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + uint16_t idxmap) +{ +} +static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits) +{ +} #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2e58540005..36dbc191cd 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -46,189 +46,6 @@ static inline bool cpu_loop_exit_requested(CPUState *cpu) return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; } -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/** - * tlb_flush_page: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page(CPUState *cpu, vaddr addr); -/** - * tlb_flush_page_all_cpus_synced: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of all CPUs, for all - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); -/** - * tlb_flush: - * @cpu: CPU whose TLB should be flushed - * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. - */ -void tlb_flush(CPUState *cpu); -/** - * tlb_flush_all_cpus_synced: - * @cpu: src CPU of the flush - * - * Flush the entire TLB for all CPUs, for all MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_all_cpus_synced(CPUState *src_cpu); -/** - * tlb_flush_page_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @wait: If true ensure synchronisation by exiting the cpu_loop - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); - -/** - * tlb_flush_page_bits_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * Similar to tlb_flush_page_mask, but with a bitmap of indexes. - */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); - -/** - * tlb_flush_range_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of the start of the range to be flushed - * @len: length of range to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), - * comparing only the low @bits worth of each virtual page. - */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits); - -#else -static inline void tlb_flush_page(CPUState *cpu, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr) -{ -} -static inline void tlb_flush(CPUState *cpu) -{ -} -static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ -} -static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) -{ -} - -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - uint16_t idxmap) -{ -} -static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits) -{ -} -#endif - #if defined(CONFIG_TCG) /** diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 22486c5dff..663831700d 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -33,6 +33,7 @@ #include "qemu/guest-random.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" diff --git a/cpu-target.c b/cpu-target.c index 499facf774..63d563cd0b 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -40,6 +40,7 @@ #include "exec/replay-core.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/translate-all.h" #include "exec/log.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 98f3cf59bc..b0a638e035 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -22,7 +22,7 @@ #include "sysemu/runstate.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/memop.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 7def8eb73b..23958c6383 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 8041b3b651..9692d5b624 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -36,6 +36,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "trace.h" typedef struct SH7750State { diff --git a/system/watchpoint.c b/system/watchpoint.c index f7366574a3..622463e11b 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "exec/cpu-all.h" +#include "exec/cputlb.h" #include "hw/core/cpu.h" /* Add a watchpoint. */ diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..57cefcba14 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 768116ef32..95cf3d2560 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "sysemu/runstate.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index f38eb054c0..c2e400643a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -19,6 +19,7 @@ #include "qemu/crc32c.h" #include "qemu/qemu-print.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include /* for crc32 */ #include "hw/irq.h" #include "sysemu/cpu-timers.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 345708a1b3..f255126016 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,7 +23,7 @@ #include "qemu/error-report.h" #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b8c3e55170..7a1729ccd2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 75c52e2143..84a17172ba 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/translation-block.h" #include "sysemu/runstate.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/machine.c b/target/i386/machine.c index b4610325aa..2a08b26a4b 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "hw/isa/isa.h" #include "migration/cpu.h" #include "kvm/hyperv.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb297..868d12381f 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,7 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ed4cda8001..2b5f092a23 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper-tcg.h" /* diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index 094aa56a20..75cd592267 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 9db8ad62a0..0def3afb14 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c index 15f94caefa..d486b8f23b 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -11,7 +11,7 @@ #include "internals.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "hw/irq.h" #include "cpu-csr.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c index 97f38fc391..40603202e5 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -12,7 +12,7 @@ #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/log.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c..fc8ea87ddb 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..f8587d5ac4 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" static unsigned int tlb_decode_size(unsigned int f) diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c index bae37f515b..ff7d3db00c 100644 --- a/target/mips/sysemu/cp0.c +++ b/target/mips/sysemu/cp0.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" /* Called for updates to CP0_Status. */ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index 79a5c833ce..01a07a169f 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -27,7 +27,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" /* SMP helpers. */ diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index e98bb95951..b545d49a6b 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/log.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..47ac783c52 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 77567afba4..21bc137ccc 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 42c681ca4a..61432c165b 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "helper_regs.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index f0ca80153b..e379da6010 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index b167b37e0a..718070b600 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -24,6 +24,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69ea..767db4a5cc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -23,7 +23,7 @@ #include "cpu.h" #include "internals.h" #include "pmu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "instmap.h" #include "tcg/tcg-op.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9846770820..9e1c4ab0e7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "sysemu/cpu-timers.h" #include "qemu/guest-random.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b..212ba97408 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a1b36664fc..1bf962cf1b 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -24,7 +24,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 945ae6e9e5..add51d4477 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/translation-block.h" #include "hw/loader.h" diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 63373f02ce..865313c98f 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "qemu/bitops.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index 08aaecf12b..0d18f14251 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -15,7 +15,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "sysemu/tcg.h" #include "trace.h" #include "qapi/qapi-types-machine.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c0b692c9e..003ed86413 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0e12dae2aa..2ad54d7133 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "hw/core/tcg-cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 303f86d363..e3401f4efe 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 9659c69550..a45c38cc4d 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index d92c9f1593..ae2a5fb4ab 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -24,6 +24,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "asi.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77..d88dd20305 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,7 +19,7 @@ #include "qemu/log.h" #include "hw/registerfields.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index ca214b948a..6327bf048f 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 29b84d5dbf..91b869fb50 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #define XTENSA_MPU_SEGMENT_MASK 0x0000001f From patchwork Thu Nov 14 01:13:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7219AD637D5 for ; Thu, 14 Nov 2024 01:19:54 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTH-0003EK-MD; Wed, 13 Nov 2024 20:16:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSh-00029N-3q for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:56 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSd-0002tV-Nz for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:15:54 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-37d518f9abcso61274f8f.2 for ; Wed, 13 Nov 2024 17:15:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546948; x=1732151748; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=47l8bIL01QRkGakpDpfE8XrYcUIw9iQZ4Ki9frTlDYk=; b=s5/aTpNAmeil+gjc7YoRh7MPXiSUW5WGmY4z8RPHHIuDVNlqd6098snIXdMuBMzumb wVpgcUxHU/KeIPP0SOatdQ1Xnb2BfjarYUuaEYF944px6CvGUm+ffS5IDE4cdKYdS7c+ CUcnRnuqkiGBXvgVjm0ytM3P00JflsJfeBLu0oX+FDBiKEfMAksZYl0lOXcbYnXLnYqh Kf1hiSb6Blnd0tYM5mL2to/DFLLP2lhy6Aw/IP/aH3P8IF1N3v4QneYn9YkPuDmT0l3o MMHT2zYlS0gN0nz2vGKbq23UsG9h+gXMNceFI8Q3/QRmQSSatUHfpHMU4uFMqedgLGi+ mK5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546948; x=1732151748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=47l8bIL01QRkGakpDpfE8XrYcUIw9iQZ4Ki9frTlDYk=; b=NBMFTnqecbOAU5tfP8bWekmHPLh/bC81jlfZJHbtmwFX976X2QZUGkb4f+nKgO2HFu /M/DP33131QOsRob5dkuPXNGLZlz5BuW3v7i6gAq4BbWmz+BtdisOwSJzbjR5AqPZ+em TdaKRcSr2KTo4AapVNQFPcDdrZKkFXgAu9vY4ftZuGP7LbchaysK236Op+Hf/mJyu+K1 BVNRGT/BPfesecfdCUjtKjvtmEGdUwCLQG9kIy7Z8+I0X11dtMfMDMIzu9UgoIfeI5/R qkAyEf4tX40TdkoyJ29NS4fQ/UBf+f9DZZGlMBsqAmuuRkERlolwrMc+/0R2t9tCyBrr Oeyg== X-Forwarded-Encrypted: i=1; AJvYcCWY8FQ6WP9EHMiFijhfo4yk/tIcOFR+LTcL8ILHkoI4ZWgwfv29MbGdT5IkOV53S7CAT/Dk1UqXJ3mm@nongnu.org X-Gm-Message-State: AOJu0YzaZ8On7vJJmF+51WjYgLAD1kJvHw1tDdVNtQcLyRdPBRDZVAFW IHDain8x4RPNGsQSC5ffX1YOpY3k+F6/k/ZLGh3SuIfA7Wuc1tq+5oSdv5ueHBk= X-Google-Smtp-Source: AGHT+IGm4IkujNwbvXU0PfthP+KilYpmsFGPbZN2Ec16W6AxewEFOjqxxAMvc9mYtsMmC6kajJV0Dg== X-Received: by 2002:a05:6000:1868:b0:374:c3e4:d6de with SMTP id ffacd0b85a97d-381f1885dd9mr19331385f8f.41.1731546947775; Wed, 13 Nov 2024 17:15:47 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed9719easm20201050f8f.9.2024.11.13.17.15.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:46 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 19/24] exec: Declare tlb_hit*() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:04 +0100 Message-ID: <20241114011310.3615-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cpu-all.h | 23 ----------------------- accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1c8e0446d0..ccaa650b19 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -323,29 +323,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - #endif /* !CONFIG_USER_ONLY */ /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 080cbcb34d..dba4831cd1 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1220,6 +1220,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + /* * Note: tlb_fill_align() can trigger a resize of the TLB. * This means that all of the caller's prior references to the TLB table From patchwork Thu Nov 14 01:13:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38D21D637D5 for ; Thu, 14 Nov 2024 01:17:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTR-0003xD-Gp; Wed, 13 Nov 2024 20:16:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSn-0002Gg-2d for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:06 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSj-0002ze-RP for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:00 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-431695fa98bso889975e9.3 for ; Wed, 13 Nov 2024 17:15:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546955; x=1732151755; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MKGKBpB51JYn8fa9pIjr5nOqIfE0klwKIY58pnM7yzQ=; b=yNiImsWRDsx6DyLM8W8L1YX5g+13n6q2eBH1gVUCdB36VlznTMNM9/7Wyueo3IQZHW ULtuj4kBJvlmpp5tTwuriTBJPooBNt6wnSRooO6as89wqJJOILpFoWjSLUsSt6XKKXM/ CwZOlyqecIAGAeORc0q/csEio1ifDxMfMygLA5jcSiA2HIccTArcis97wgB9HxPDDiiB tjihHDN8sJIRZ9OJXqG2+FniC3YVYxli1tyBuCrXBKRvfMixG0YBz5bpalLyLv6rQZ75 24JEreVeDC92V+SjY4pLPIqwf8ut6Q7ZsboPnv3RKsG8tRRuPlMQTozMVkv9EsJE8I9L igcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546955; x=1732151755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MKGKBpB51JYn8fa9pIjr5nOqIfE0klwKIY58pnM7yzQ=; b=D8U75EBPTXDeNQTvRvvWYenM2MSA83yXfjkH5BllQVfaAPTw7EFdw/qL29nHEpbo0v j/4fQLmqgNfOYSmcd5DwOZPuwXCpdFIxZ3MHFuYehlSi9EZTry8ue0HSBFOpAxxADCpQ EX33/T0bSMqRcdCw5KmYsZQmgJS9z76EN3+nGRQciJo99YgZXWdvtGgmJ8a44Zhhmotn 2W/GkRBmv/QRUB3w8HpGH0nixwl4gNPq186gJnUqzBOKqHVfqBbD5pY+ijfEcY8Om5LN aPP6FWzfmL/z8Q7tntKctR+CYHpn7SYqtt9HVUcKxfuKPgTCAZQ+R69J9zB3cVo0jfPh KOrQ== X-Forwarded-Encrypted: i=1; AJvYcCWDQSyho98NiMxjhM485maXmccuBuEK53LwTcinNSReFGzO8TMM5kX2DUU1HPXN2oK+Z/kwUHGy3vb1@nongnu.org X-Gm-Message-State: AOJu0Yy3B5izbTOS/9TJV56zDBLUpKXCaJ2BGE0mAGiarTiUPuGXZejw gL/EIa1Y6H9H+KWo9Mc9dqZpiXOGhLx6wSXW+cKU+UVXj/Vo38X3khVCOzMLKWk= X-Google-Smtp-Source: AGHT+IGZeLWyySAwDHTHVjsW2SFDufD9UpueEyNXzGy6rQrK9O+R2MVoL8wOSZmjPebbfF+JzN4y0Q== X-Received: by 2002:a05:6000:1ac9:b0:374:c640:8596 with SMTP id ffacd0b85a97d-381f186fc60mr19166319f8f.32.1731546955339; Wed, 13 Nov 2024 17:15:55 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381fc0f5f91sm11245808f8f.62.2024.11.13.17.15.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:15:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 20/24] exec: Declare tlb_vaddr_to_host() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:05 +0100 Message-ID: <20241114011310.3615-21-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- include/exec/cpu_ldst.h | 25 ------------------------- include/exec/cputlb.h | 26 ++++++++++++++++++++++++++ target/arm/tcg/helper-a64.c | 1 + target/ppc/mem_helper.c | 1 + 4 files changed, 28 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 769e9fc440..eec47ca05e 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,7 +69,6 @@ #include "exec/memopidx.h" #include "exec/vaddr.h" #include "exec/abi_ptr.h" -#include "exec/mmu-access-type.h" #include "qemu/int128.h" #if defined(CONFIG_USER_ONLY) @@ -311,30 +310,6 @@ uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr); uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr); -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_idx) -{ - return g2h(env_cpu(env), addr); -} -#else -void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, - MMUAccessType access_type, int mmu_idx); -#endif - /* * For user-only, helpers that use guest to host address translation * must protect the actual host memory access by recording 'retaddr' diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 07c4bc669e..4acc2c6235 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -20,6 +20,7 @@ #ifndef CPUTLB_H #define CPUTLB_H +#include "exec/abi_ptr.h" #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" @@ -306,4 +307,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +#ifdef CONFIG_USER_ONLY +#include "user/guest-host.h" +static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_idx) +{ + return g2h(env_cpu(env), addr); +} +#else +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, + MMUAccessType access_type, int mmu_idx); +#endif + #endif diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 8f42a28d07..9cb5d8ee53 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/cputlb.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "fpu/softfloat.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 51b137febd..44974b25f8 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" +#include "exec/cputlb.h" #include "internal.h" #include "qemu/atomic128.h" From patchwork Thu Nov 14 01:13:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6E89D637D5 for ; Thu, 14 Nov 2024 01:18:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTU-0004Kq-C5; Wed, 13 Nov 2024 20:16:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOSz-0002UB-4s for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:16 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSs-00030s-GR for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:12 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-382185ed80eso43740f8f.3 for ; Wed, 13 Nov 2024 17:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546963; x=1732151763; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XrMoqQT7ptZYv4vONwORkBwHk59Gl8c3keboGabWJlw=; b=EmHH/RB4cbscKOuIkp4PQ/anSMtsJ7Qp/LPAiEqiop9fAYSMrDaovfrmDk/S1vKqbi BlgQ7euPpVHhPbMtHHheGpNf/YqdJknzxfPl3IWddy3r1lIbuRGfYO6AESdBNqPp8GPL GtySufHfxNeUgOC6pmckgb+17BALWNVkqikDjrL4NGyqXkduga/US5G6ACpmp8N+qzrl 9aRgELZQsv/l4Cqy3mbKOCEfVK7+HZnOHiQm/yVUC7aLkuPzBl7UQS3uhMFZPsNOlkI1 a4UICUY90l45hwr16qHJ/cmxreuQk/Yj/UlWuWJCT1k3tjYcGjkj1hVjVjVVH+3qx06I Ilkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546963; x=1732151763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XrMoqQT7ptZYv4vONwORkBwHk59Gl8c3keboGabWJlw=; b=UtSbA+yYfy8J1Lo04r7CeBNullbsidWlH20PIFsEmTJYaRXo+uLLKQVaDf4sXGbQQ9 Z3oVK1PR1ukTp2LbZWtRIQycf19Fi8O3vQd/2avokGa0lcanMTkEj0Vvk2c50xpXKoMj tzLkSFOEspPe2Wj5Ymjb8/NN/iHtEMoM804WTZ2ZMwxhOgC6BPwuG+Kep+nOXvYVW4ng eQzFQma+CDBPbzt0WVFzFXHDEATyFGJY8kZeiuQ8H/QJ6FF/vOdvdg2E3OrwOiH3tX4M LuRJHMRxtszTD4oUyPWwAGbb5cPJDPwjk+QQ63dEEwfaHiBBAmD0Z8pGjQ8TAlrqgsb8 8Kaw== X-Forwarded-Encrypted: i=1; AJvYcCUvfK1c9Fhc0BZQUU/imlY9vmdIVXBY3j49bzb3s3mOkgnTG0EIcSrJG3pRhBCssm+niNDIBkWWkljW@nongnu.org X-Gm-Message-State: AOJu0YwgsclMjeuvOa5JvYcOFix1ENVhGxFC128qJ1wMdYtTgD0dfUot hbFmE0b4OKDicAXNMwo9ps0GIi4dsEfSU+oBQrAY0r+wuszgAqE+1rzW4Lme8qI= X-Google-Smtp-Source: AGHT+IG2AXes16xthEsOBLXXWXy9qaPlNaK+RVqMME8LkJ1kCx8/uy3WXzn1xFJWGaGToeAaD0oMjg== X-Received: by 2002:a5d:64e3:0:b0:37d:4ebe:163e with SMTP id ffacd0b85a97d-381f188c956mr18915374f8f.53.1731546963319; Wed, 13 Nov 2024 17:16:03 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed970713sm20009720f8f.3.2024.11.13.17.15.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:16:01 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 21/24] exec: Extract CPU physical memory API to 'sysemu/physmem-target.h' Date: Thu, 14 Nov 2024 02:13:06 +0100 Message-ID: <20241114011310.3615-22-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In order to keep "exec/ram_addr.h" focused on (target agnostic) methods related to the ram_addr_t type, move all (target specific) CPU physical memory API to a new "sysemu/physmem-target.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 1 + include/exec/ram_addr.h | 483 +--------------------------- include/sysemu/physmem-target.h | 506 ++++++++++++++++++++++++++++++ accel/kvm/kvm-all.c | 1 + accel/tcg/cputlb.c | 1 + accel/tcg/translate-all.c | 1 + hw/ppc/spapr.c | 1 + hw/ppc/spapr_caps.c | 1 + hw/ppc/spapr_pci.c | 1 + hw/remote/memory.c | 1 + hw/remote/proxy-memory-listener.c | 1 + hw/s390x/s390-stattrib-kvm.c | 1 + hw/s390x/s390-stattrib.c | 1 + hw/s390x/s390-virtio-ccw.c | 1 + hw/vfio/common.c | 1 + hw/vfio/container.c | 1 + hw/vfio/iommufd.c | 1 + hw/vfio/migration.c | 1 + hw/vfio/spapr.c | 1 + hw/virtio/virtio-mem.c | 1 + migration/ram.c | 1 + plugins/api.c | 1 + system/memory.c | 1 + system/physmem.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/ppc/kvm.c | 1 + target/s390x/kvm/kvm.c | 1 + 27 files changed, 532 insertions(+), 482 deletions(-) create mode 100644 include/sysemu/physmem-target.h diff --git a/MAINTAINERS b/MAINTAINERS index 095420f8b0..0027e56fa5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3027,6 +3027,7 @@ F: include/exec/memory.h F: include/exec/ram_addr.h F: include/exec/ramblock.h F: include/sysemu/memory_mapping.h +F: include/sysemu/physmem-target.h F: system/dma-helpers.c F: system/ioport.c F: system/memory.c diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index b6d5551549..80f6dc7564 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -20,82 +20,6 @@ #define RAM_ADDR_H #ifndef CONFIG_USER_ONLY -#include "cpu.h" -#include "sysemu/xen.h" -#include "sysemu/tcg.h" -#include "exec/cputlb.h" -#include "exec/ramlist.h" -#include "exec/ramblock.h" -#include "exec/exec-all.h" -#include "qemu/rcu.h" - -extern uint64_t total_dirty_pages; - -/** - * clear_bmap_size: calculate clear bitmap size - * - * @pages: number of guest pages - * @shift: guest page number shift - * - * Returns: number of bits for the clear bitmap - */ -static inline long clear_bmap_size(uint64_t pages, uint8_t shift) -{ - return DIV_ROUND_UP(pages, 1UL << shift); -} - -/** - * clear_bmap_set: set clear bitmap for the page range. Must be with - * bitmap_mutex held. - * - * @rb: the ramblock to operate on - * @start: the start page number - * @size: number of pages to set in the bitmap - * - * Returns: None - */ -static inline void clear_bmap_set(RAMBlock *rb, uint64_t start, - uint64_t npages) -{ - uint8_t shift = rb->clear_bmap_shift; - - bitmap_set(rb->clear_bmap, start >> shift, clear_bmap_size(npages, shift)); -} - -/** - * clear_bmap_test_and_clear: test clear bitmap for the page, clear if set. - * Must be with bitmap_mutex held. - * - * @rb: the ramblock to operate on - * @page: the page number to check - * - * Returns: true if the bit was set, false otherwise - */ -static inline bool clear_bmap_test_and_clear(RAMBlock *rb, uint64_t page) -{ - uint8_t shift = rb->clear_bmap_shift; - - return bitmap_test_and_clear(rb->clear_bmap, page >> shift, 1); -} - -static inline bool offset_in_ramblock(RAMBlock *b, ram_addr_t offset) -{ - return (b && b->host && offset < b->used_length) ? true : false; -} - -static inline void *ramblock_ptr(RAMBlock *block, ram_addr_t offset) -{ - assert(offset_in_ramblock(block, offset)); - return (char *)block->host + offset; -} - -static inline unsigned long int ramblock_recv_bitmap_offset(void *host_addr, - RAMBlock *rb) -{ - uint64_t host_addr_offset = - (uint64_t)(uintptr_t)(host_addr - (void *)rb->host); - return host_addr_offset >> TARGET_PAGE_BITS; -} bool ramblock_is_pmem(RAMBlock *rb); @@ -143,411 +67,6 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp); void qemu_ram_msync(RAMBlock *block, ram_addr_t start, ram_addr_t length); -/* Clear whole block of mem */ -static inline void qemu_ram_block_writeback(RAMBlock *block) -{ - qemu_ram_msync(block, 0, block->used_length); -} +#endif /* CONFIG_USER_ONLY */ -#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) -#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE)) - -static inline bool cpu_physical_memory_get_dirty(ram_addr_t start, - ram_addr_t length, - unsigned client) -{ - DirtyMemoryBlocks *blocks; - unsigned long end, page; - unsigned long idx, offset, base; - bool dirty = false; - - assert(client < DIRTY_MEMORY_NUM); - - end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; - page = start >> TARGET_PAGE_BITS; - - WITH_RCU_READ_LOCK_GUARD() { - blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); - - idx = page / DIRTY_MEMORY_BLOCK_SIZE; - offset = page % DIRTY_MEMORY_BLOCK_SIZE; - base = page - offset; - while (page < end) { - unsigned long next = MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); - unsigned long num = next - base; - unsigned long found = find_next_bit(blocks->blocks[idx], - num, offset); - if (found < num) { - dirty = true; - break; - } - - page = next; - idx++; - offset = 0; - base += DIRTY_MEMORY_BLOCK_SIZE; - } - } - - return dirty; -} - -static inline bool cpu_physical_memory_all_dirty(ram_addr_t start, - ram_addr_t length, - unsigned client) -{ - DirtyMemoryBlocks *blocks; - unsigned long end, page; - unsigned long idx, offset, base; - bool dirty = true; - - assert(client < DIRTY_MEMORY_NUM); - - end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; - page = start >> TARGET_PAGE_BITS; - - RCU_READ_LOCK_GUARD(); - - blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); - - idx = page / DIRTY_MEMORY_BLOCK_SIZE; - offset = page % DIRTY_MEMORY_BLOCK_SIZE; - base = page - offset; - while (page < end) { - unsigned long next = MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); - unsigned long num = next - base; - unsigned long found = find_next_zero_bit(blocks->blocks[idx], num, offset); - if (found < num) { - dirty = false; - break; - } - - page = next; - idx++; - offset = 0; - base += DIRTY_MEMORY_BLOCK_SIZE; - } - - return dirty; -} - -static inline bool cpu_physical_memory_get_dirty_flag(ram_addr_t addr, - unsigned client) -{ - return cpu_physical_memory_get_dirty(addr, 1, client); -} - -static inline bool cpu_physical_memory_is_clean(ram_addr_t addr) -{ - bool vga = cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_VGA); - bool code = cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_CODE); - bool migration = - cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_MIGRATION); - return !(vga && code && migration); -} - -static inline uint8_t cpu_physical_memory_range_includes_clean(ram_addr_t start, - ram_addr_t length, - uint8_t mask) -{ - uint8_t ret = 0; - - if (mask & (1 << DIRTY_MEMORY_VGA) && - !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_VGA)) { - ret |= (1 << DIRTY_MEMORY_VGA); - } - if (mask & (1 << DIRTY_MEMORY_CODE) && - !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_CODE)) { - ret |= (1 << DIRTY_MEMORY_CODE); - } - if (mask & (1 << DIRTY_MEMORY_MIGRATION) && - !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_MIGRATION)) { - ret |= (1 << DIRTY_MEMORY_MIGRATION); - } - return ret; -} - -static inline void cpu_physical_memory_set_dirty_flag(ram_addr_t addr, - unsigned client) -{ - unsigned long page, idx, offset; - DirtyMemoryBlocks *blocks; - - assert(client < DIRTY_MEMORY_NUM); - - page = addr >> TARGET_PAGE_BITS; - idx = page / DIRTY_MEMORY_BLOCK_SIZE; - offset = page % DIRTY_MEMORY_BLOCK_SIZE; - - RCU_READ_LOCK_GUARD(); - - blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); - - set_bit_atomic(offset, blocks->blocks[idx]); -} - -static inline void cpu_physical_memory_set_dirty_range(ram_addr_t start, - ram_addr_t length, - uint8_t mask) -{ - DirtyMemoryBlocks *blocks[DIRTY_MEMORY_NUM]; - unsigned long end, page; - unsigned long idx, offset, base; - int i; - - if (!mask && !xen_enabled()) { - return; - } - - end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; - page = start >> TARGET_PAGE_BITS; - - WITH_RCU_READ_LOCK_GUARD() { - for (i = 0; i < DIRTY_MEMORY_NUM; i++) { - blocks[i] = qatomic_rcu_read(&ram_list.dirty_memory[i]); - } - - idx = page / DIRTY_MEMORY_BLOCK_SIZE; - offset = page % DIRTY_MEMORY_BLOCK_SIZE; - base = page - offset; - while (page < end) { - unsigned long next = MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); - - if (likely(mask & (1 << DIRTY_MEMORY_MIGRATION))) { - bitmap_set_atomic(blocks[DIRTY_MEMORY_MIGRATION]->blocks[idx], - offset, next - page); - } - if (unlikely(mask & (1 << DIRTY_MEMORY_VGA))) { - bitmap_set_atomic(blocks[DIRTY_MEMORY_VGA]->blocks[idx], - offset, next - page); - } - if (unlikely(mask & (1 << DIRTY_MEMORY_CODE))) { - bitmap_set_atomic(blocks[DIRTY_MEMORY_CODE]->blocks[idx], - offset, next - page); - } - - page = next; - idx++; - offset = 0; - base += DIRTY_MEMORY_BLOCK_SIZE; - } - } - - xen_hvm_modified_memory(start, length); -} - -#if !defined(_WIN32) - -/* - * Contrary to cpu_physical_memory_sync_dirty_bitmap() this function returns - * the number of dirty pages in @bitmap passed as argument. On the other hand, - * cpu_physical_memory_sync_dirty_bitmap() returns newly dirtied pages that - * weren't set in the global migration bitmap. - */ -static inline -uint64_t cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap, - ram_addr_t start, - ram_addr_t pages) -{ - unsigned long i, j; - unsigned long page_number, c, nbits; - hwaddr addr; - ram_addr_t ram_addr; - uint64_t num_dirty = 0; - unsigned long len = (pages + HOST_LONG_BITS - 1) / HOST_LONG_BITS; - unsigned long hpratio = qemu_real_host_page_size() / TARGET_PAGE_SIZE; - unsigned long page = BIT_WORD(start >> TARGET_PAGE_BITS); - - /* start address is aligned at the start of a word? */ - if ((((page * BITS_PER_LONG) << TARGET_PAGE_BITS) == start) && - (hpratio == 1)) { - unsigned long **blocks[DIRTY_MEMORY_NUM]; - unsigned long idx; - unsigned long offset; - long k; - long nr = BITS_TO_LONGS(pages); - - idx = (start >> TARGET_PAGE_BITS) / DIRTY_MEMORY_BLOCK_SIZE; - offset = BIT_WORD((start >> TARGET_PAGE_BITS) % - DIRTY_MEMORY_BLOCK_SIZE); - - WITH_RCU_READ_LOCK_GUARD() { - for (i = 0; i < DIRTY_MEMORY_NUM; i++) { - blocks[i] = - qatomic_rcu_read(&ram_list.dirty_memory[i])->blocks; - } - - for (k = 0; k < nr; k++) { - if (bitmap[k]) { - unsigned long temp = leul_to_cpu(bitmap[k]); - - nbits = ctpopl(temp); - qatomic_or(&blocks[DIRTY_MEMORY_VGA][idx][offset], temp); - - if (global_dirty_tracking) { - qatomic_or( - &blocks[DIRTY_MEMORY_MIGRATION][idx][offset], - temp); - if (unlikely( - global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RATE)) { - total_dirty_pages += nbits; - } - } - - num_dirty += nbits; - - if (tcg_enabled()) { - qatomic_or(&blocks[DIRTY_MEMORY_CODE][idx][offset], - temp); - } - } - - if (++offset >= BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { - offset = 0; - idx++; - } - } - } - - xen_hvm_modified_memory(start, pages << TARGET_PAGE_BITS); - } else { - uint8_t clients = tcg_enabled() ? DIRTY_CLIENTS_ALL : DIRTY_CLIENTS_NOCODE; - - if (!global_dirty_tracking) { - clients &= ~(1 << DIRTY_MEMORY_MIGRATION); - } - - /* - * bitmap-traveling is faster than memory-traveling (for addr...) - * especially when most of the memory is not dirty. - */ - for (i = 0; i < len; i++) { - if (bitmap[i] != 0) { - c = leul_to_cpu(bitmap[i]); - nbits = ctpopl(c); - if (unlikely(global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RATE)) { - total_dirty_pages += nbits; - } - num_dirty += nbits; - do { - j = ctzl(c); - c &= ~(1ul << j); - page_number = (i * HOST_LONG_BITS + j) * hpratio; - addr = page_number * TARGET_PAGE_SIZE; - ram_addr = start + addr; - cpu_physical_memory_set_dirty_range(ram_addr, - TARGET_PAGE_SIZE * hpratio, clients); - } while (c != 0); - } - } - } - - return num_dirty; -} -#endif /* not _WIN32 */ - -static inline void cpu_physical_memory_dirty_bits_cleared(ram_addr_t start, - ram_addr_t length) -{ - if (tcg_enabled()) { - tlb_reset_dirty_range_all(start, length); - } - -} -bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, - ram_addr_t length, - unsigned client); - -DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty - (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client); - -bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, - ram_addr_t start, - ram_addr_t length); - -static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, - ram_addr_t length) -{ - cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_MIGRATION); - cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_VGA); - cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_CODE); -} - - -/* Called with RCU critical section */ -static inline -uint64_t cpu_physical_memory_sync_dirty_bitmap(RAMBlock *rb, - ram_addr_t start, - ram_addr_t length) -{ - ram_addr_t addr; - unsigned long word = BIT_WORD((start + rb->offset) >> TARGET_PAGE_BITS); - uint64_t num_dirty = 0; - unsigned long *dest = rb->bmap; - - /* start address and length is aligned at the start of a word? */ - if (((word * BITS_PER_LONG) << TARGET_PAGE_BITS) == - (start + rb->offset) && - !(length & ((BITS_PER_LONG << TARGET_PAGE_BITS) - 1))) { - int k; - int nr = BITS_TO_LONGS(length >> TARGET_PAGE_BITS); - unsigned long * const *src; - unsigned long idx = (word * BITS_PER_LONG) / DIRTY_MEMORY_BLOCK_SIZE; - unsigned long offset = BIT_WORD((word * BITS_PER_LONG) % - DIRTY_MEMORY_BLOCK_SIZE); - unsigned long page = BIT_WORD(start >> TARGET_PAGE_BITS); - - src = qatomic_rcu_read( - &ram_list.dirty_memory[DIRTY_MEMORY_MIGRATION])->blocks; - - for (k = page; k < page + nr; k++) { - if (src[idx][offset]) { - unsigned long bits = qatomic_xchg(&src[idx][offset], 0); - unsigned long new_dirty; - new_dirty = ~dest[k]; - dest[k] |= bits; - new_dirty &= bits; - num_dirty += ctpopl(new_dirty); - } - - if (++offset >= BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { - offset = 0; - idx++; - } - } - if (num_dirty) { - cpu_physical_memory_dirty_bits_cleared(start, length); - } - - if (rb->clear_bmap) { - /* - * Postpone the dirty bitmap clear to the point before we - * really send the pages, also we will split the clear - * dirty procedure into smaller chunks. - */ - clear_bmap_set(rb, start >> TARGET_PAGE_BITS, - length >> TARGET_PAGE_BITS); - } else { - /* Slow path - still do that in a huge chunk */ - memory_region_clear_dirty_bitmap(rb->mr, start, length); - } - } else { - ram_addr_t offset = rb->offset; - - for (addr = 0; addr < length; addr += TARGET_PAGE_SIZE) { - if (cpu_physical_memory_test_and_clear_dirty( - start + addr + offset, - TARGET_PAGE_SIZE, - DIRTY_MEMORY_MIGRATION)) { - long k = (start + addr) >> TARGET_PAGE_BITS; - if (!test_and_set_bit(k, dest)) { - num_dirty++; - } - } - } - } - - return num_dirty; -} -#endif #endif diff --git a/include/sysemu/physmem-target.h b/include/sysemu/physmem-target.h new file mode 100644 index 0000000000..b30c42da60 --- /dev/null +++ b/include/sysemu/physmem-target.h @@ -0,0 +1,506 @@ +/* + * Declarations for cpu physical memory functions + * + * Copyright 2011 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Avi Kivity + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + * + */ + +/* + * This header is for use by exec.c and memory.c ONLY. Do not include it. + * The functions declared here will be removed soon. + */ + +#ifndef RAM_ADDR_TARGET_H +#define RAM_ADDR_TARGET_H + +#include "cpu.h" +#include "sysemu/xen.h" +#include "sysemu/tcg.h" +#include "exec/cputlb.h" +#include "exec/ram_addr.h" +#include "exec/ramlist.h" +#include "exec/ramblock.h" +#include "qemu/rcu.h" + +extern uint64_t total_dirty_pages; + +/** + * clear_bmap_size: calculate clear bitmap size + * + * @pages: number of guest pages + * @shift: guest page number shift + * + * Returns: number of bits for the clear bitmap + */ +static inline long clear_bmap_size(uint64_t pages, uint8_t shift) +{ + return DIV_ROUND_UP(pages, 1UL << shift); +} + +/** + * clear_bmap_set: set clear bitmap for the page range. Must be with + * bitmap_mutex held. + * + * @rb: the ramblock to operate on + * @start: the start page number + * @size: number of pages to set in the bitmap + * + * Returns: None + */ +static inline void clear_bmap_set(RAMBlock *rb, uint64_t start, + uint64_t npages) +{ + uint8_t shift = rb->clear_bmap_shift; + + bitmap_set(rb->clear_bmap, start >> shift, clear_bmap_size(npages, shift)); +} + +/** + * clear_bmap_test_and_clear: test clear bitmap for the page, clear if set. + * Must be with bitmap_mutex held. + * + * @rb: the ramblock to operate on + * @page: the page number to check + * + * Returns: true if the bit was set, false otherwise + */ +static inline bool clear_bmap_test_and_clear(RAMBlock *rb, uint64_t page) +{ + uint8_t shift = rb->clear_bmap_shift; + + return bitmap_test_and_clear(rb->clear_bmap, page >> shift, 1); +} + +static inline bool offset_in_ramblock(RAMBlock *b, ram_addr_t offset) +{ + return (b && b->host && offset < b->used_length) ? true : false; +} + +static inline void *ramblock_ptr(RAMBlock *block, ram_addr_t offset) +{ + assert(offset_in_ramblock(block, offset)); + return (char *)block->host + offset; +} + +static inline unsigned long int ramblock_recv_bitmap_offset(void *host_addr, + RAMBlock *rb) +{ + uint64_t host_addr_offset = + (uint64_t)(uintptr_t)(host_addr - (void *)rb->host); + return host_addr_offset >> TARGET_PAGE_BITS; +} + +/* Clear whole block of mem */ +static inline void qemu_ram_block_writeback(RAMBlock *block) +{ + qemu_ram_msync(block, 0, block->used_length); +} + +#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) +#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE)) + +static inline bool cpu_physical_memory_get_dirty(ram_addr_t start, + ram_addr_t length, + unsigned client) +{ + DirtyMemoryBlocks *blocks; + unsigned long end, page; + unsigned long idx, offset, base; + bool dirty = false; + + assert(client < DIRTY_MEMORY_NUM); + + end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; + page = start >> TARGET_PAGE_BITS; + + WITH_RCU_READ_LOCK_GUARD() { + blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); + + idx = page / DIRTY_MEMORY_BLOCK_SIZE; + offset = page % DIRTY_MEMORY_BLOCK_SIZE; + base = page - offset; + while (page < end) { + unsigned long next = MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); + unsigned long num = next - base; + unsigned long found = find_next_bit(blocks->blocks[idx], + num, offset); + if (found < num) { + dirty = true; + break; + } + + page = next; + idx++; + offset = 0; + base += DIRTY_MEMORY_BLOCK_SIZE; + } + } + + return dirty; +} + +static inline bool cpu_physical_memory_all_dirty(ram_addr_t start, + ram_addr_t length, + unsigned client) +{ + DirtyMemoryBlocks *blocks; + unsigned long end, page; + unsigned long idx, offset, base; + bool dirty = true; + + assert(client < DIRTY_MEMORY_NUM); + + end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; + page = start >> TARGET_PAGE_BITS; + + RCU_READ_LOCK_GUARD(); + + blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); + + idx = page / DIRTY_MEMORY_BLOCK_SIZE; + offset = page % DIRTY_MEMORY_BLOCK_SIZE; + base = page - offset; + while (page < end) { + unsigned long next = MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); + unsigned long num = next - base; + unsigned long found = find_next_zero_bit(blocks->blocks[idx], num, offset); + if (found < num) { + dirty = false; + break; + } + + page = next; + idx++; + offset = 0; + base += DIRTY_MEMORY_BLOCK_SIZE; + } + + return dirty; +} + +static inline bool cpu_physical_memory_get_dirty_flag(ram_addr_t addr, + unsigned client) +{ + return cpu_physical_memory_get_dirty(addr, 1, client); +} + +static inline bool cpu_physical_memory_is_clean(ram_addr_t addr) +{ + bool vga = cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_VGA); + bool code = cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_CODE); + bool migration = + cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_MIGRATION); + return !(vga && code && migration); +} + +static inline uint8_t cpu_physical_memory_range_includes_clean(ram_addr_t start, + ram_addr_t length, + uint8_t mask) +{ + uint8_t ret = 0; + + if (mask & (1 << DIRTY_MEMORY_VGA) && + !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_VGA)) { + ret |= (1 << DIRTY_MEMORY_VGA); + } + if (mask & (1 << DIRTY_MEMORY_CODE) && + !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_CODE)) { + ret |= (1 << DIRTY_MEMORY_CODE); + } + if (mask & (1 << DIRTY_MEMORY_MIGRATION) && + !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_MIGRATION)) { + ret |= (1 << DIRTY_MEMORY_MIGRATION); + } + return ret; +} + +static inline void cpu_physical_memory_set_dirty_flag(ram_addr_t addr, + unsigned client) +{ + unsigned long page, idx, offset; + DirtyMemoryBlocks *blocks; + + assert(client < DIRTY_MEMORY_NUM); + + page = addr >> TARGET_PAGE_BITS; + idx = page / DIRTY_MEMORY_BLOCK_SIZE; + offset = page % DIRTY_MEMORY_BLOCK_SIZE; + + RCU_READ_LOCK_GUARD(); + + blocks = qatomic_rcu_read(&ram_list.dirty_memory[client]); + + set_bit_atomic(offset, blocks->blocks[idx]); +} + +static inline void cpu_physical_memory_set_dirty_range(ram_addr_t start, + ram_addr_t length, + uint8_t mask) +{ + DirtyMemoryBlocks *blocks[DIRTY_MEMORY_NUM]; + unsigned long end, page; + unsigned long idx, offset, base; + int i; + + if (!mask && !xen_enabled()) { + return; + } + + end = TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; + page = start >> TARGET_PAGE_BITS; + + WITH_RCU_READ_LOCK_GUARD() { + for (i = 0; i < DIRTY_MEMORY_NUM; i++) { + blocks[i] = qatomic_rcu_read(&ram_list.dirty_memory[i]); + } + + idx = page / DIRTY_MEMORY_BLOCK_SIZE; + offset = page % DIRTY_MEMORY_BLOCK_SIZE; + base = page - offset; + while (page < end) { + unsigned long next = MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); + + if (likely(mask & (1 << DIRTY_MEMORY_MIGRATION))) { + bitmap_set_atomic(blocks[DIRTY_MEMORY_MIGRATION]->blocks[idx], + offset, next - page); + } + if (unlikely(mask & (1 << DIRTY_MEMORY_VGA))) { + bitmap_set_atomic(blocks[DIRTY_MEMORY_VGA]->blocks[idx], + offset, next - page); + } + if (unlikely(mask & (1 << DIRTY_MEMORY_CODE))) { + bitmap_set_atomic(blocks[DIRTY_MEMORY_CODE]->blocks[idx], + offset, next - page); + } + + page = next; + idx++; + offset = 0; + base += DIRTY_MEMORY_BLOCK_SIZE; + } + } + + xen_hvm_modified_memory(start, length); +} + +#if !defined(_WIN32) + +/* + * Contrary to cpu_physical_memory_sync_dirty_bitmap() this function returns + * the number of dirty pages in @bitmap passed as argument. On the other hand, + * cpu_physical_memory_sync_dirty_bitmap() returns newly dirtied pages that + * weren't set in the global migration bitmap. + */ +static inline +uint64_t cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap, + ram_addr_t start, + ram_addr_t pages) +{ + unsigned long i, j; + unsigned long page_number, c, nbits; + hwaddr addr; + ram_addr_t ram_addr; + uint64_t num_dirty = 0; + unsigned long len = (pages + HOST_LONG_BITS - 1) / HOST_LONG_BITS; + unsigned long hpratio = qemu_real_host_page_size() / TARGET_PAGE_SIZE; + unsigned long page = BIT_WORD(start >> TARGET_PAGE_BITS); + + /* start address is aligned at the start of a word? */ + if ((((page * BITS_PER_LONG) << TARGET_PAGE_BITS) == start) && + (hpratio == 1)) { + unsigned long **blocks[DIRTY_MEMORY_NUM]; + unsigned long idx; + unsigned long offset; + long k; + long nr = BITS_TO_LONGS(pages); + + idx = (start >> TARGET_PAGE_BITS) / DIRTY_MEMORY_BLOCK_SIZE; + offset = BIT_WORD((start >> TARGET_PAGE_BITS) % + DIRTY_MEMORY_BLOCK_SIZE); + + WITH_RCU_READ_LOCK_GUARD() { + for (i = 0; i < DIRTY_MEMORY_NUM; i++) { + blocks[i] = + qatomic_rcu_read(&ram_list.dirty_memory[i])->blocks; + } + + for (k = 0; k < nr; k++) { + if (bitmap[k]) { + unsigned long temp = leul_to_cpu(bitmap[k]); + + nbits = ctpopl(temp); + qatomic_or(&blocks[DIRTY_MEMORY_VGA][idx][offset], temp); + + if (global_dirty_tracking) { + qatomic_or( + &blocks[DIRTY_MEMORY_MIGRATION][idx][offset], + temp); + if (unlikely( + global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RATE)) { + total_dirty_pages += nbits; + } + } + + num_dirty += nbits; + + if (tcg_enabled()) { + qatomic_or(&blocks[DIRTY_MEMORY_CODE][idx][offset], + temp); + } + } + + if (++offset >= BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { + offset = 0; + idx++; + } + } + } + + xen_hvm_modified_memory(start, pages << TARGET_PAGE_BITS); + } else { + uint8_t clients = tcg_enabled() ? DIRTY_CLIENTS_ALL : DIRTY_CLIENTS_NOCODE; + + if (!global_dirty_tracking) { + clients &= ~(1 << DIRTY_MEMORY_MIGRATION); + } + + /* + * bitmap-traveling is faster than memory-traveling (for addr...) + * especially when most of the memory is not dirty. + */ + for (i = 0; i < len; i++) { + if (bitmap[i] != 0) { + c = leul_to_cpu(bitmap[i]); + nbits = ctpopl(c); + if (unlikely(global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RATE)) { + total_dirty_pages += nbits; + } + num_dirty += nbits; + do { + j = ctzl(c); + c &= ~(1ul << j); + page_number = (i * HOST_LONG_BITS + j) * hpratio; + addr = page_number * TARGET_PAGE_SIZE; + ram_addr = start + addr; + cpu_physical_memory_set_dirty_range(ram_addr, + TARGET_PAGE_SIZE * hpratio, clients); + } while (c != 0); + } + } + } + + return num_dirty; +} +#endif /* not _WIN32 */ + +static inline void cpu_physical_memory_dirty_bits_cleared(ram_addr_t start, + ram_addr_t length) +{ + if (tcg_enabled()) { + tlb_reset_dirty_range_all(start, length); + } + +} +bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, + ram_addr_t length, + unsigned client); + +DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty + (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client); + +bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, + ram_addr_t start, + ram_addr_t length); + +static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, + ram_addr_t length) +{ + cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_MIGRATION); + cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_VGA); + cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_CODE); +} + + +/* Called with RCU critical section */ +static inline +uint64_t cpu_physical_memory_sync_dirty_bitmap(RAMBlock *rb, + ram_addr_t start, + ram_addr_t length) +{ + ram_addr_t addr; + unsigned long word = BIT_WORD((start + rb->offset) >> TARGET_PAGE_BITS); + uint64_t num_dirty = 0; + unsigned long *dest = rb->bmap; + + /* start address and length is aligned at the start of a word? */ + if (((word * BITS_PER_LONG) << TARGET_PAGE_BITS) == + (start + rb->offset) && + !(length & ((BITS_PER_LONG << TARGET_PAGE_BITS) - 1))) { + int k; + int nr = BITS_TO_LONGS(length >> TARGET_PAGE_BITS); + unsigned long * const *src; + unsigned long idx = (word * BITS_PER_LONG) / DIRTY_MEMORY_BLOCK_SIZE; + unsigned long offset = BIT_WORD((word * BITS_PER_LONG) % + DIRTY_MEMORY_BLOCK_SIZE); + unsigned long page = BIT_WORD(start >> TARGET_PAGE_BITS); + + src = qatomic_rcu_read( + &ram_list.dirty_memory[DIRTY_MEMORY_MIGRATION])->blocks; + + for (k = page; k < page + nr; k++) { + if (src[idx][offset]) { + unsigned long bits = qatomic_xchg(&src[idx][offset], 0); + unsigned long new_dirty; + new_dirty = ~dest[k]; + dest[k] |= bits; + new_dirty &= bits; + num_dirty += ctpopl(new_dirty); + } + + if (++offset >= BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { + offset = 0; + idx++; + } + } + if (num_dirty) { + cpu_physical_memory_dirty_bits_cleared(start, length); + } + + if (rb->clear_bmap) { + /* + * Postpone the dirty bitmap clear to the point before we + * really send the pages, also we will split the clear + * dirty procedure into smaller chunks. + */ + clear_bmap_set(rb, start >> TARGET_PAGE_BITS, + length >> TARGET_PAGE_BITS); + } else { + /* Slow path - still do that in a huge chunk */ + memory_region_clear_dirty_bitmap(rb->mr, start, length); + } + } else { + ram_addr_t offset = rb->offset; + + for (addr = 0; addr < length; addr += TARGET_PAGE_SIZE) { + if (cpu_physical_memory_test_and_clear_dirty( + start + addr + offset, + TARGET_PAGE_SIZE, + DIRTY_MEMORY_MIGRATION)) { + long k = (start + addr) >> TARGET_PAGE_BITS; + if (!test_and_set_bit(k, dest)) { + num_dirty++; + } + } + } + } + + return num_dirty; +} + +#endif diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 801cff16a5..a80547006b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -35,6 +35,7 @@ #include "qemu/bswap.h" #include "exec/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" #include "trace.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index dba4831cd1..d4b381641c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -28,6 +28,7 @@ #include "exec/tb-flush.h" #include "exec/memory-internal.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/mmu-access-type.h" #include "exec/tlb-common.h" #include "exec/vaddr.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fdf6d8ac19..48015be829 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -41,6 +41,7 @@ #endif #else #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #endif #include "exec/cputlb.h" diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 5c02037c56..a9833530c7 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -75,6 +75,7 @@ #include "hw/virtio/vhost-scsi-common.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/usb.h" #include "qemu/config-file.h" diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 2f74923560..5eef7475c1 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -28,6 +28,7 @@ #include "qapi/visitor.h" #include "sysemu/hw_accel.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "target/ppc/cpu.h" #include "target/ppc/mmu-hash64.h" #include "cpu-models.h" diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7e24084673..a91fea1304 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -35,6 +35,7 @@ #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include #include "trace.h" #include "qemu/error-report.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 6d60da91e0..0af2a2f3fe 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -12,6 +12,7 @@ #include "hw/remote/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qapi/error.h" static void remote_sysmem_reset(void) diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c index a926f61ebe..3948751ed7 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -13,6 +13,7 @@ #include "exec/memory.h" #include "exec/cpu-common.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/remote/mpqemu-link.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index eeaa811098..b495d81296 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -16,6 +16,7 @@ #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "kvm/kvm_s390x.h" #include "qapi/error.h" diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index c4259b5327..fe7945e856 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -17,6 +17,7 @@ #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qapi/qmp/qdict.h" #include "cpu.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index fe03f716f3..5b6fe1a18a 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/boards.h" #include "hw/s390x/s390-virtio-hcall.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index dcef44fe55..2e7a02cd4b 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -30,6 +30,7 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "hw/hw.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 9ccdb639ac..f0bc9e8c2b 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -26,6 +26,7 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qemu/range.h" #include "sysemu/reset.h" diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index e7bece4ea1..120c82f3de 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -26,6 +26,7 @@ #include "qemu/chardev_open.h" #include "pci.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" static int iommufd_cdev_map(const VFIOContainerBase *bcontainer, hwaddr iova, ram_addr_t size, void *vaddr, bool readonly) diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index 01aa11013e..f5698eeae0 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -27,6 +27,7 @@ #include "qapi/qapi-events-vfio.h" #include "exec/ramlist.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "pci.h" #include "trace.h" #include "hw/hw.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 018bd20481..980147338a 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -20,6 +20,7 @@ #include "hw/vfio/vfio-common.h" #include "hw/hw.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "trace.h" diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 80ada89551..dae94dbbde 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -25,6 +25,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "migration/misc.h" #include "hw/boards.h" #include "hw/qdev-properties.h" diff --git a/migration/ram.c b/migration/ram.c index 05ff9eb328..82c44e8213 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -49,6 +49,7 @@ #include "qapi/qmp/qerror.h" #include "trace.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/target_page.h" #include "qemu/rcu_queue.h" #include "migration/colo.h" diff --git a/plugins/api.c b/plugins/api.c index 24ea64e2de..77b55cff74 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -50,6 +50,7 @@ #include "qapi/error.h" #include "migration/blocker.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/plugin-memory.h" #include "hw/boards.h" #else diff --git a/system/memory.c b/system/memory.c index 85f6834cb3..7eae1bbda7 100644 --- a/system/memory.c +++ b/system/memory.c @@ -27,6 +27,7 @@ #include "exec/memory-internal.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/tcg.h" diff --git a/system/physmem.c b/system/physmem.c index 3f937a5e58..26cfb84454 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -67,6 +67,7 @@ #include "exec/memory-internal.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/pmem.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index b017b26d07..0950a1c6f1 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -25,6 +25,7 @@ #include "exec/page-protection.h" #ifndef CONFIG_USER_ONLY #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 3efc28f18b..f764931426 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -42,6 +42,7 @@ #include "gdbstub/enums.h" #include "exec/memattrs.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "sysemu/hostmem.h" #include "qemu/cutils.h" #include "qemu/main-loop.h" diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 8ffe0159d8..c8045d873c 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -42,6 +42,7 @@ #include "sysemu/device_tree.h" #include "gdbstub/enums.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "trace.h" #include "hw/s390x/s390-pci-inst.h" #include "hw/s390x/s390-pci-bus.h" From patchwork Thu Nov 14 01:13:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B7C0D637D6 for ; Thu, 14 Nov 2024 01:19:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTS-00044B-Al; Wed, 13 Nov 2024 20:16:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOT0-0002VS-IQ for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:16 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOSx-00031y-Sq for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:14 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-431616c23b5so205305e9.0 for ; Wed, 13 Nov 2024 17:16:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546969; x=1732151769; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dJnPLBXDUWt9APABFP9RtiuQUlaLpT6eHtJy+a+Whyg=; b=qSC2iR3FZXQ9xvcsI53Cva0/uYAFxHj+GyOAmpyHInvli7a3m+TRmBsokfSUeheQD6 5pBBDLn+iRIGWrq4mHs24modnt7mMF8QtnlDY1ALgRaHcgt3z2EFGBYDOvpD+NEXgqZ8 v9fxuS1RSgwfz6k4y6wzk5Aq/iiFZ5OuopnyrGOxuItaqa/Gd7agNItE9Xgdv3sKOi9s GGuZZUCNG40cuOSKjVsw4GOKU4zpQ+KcOhL47kr7MQaE/JR0rA4GuXIPfRxhoQgptGm4 4R3pA07Pw8BoPwOQc5cejTOwPkvZpeqxqP+R/N59rNViHh+Z+JNlbAMrJiqmv9kjh+oy 5hkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546969; x=1732151769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dJnPLBXDUWt9APABFP9RtiuQUlaLpT6eHtJy+a+Whyg=; b=qzRadUCaYawoPH7HmJPN2dl0lxKD8sMJmVVRWEOMOZ0Du8FrH5bo/Qhcessv14AWJ8 VT7M/GeTkK2XwZua5BsLSgdBeBYx++o+Xs18NViUpY7kksegtRThfsQ5DYbtmj3jqQOS gj0diBgVKwRUQ9e2q1HRvqi2fJ3zyzhADvakT7rTmRqMKlc3juqk4nuW2msE3G+irXWZ Ta7k3PZ3FhxmfeLXPDeZ6V7DI/Kj+hfsdI13E2cdrPoUgEjPRibzvPQR2XIionvm2WuX 0h3ObfCii7Abl4ej8EOemabrAZH81w3p+yv/XzbpUTOy21yRyfB7SFW1v+GGWqWWtue5 41Qg== X-Forwarded-Encrypted: i=1; AJvYcCUStxbJ5Q53DcXNf3lxQ5YPMb29vfJS6H8ypYnu0Wqvbz8Y+Zu9i/bTklyvVePSY//30OEcXuu7Zqke@nongnu.org X-Gm-Message-State: AOJu0YwSKlxS391guXvV1spxOCNm4LtpX99xNzFDEeFt9YxtfxMXD/E0 RHzsNQ4VU0kPttJvc2kyblFjF63QqUHwINo1MmPuH2/edLiIl+PDs6u5x7nzQ9Gpan1O1NACxdZ y X-Google-Smtp-Source: AGHT+IFNRYI+6+k6hzZD/Oqm3sK6NGybQN7v5rJRv2V4XIRC72YBhh+g6R+IRQke+T79tc6rz4+9zg== X-Received: by 2002:a05:600c:4fc5:b0:431:55f3:d34e with SMTP id 5b1f17b1804b1-432d9761bdcmr12005115e9.15.1731546969598; Wed, 13 Nov 2024 17:16:09 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da280018sm4774385e9.26.2024.11.13.17.16.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:16:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 22/24] exec/cpu-common: Move ram_addr_t related methods to 'exec/ram_addr.h' Date: Thu, 14 Nov 2024 02:13:07 +0100 Message-ID: <20241114011310.3615-23-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move methods related to the ram_addr_t type to the specific "exec/ram_addr.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 56 +------------------------------- include/exec/ram_addr.h | 56 ++++++++++++++++++++++++++++++++ include/exec/translation-block.h | 2 +- 3 files changed, 58 insertions(+), 56 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 638dc806a5..b790202c56 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -54,61 +54,7 @@ enum device_endian { #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN #endif -/* address in the RAM (different from a physical address) */ -#if defined(CONFIG_XEN_BACKEND) -typedef uint64_t ram_addr_t; -# define RAM_ADDR_MAX UINT64_MAX -# define RAM_ADDR_FMT "%" PRIx64 -#else -typedef uintptr_t ram_addr_t; -# define RAM_ADDR_MAX UINTPTR_MAX -# define RAM_ADDR_FMT "%" PRIxPTR -#endif - -/* memory API */ - -void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); -/* This should not be used by devices. */ -ram_addr_t qemu_ram_addr_from_host(void *ptr); -ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); -RAMBlock *qemu_ram_block_by_name(const char *name); - -/* - * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. - * - * @ptr: The host pointer to translate. - * @round_offset: Whether to round the result offset down to a target page - * @offset: Will be set to the offset within the returned RAMBlock. - * - * Returns: RAMBlock (or NULL if not found) - * - * By the time this function returns, the returned pointer is not protected - * by RCU anymore. If the caller is not within an RCU critical section and - * does not hold the BQL, it must have other means of protecting the - * pointer, such as a reference to the memory region that owns the RAMBlock. - */ -RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, - ram_addr_t *offset); -ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); -void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); -void qemu_ram_unset_idstr(RAMBlock *block); -const char *qemu_ram_get_idstr(RAMBlock *rb); -void *qemu_ram_get_host_addr(RAMBlock *rb); -ram_addr_t qemu_ram_get_offset(RAMBlock *rb); -ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); -ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); -bool qemu_ram_is_shared(RAMBlock *rb); -bool qemu_ram_is_noreserve(RAMBlock *rb); -bool qemu_ram_is_uf_zeroable(RAMBlock *rb); -void qemu_ram_set_uf_zeroable(RAMBlock *rb); -bool qemu_ram_is_migratable(RAMBlock *rb); -void qemu_ram_set_migratable(RAMBlock *rb); -void qemu_ram_unset_migratable(RAMBlock *rb); -bool qemu_ram_is_named_file(RAMBlock *rb); -int qemu_ram_get_fd(RAMBlock *rb); - -size_t qemu_ram_pagesize(RAMBlock *block); -size_t qemu_ram_pagesize_largest(void); +#include "exec/ram_addr.h" /** * cpu_address_space_init: diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 80f6dc7564..e0620ddb03 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -21,6 +21,62 @@ #ifndef CONFIG_USER_ONLY +/* address in the RAM (different from a physical address) */ +#if defined(CONFIG_XEN_BACKEND) +typedef uint64_t ram_addr_t; +# define RAM_ADDR_MAX UINT64_MAX +# define RAM_ADDR_FMT "%" PRIx64 +#else +typedef uintptr_t ram_addr_t; +# define RAM_ADDR_MAX UINTPTR_MAX +# define RAM_ADDR_FMT "%" PRIxPTR +#endif + +/* memory API */ + +void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); +/* This should not be used by devices. */ +ram_addr_t qemu_ram_addr_from_host(void *ptr); +ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); +RAMBlock *qemu_ram_block_by_name(const char *name); + +/* + * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. + * + * @ptr: The host pointer to translate. + * @round_offset: Whether to round the result offset down to a target page + * @offset: Will be set to the offset within the returned RAMBlock. + * + * Returns: RAMBlock (or NULL if not found) + * + * By the time this function returns, the returned pointer is not protected + * by RCU anymore. If the caller is not within an RCU critical section and + * does not hold the BQL, it must have other means of protecting the + * pointer, such as a reference to the memory region that owns the RAMBlock. + */ +RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, + ram_addr_t *offset); +ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); +void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); +void qemu_ram_unset_idstr(RAMBlock *block); +const char *qemu_ram_get_idstr(RAMBlock *rb); +void *qemu_ram_get_host_addr(RAMBlock *rb); +ram_addr_t qemu_ram_get_offset(RAMBlock *rb); +ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); +ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); +bool qemu_ram_is_shared(RAMBlock *rb); +bool qemu_ram_is_noreserve(RAMBlock *rb); +bool qemu_ram_is_uf_zeroable(RAMBlock *rb); +void qemu_ram_set_uf_zeroable(RAMBlock *rb); +bool qemu_ram_is_migratable(RAMBlock *rb); +void qemu_ram_set_migratable(RAMBlock *rb); +void qemu_ram_unset_migratable(RAMBlock *rb); +bool qemu_ram_is_named_file(RAMBlock *rb); +int qemu_ram_get_fd(RAMBlock *rb); + +size_t qemu_ram_pagesize(RAMBlock *block); +size_t qemu_ram_pagesize_largest(void); + bool ramblock_is_pmem(RAMBlock *rb); long qemu_minrampagesize(void); diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index b99afb0077..9c4757882c 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -8,7 +8,7 @@ #define EXEC_TRANSLATION_BLOCK_H #include "qemu/thread.h" -#include "exec/cpu-common.h" +#include "exec/ram_addr.h" #include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" From patchwork Thu Nov 14 01:13:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D82BD637CF for ; Thu, 14 Nov 2024 01:20:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTf-0005AH-11; Wed, 13 Nov 2024 20:16:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOT8-0002lZ-Qv for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:27 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOT5-00033V-Hk for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:22 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-432d9b8558aso1338715e9.0 for ; Wed, 13 Nov 2024 17:16:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546976; x=1732151776; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ziBtbUpyHfOZqiArsxZ9RJYwzJ+JBpYBES4OJcXpO28=; b=b9V29geIA63RWvK70AshU6nqkTu5Aao0j9jkH0Anqjh6sXLct2VVw2a6v9twfyywvd aoHLgmBkFK772VmW8Q4mtufQ7ZCnAom42IBTUc6ZpNt6hv39C7gfgt8/j/VltrxsquKK 1cstdhG9/s7CK64RWmieqA7H1hVCoqk0IVZQggvLqpKXS40YNxHzZcajQV+9i1+0vI9/ lcHNU5DI77Bz/7urLYpntH49vXCoHbulev5AcI5pa0vhVPRoZH6Iy5TxhRR+lV4H9AX8 2Y5izbohH6JdJieVj+onA5KRolW5dktWhQnTNllJ9Z3+Nk0oHSA+rxoozGadXrwapS9g 0Oew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546976; x=1732151776; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ziBtbUpyHfOZqiArsxZ9RJYwzJ+JBpYBES4OJcXpO28=; b=s0am7bK9cIU1FidyVDIKkFmYnx9K3Ezq4tCgbidPFzCyNWYSDb5I77RrdEHjV1T38A bvRnoKv+de9Jwn1mpfLRR0DPjZ+2sZ+LCu1OFiOl4dmOY1DH38h4PqRBQUhij9ig2nTi OQsAFpAHsVZcCsxZr1mb9HVCeB78Zs7pB9lui/V377W3GXNfFlE9dJ1c/clChEkRkZKI 5biuenCKFgHUUSzeM4i5qYkf1B+/70SGoyhX1KuXnOV3LwFku1Rusvfw/qn9Ev98VQWL FfJ8KJ5G97YVQukU9QBMbLdxx5Tmw8LG7SovErVgXnPDiuBr/kR+pyFjJwCdDdfry+C/ Gc5g== X-Forwarded-Encrypted: i=1; AJvYcCUBzwhuFlFhqjwuy4pqEIVM6lBzbagPa9ppaw4mhY89n5VxodQOIRyIX9I15X9O1sgQ9BjshDRPuKoO@nongnu.org X-Gm-Message-State: AOJu0YzG/NdtL5u7nkj77RWIrBbk4sMzOBZU6ZlQ+FiUXewlSz0eFY13 sdby2l3icPIyupqZJpuvWsb29o761RsqqXZqjAsVLtYRf0GSi709C28cn4pFy0o= X-Google-Smtp-Source: AGHT+IFG/ZF691knJltVBevXFTBqGvTEtAKOLukeJC55OBRtxqlY2UQOjoHdG6QCpoUL0VTdcMqiXw== X-Received: by 2002:a5d:47a8:0:b0:381:f443:21c6 with SMTP id ffacd0b85a97d-38213f80149mr1345659f8f.0.1731546976466; Wed, 13 Nov 2024 17:16:16 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381ed97db25sm19856743f8f.41.2024.11.13.17.16.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:16:15 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 23/24] exec/memory: Move qemu_map_ram_ptr() declaration to 'exec/ram_addr.h' Date: Thu, 14 Nov 2024 02:13:08 +0100 Message-ID: <20241114011310.3615-24-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/memory.h | 2 +- include/exec/ram_addr.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 9458e2801d..58faa3eb08 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -28,6 +28,7 @@ #include "qemu/notify.h" #include "qom/object.h" #include "qemu/rcu.h" +#include "exec/ram_addr.h" #define RAM_ADDR_INVALID (~(ram_addr_t)0) @@ -2973,7 +2974,6 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, MemTxAttrs attrs, void *buf, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr); -void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr); /* Internal functions, part of the implementation of address_space_read_cached * and address_space_write_cached. */ diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index e0620ddb03..c4f220ae93 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -73,6 +73,7 @@ void qemu_ram_set_migratable(RAMBlock *rb); void qemu_ram_unset_migratable(RAMBlock *rb); bool qemu_ram_is_named_file(RAMBlock *rb); int qemu_ram_get_fd(RAMBlock *rb); +void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr); size_t qemu_ram_pagesize(RAMBlock *block); size_t qemu_ram_pagesize_largest(void); From patchwork Thu Nov 14 01:13:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13874448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31614D637D5 for ; Thu, 14 Nov 2024 01:20:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBOTZ-0004iB-5O; Wed, 13 Nov 2024 20:16:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBOTG-00039o-Mk for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:30 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBOTC-00035S-O7 for qemu-devel@nongnu.org; Wed, 13 Nov 2024 20:16:30 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-382171e1a83so137267f8f.0 for ; Wed, 13 Nov 2024 17:16:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731546985; x=1732151785; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/i7abgIX+3ynadFwtVOHIgRvjRLqB047FgJOUkSoXwQ=; b=fMp5Q3OUwLpYyOYouxgBoZr673RHgWhi3VwT1HcYemLC+aCGHz2G0czLr6D9Yjwhye GhcsQGttm8NANIXVKCBF1vVB4ImCO+7D0ihYmgFYhdv0IU/GMHj+OHh1dcH0sXiMOwrY JMO185I3zDHj7YOfAXusSyB+zkqp42qsKEboWBteSguXQm5V5TODhWSoHMJcsUAkYb1X TYjyhUIK/miJAnwwl0m0q+z9i+Bhax9FMjUdXOBKh43HnroeVB3epKjGadFLOCvRv00V RCeg9ywd0A91VvWjayd9y6kzgU2MpdfYaLcndIdKAIZVnqEFG1Vxqmg3Y7TmG54xZH/c iP5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731546985; x=1732151785; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/i7abgIX+3ynadFwtVOHIgRvjRLqB047FgJOUkSoXwQ=; b=hSiFz1DcB6cFjqe/6Sl+oGs2nC/IQ/5KBO5XEyoujtT644DEY73jY3E8G46kasfyIb aDyXktjO15fBesShal0Qyq++rM/8el+XLCzNjBeNWcyyzooGGmryZfQvQQ+FmDYYcCIV ExqHgySYOgShp5UxGbsA56NTZFAHPuSljYIyOxh789wHCpSWtwQ0Y6G/GtCoqhsWlzNd nlaba4YeuPZ4ZV6fAie7cKQ9JPXKdMM0f0NOg/nQgvYlNp8+W7JK55gkKoMOG/sjcDTh lw+IwIWC17qVMXu+q12+8l5t7yFkBs7pGDeNC0L0ASq3/v6fLVZmsExbXOvcHc29o9Uk XJ7w== X-Forwarded-Encrypted: i=1; AJvYcCXqhPjS9uDX+H6dVGhHNJVQ47YkOZHwcr9PUHAuQXeEH7jX6SX6VPwNr032rrPKJfz25fffq/nSxH9j@nongnu.org X-Gm-Message-State: AOJu0YzGYXsK0vOf+jm/+wmciKh0O3Upq+cey8HJ4COPGO7/YeUESZ9z 6ATZDcldxwqmgSwBGlhnIS7m88V6W4X2H+hFWGqHNh9MPch9jkV3HyyOPxaRQ+M= X-Google-Smtp-Source: AGHT+IFCBCAt12OLqgLDDZHzh68q86+ysDJJZpWlHumLNgL12t17vmSl5EE0M1zOwpQgowR0MbnrnA== X-Received: by 2002:a05:6000:2a3:b0:371:6fc7:d45d with SMTP id ffacd0b85a97d-38213ff978fmr981104f8f.2.1731546984697; Wed, 13 Nov 2024 17:16:24 -0800 (PST) Received: from localhost.localdomain ([176.187.209.238]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-381eda137dbsm19426371f8f.110.2024.11.13.17.16.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 13 Nov 2024 17:16:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 24/24] exec: Move 'ram_addr.h' header under sysemu/ namespace Date: Thu, 14 Nov 2024 02:13:09 +0100 Message-ID: <20241114011310.3615-25-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org "ram_addr.h" contains declarations specific to system emulation, move it under the sysemu/ directory to clarify the API namespace. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 2 +- include/exec/cpu-common.h | 2 +- include/exec/memory.h | 2 +- include/exec/translation-block.h | 2 +- include/sysemu/physmem-target.h | 2 +- include/{exec => sysemu}/ram_addr.h | 0 accel/kvm/kvm-all.c | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 2 +- hw/ppc/spapr.c | 2 +- hw/ppc/spapr_caps.c | 2 +- hw/ppc/spapr_pci.c | 2 +- hw/remote/memory.c | 2 +- hw/remote/proxy-memory-listener.c | 2 +- hw/s390x/s390-stattrib-kvm.c | 2 +- hw/s390x/s390-stattrib.c | 2 +- hw/s390x/s390-virtio-ccw.c | 2 +- hw/vfio/common.c | 2 +- hw/vfio/container.c | 2 +- hw/vfio/iommufd.c | 2 +- hw/vfio/migration.c | 2 +- hw/vfio/spapr.c | 2 +- hw/virtio/virtio-mem.c | 2 +- migration/ram.c | 2 +- plugins/api.c | 2 +- system/memory.c | 2 +- system/physmem.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/ppc/kvm.c | 2 +- target/s390x/kvm/kvm.c | 2 +- 30 files changed, 29 insertions(+), 29 deletions(-) rename include/{exec => sysemu}/ram_addr.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 0027e56fa5..f303f73534 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3024,10 +3024,10 @@ S: Supported F: include/exec/ioport.h F: include/exec/memop.h F: include/exec/memory.h -F: include/exec/ram_addr.h F: include/exec/ramblock.h F: include/sysemu/memory_mapping.h F: include/sysemu/physmem-target.h +F: include/sysemu/ram_addr.h F: system/dma-helpers.c F: system/ioport.c F: system/memory.c diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index b790202c56..27f047b13b 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -54,7 +54,7 @@ enum device_endian { #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN #endif -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" /** * cpu_address_space_init: diff --git a/include/exec/memory.h b/include/exec/memory.h index 58faa3eb08..b2e2d4590a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -28,7 +28,7 @@ #include "qemu/notify.h" #include "qom/object.h" #include "qemu/rcu.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #define RAM_ADDR_INVALID (~(ram_addr_t)0) diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index 9c4757882c..b72fcbbb18 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -8,7 +8,7 @@ #define EXEC_TRANSLATION_BLOCK_H #include "qemu/thread.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" diff --git a/include/sysemu/physmem-target.h b/include/sysemu/physmem-target.h index b30c42da60..32efaf80b6 100644 --- a/include/sysemu/physmem-target.h +++ b/include/sysemu/physmem-target.h @@ -23,7 +23,7 @@ #include "sysemu/xen.h" #include "sysemu/tcg.h" #include "exec/cputlb.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "qemu/rcu.h" diff --git a/include/exec/ram_addr.h b/include/sysemu/ram_addr.h similarity index 100% rename from include/exec/ram_addr.h rename to include/sysemu/ram_addr.h diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index a80547006b..1ec73400a7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -34,7 +34,7 @@ #include "sysemu/accel-blocker.h" #include "qemu/bswap.h" #include "exec/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d4b381641c..46f35ddd59 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/mmu-access-type.h" #include "exec/tlb-common.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 48015be829..6d165fded6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -40,7 +40,7 @@ #endif #endif #else -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #endif diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a9833530c7..ac9ab5986a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -74,7 +74,7 @@ #include "hw/virtio/virtio-scsi.h" #include "hw/virtio/vhost-scsi-common.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/usb.h" diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 5eef7475c1..1d9ad3d6fc 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -27,7 +27,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "sysemu/hw_accel.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "target/ppc/cpu.h" #include "target/ppc/mmu-hash64.h" diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index a91fea1304..f6b2cb7396 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -34,7 +34,7 @@ #include "hw/pci/pci_host.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include #include "trace.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 0af2a2f3fe..23df49099a 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include "hw/remote/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qapi/error.h" diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c index 3948751ed7..0baf145016 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -12,7 +12,7 @@ #include "qemu/range.h" #include "exec/memory.h" #include "exec/cpu-common.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index b495d81296..48fd8e56cc 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -15,7 +15,7 @@ #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "kvm/kvm_s390x.h" #include "qapi/error.h" diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index fe7945e856..5bad70ae5c 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -16,7 +16,7 @@ #include "hw/qdev-properties.h" #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qapi/qmp/qdict.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 5b6fe1a18a..823a45cdec 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -13,7 +13,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/boards.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 2e7a02cd4b..01aae36194 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -29,7 +29,7 @@ #include "hw/vfio/pci.h" #include "exec/address-spaces.h" #include "exec/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "hw/hw.h" #include "qemu/error-report.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index f0bc9e8c2b..fe2254962b 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -25,7 +25,7 @@ #include "hw/vfio/vfio-common.h" #include "exec/address-spaces.h" #include "exec/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qemu/range.h" diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 120c82f3de..0b539cd55a 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -25,7 +25,7 @@ #include "qemu/cutils.h" #include "qemu/chardev_open.h" #include "pci.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" static int iommufd_cdev_map(const VFIOContainerBase *bcontainer, hwaddr iova, diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index f5698eeae0..a057034e2a 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -26,7 +26,7 @@ #include "qapi/error.h" #include "qapi/qapi-events-vfio.h" #include "exec/ramlist.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "pci.h" #include "trace.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 980147338a..7b4159948f 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -19,7 +19,7 @@ #include "hw/vfio/vfio-common.h" #include "hw/hw.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qapi/error.h" diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index dae94dbbde..1cccec24c3 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -24,7 +24,7 @@ #include "hw/virtio/virtio-mem.h" #include "qapi/error.h" #include "qapi/visitor.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "migration/misc.h" #include "hw/boards.h" diff --git a/migration/ram.c b/migration/ram.c index 82c44e8213..5da14601c1 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -48,7 +48,7 @@ #include "qapi/qapi-commands-migration.h" #include "qapi/qmp/qerror.h" #include "trace.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/target_page.h" #include "qemu/rcu_queue.h" diff --git a/plugins/api.c b/plugins/api.c index 77b55cff74..24bf31804f 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -49,7 +49,7 @@ #ifndef CONFIG_USER_ONLY #include "qapi/error.h" #include "migration/blocker.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/plugin-memory.h" #include "hw/boards.h" diff --git a/system/memory.c b/system/memory.c index 7eae1bbda7..281f3c94e1 100644 --- a/system/memory.c +++ b/system/memory.c @@ -26,7 +26,7 @@ #include "trace.h" #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" diff --git a/system/physmem.c b/system/physmem.c index 26cfb84454..d856c77d8b 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -66,7 +66,7 @@ #include "sysemu/replay.h" #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/pmem.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 0950a1c6f1..c401a0981c 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -24,7 +24,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #ifndef CONFIG_USER_ONLY -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #endif #include "exec/cpu_ldst.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index f764931426..f9dc722f3f 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -41,7 +41,7 @@ #include "trace.h" #include "gdbstub/enums.h" #include "exec/memattrs.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "sysemu/hostmem.h" #include "qemu/cutils.h" diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index c8045d873c..7dd4e403aa 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -41,7 +41,7 @@ #include "sysemu/runstate.h" #include "sysemu/device_tree.h" #include "gdbstub/enums.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "trace.h" #include "hw/s390x/s390-pci-inst.h"