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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da2800absm28573255e9.25.2024.11.14.08.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:47 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 01/15] irqchip/riscv-imsic: Use hierarchy to reach irq_set_affinity Date: Thu, 14 Nov 2024 17:18:46 +0100 Message-ID: <20241114161845.502027-18-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081850_387854_F19EE333 X-CRM114-Status: GOOD ( 11.84 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org In order to support IRQ domains which reside between the leaf domains and IMSIC, put the IMSIC implementation of irq_set_affinity into its chip. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index c708780e8760..5d7c30ad8855 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -96,9 +96,8 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask bool force) { struct imsic_vector *old_vec, *new_vec; - struct irq_data *pd = d->parent_data; - old_vec = irq_data_get_irq_chip_data(pd); + old_vec = irq_data_get_irq_chip_data(d); if (WARN_ON(!old_vec)) return -ENOENT; @@ -116,13 +115,13 @@ static int imsic_irq_set_affinity(struct irq_data *d, const struct cpumask *mask return -ENOSPC; /* Point device to the new vector */ - imsic_msi_update_msg(d, new_vec); + imsic_msi_update_msg(irq_get_irq_data(d->irq), new_vec); /* Update irq descriptors with the new vector */ - pd->chip_data = new_vec; + d->chip_data = new_vec; - /* Update effective affinity of parent irq data */ - irq_data_update_effective_affinity(pd, cpumask_of(new_vec->cpu)); + /* Update effective affinity */ + irq_data_update_effective_affinity(d, cpumask_of(new_vec->cpu)); /* Move state of the old vector to the new vector */ imsic_vector_move(old_vec, new_vec); @@ -135,6 +134,9 @@ static struct irq_chip imsic_irq_base_chip = { .name = "IMSIC", .irq_mask = imsic_irq_mask, .irq_unmask = imsic_irq_unmask, +#ifdef CONFIG_SMP + .irq_set_affinity = imsic_irq_set_affinity, +#endif .irq_retrigger = imsic_irq_retrigger, .irq_compose_msi_msg = imsic_irq_compose_msg, .flags = IRQCHIP_SKIP_SET_WAKE | @@ -245,7 +247,7 @@ static bool imsic_init_dev_msi_info(struct device *dev, if (WARN_ON_ONCE(domain != real_parent)) return false; #ifdef CONFIG_SMP - info->chip->irq_set_affinity = imsic_irq_set_affinity; + info->chip->irq_set_affinity = irq_chip_set_affinity_parent; #endif break; default: From patchwork Thu Nov 14 16:18:47 2024 Content-Type: text/plain; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265c45sm28633555e9.11.2024.11.14.08.18.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:49 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 02/15] genirq/msi: Provide DOMAIN_BUS_MSI_REMAP Date: Thu, 14 Nov 2024 17:18:47 +0100 Message-ID: <20241114161845.502027-19-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081851_677087_4A68FB26 X-CRM114-Status: UNSURE ( 8.71 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Provide a domain bus token for the upcoming support for the RISC-V IOMMU interrupt remapping domain, which needs to be distinguished from NEXUS domains. The new token name is generic, as the only information that needs to be conveyed is that the IRQ domain will remap MSIs, i.e. there's nothing RISC-V specific to convey. Signed-off-by: Andrew Jones --- include/linux/irqdomain_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h index 36653e2ee1c9..676eca8147ae 100644 --- a/include/linux/irqdomain_defs.h +++ b/include/linux/irqdomain_defs.h @@ -27,6 +27,7 @@ enum irq_domain_bus_token { DOMAIN_BUS_AMDVI, DOMAIN_BUS_DEVICE_MSI, DOMAIN_BUS_WIRED_TO_MSI, + DOMAIN_BUS_MSI_REMAP, }; #endif /* _LINUX_IRQDOMAIN_DEFS_H */ From patchwork Thu Nov 14 16:18:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 86776D68B36 for ; Thu, 14 Nov 2024 16:19:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KvBGJR5fycL12D2M320EM1Ty5TEAv7N9T8v0ArpL6nM=; b=P5+j1QS3EpgA/Y yOU3e7xmYbK2Xf7Hx8H/pzCkxKBfw7GqJg3axpGH8F/oUuBPp7kFdw5yZEOEjpSjzwD62aPKdyUUW I43bEcFNs/ptoGTPT002o7U4ew2L72PHiZawdN15OD3v+Y07iWRdw0WcVXzUW2QA4hndL2wu+R4aF shpU0NlEicUUFVAMlLQc1gpRKtRzQYfvOqFykBHrZgO0uHNRFZ2HnlLXdpEuPPXgHIdY4MZ9SlieG 79IP9KkiG8BUetwbplxx/BrEr/59tq5sZphoC4nMOY9HzirZfpbuKUOZteA68GJ+uWuerP6d5X5nm XvqXG75hq/hycjPUdZ6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYa-000000004tb-0eSX; Thu, 14 Nov 2024 16:18:56 +0000 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYX-000000004pK-1eO9 for linux-riscv@lists.infradead.org; Thu, 14 Nov 2024 16:18:54 +0000 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-539e8607c2aso849834e87.3 for ; Thu, 14 Nov 2024 08:18:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601131; x=1732205931; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EgkdpOYsLIOn0iKAKl5fgt6eXL8Mzl+XIucJ8fWc9TA=; b=HMk4PUosQnNRSmgX82JVY7cDKQtXa0/z4ZNqrK/iYyLV7q3xp44EkzDh5DgUpe7cL0 r7fr4yCTFZUXJXHN8ZhMuvWCvwgWLlpUlt5EfACyBaBZDd2L2NrC+xBcIRT21uA3sMjb qutlGpfeMA4HeVbrNfXzRzXGFQjBm/p1pzfarq+UsdpC1+L1sg0ZVF44hn7dd9qBoi7/ Seh9v3pOW5K7/ZfbCfCiP/M7eeMSr4MMsGzuh60Qcl4+xQqoX2xDrAa3FFFoUjzYi5lQ LbUBvtjDFWbrum2qGz/n5cMroo6lgoV0ZUMJip2FNl4pUD7phutmjQSOvt2gWvnJsrry B6uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601131; x=1732205931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EgkdpOYsLIOn0iKAKl5fgt6eXL8Mzl+XIucJ8fWc9TA=; b=PPXpfKEqdRZB62Rhgi64L3/msXMKmpBq4n5/SvaOst5NhNQ4ic6WbZcKPgGimiBGKb ggGQ3gWdAYw7B3UGAgW7+Ie+ecvVgMGyASub5UXr0uQ+JAck+GRsLTTgOXpjUkDWdA+L n0BEbU7AmQ1LsJEfnpXhPl7GcMTxaDy4E3+Lj6dRaLNK2C3unHN/e6ySkyQpcZpUiud3 G+ojX+idwhQddOTKujxL+3vB1fBWlaUu4Jr5W9KonwhutFz9GXWvtuPpPbKyUr9t68xF VEuYtBt2TDnbVS3iWJH/XmkDcs3bP5gazJNtSFsv4nFI/Vl7oP2y99yc3bvN6u5Nf+e5 krWA== X-Forwarded-Encrypted: i=1; AJvYcCXL378QoDrG+C2cN8seQHHuv5lcRKN1g6SC2q5P47Wl9LdvOO2/GfADjmA1U5g7Qt8sqqySmeDhvr8HyA==@lists.infradead.org X-Gm-Message-State: AOJu0Yz9eKhy1zNaluePJMEoufXzBIgsrkp4Ma5VncRyPLDY9Lm7XfU5 fzuhoavhyzsny10EmzJuu3hu7ZmAYY9mdXiB5GhKaphGGmKuJNJIotepkxkpo9Q= X-Google-Smtp-Source: AGHT+IFd0CnkIMN5l0Pz4D+G0QBgRZi3KYTDXcb5xA9gQJqvW8wTertCqu9+xj4IWnW1G55hIkNGVw== X-Received: by 2002:a05:6512:3ca5:b0:539:f607:1d2b with SMTP id 2adb3069b0e04-53d862b45e5mr14144215e87.7.1731601131046; Thu, 14 Nov 2024 08:18:51 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac1f409sm24906005e9.37.2024.11.14.08.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:50 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 03/15] irqchip/riscv-imsic: Add support for DOMAIN_BUS_MSI_REMAP Date: Thu, 14 Nov 2024 17:18:48 +0100 Message-ID: <20241114161845.502027-20-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081853_446600_416F332B X-CRM114-Status: UNSURE ( 9.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Unlike a child of an MSI NEXUS domain, a child of an MSI_REMAP domain will not invoke init_dev_msi_info() with 'domain' equal to 'msi_parent_domain'. This is because the MSI_REMAP domain implements init_dev_msi_info() with msi_parent_init_dev_msi_info(), which makes 'domain' point to the NEXUS (IMSIC) domain, while keeping 'msi_parent_domain' pointing to itself. The rest of the IMSIC init_dev_msi_info() implementation works for MSI_REMAP domains, though, so there's nothing to do to add support except accept the token. Signed-off-by: Andrew Jones --- drivers/irqchip/irq-riscv-imsic-platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 5d7c30ad8855..6a7d7fefda6a 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -246,6 +246,8 @@ static bool imsic_init_dev_msi_info(struct device *dev, case DOMAIN_BUS_NEXUS: if (WARN_ON_ONCE(domain != real_parent)) return false; + fallthrough; + case DOMAIN_BUS_MSI_REMAP: #ifdef CONFIG_SMP info->chip->irq_set_affinity = irq_chip_set_affinity_parent; #endif From patchwork Thu Nov 14 16:18:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA186D68B38 for ; Thu, 14 Nov 2024 16:19:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fucf/NTbivx0SWtbw94Cd1yOgHbEJ3fJZcSh4i6WRqw=; b=VPMCAYIe5m4HOG vny7MqueVB9hzf1MoihLZbBfL1ymTUgUvQONq7v7c97o77SL3Pp+ccAN8T7UkRE6j8upoqw4p7H5P fRY0RMl7TFyQ6eRBl1blClGCwYxkgOr+5FXjDkbuHg9nyDVMlTbPxuTHBIasWVlFCYKOUNeVR+ryT GMMXKwT61bicPrmVQtY+a36GBW0CtLkDFK0Rgz0VCvyFgu7GjQk2D/NGvGhRpWKTwOJ0v4G3IAli1 GfKdHefrHmwov0OgdB+a1kbz4JSVvaBBFpVbXTUy4xnPJAEd4ljGp3OBiezcHWBdZ0Ba1EaNu+xal bK9Mp6axn04sHjNFiRtA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYa-000000004vE-3pOm; Thu, 14 Nov 2024 16:18:56 +0000 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYX-000000004ps-38GF for linux-riscv@lists.infradead.org; Thu, 14 Nov 2024 16:18:55 +0000 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4315f24a6bbso6995005e9.1 for ; Thu, 14 Nov 2024 08:18:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601132; x=1732205932; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o3RScEb/zQMeNBIY0PtZD1/ZjJQ2IegD9nNkwkqM6gc=; b=o91C/Z/FTD9GqtnFqTP4X1CCuH7Y2G7mEFC1i3WQZocrHAcLTxYh/57Wbj1EtqxPJY Sk3Xt+EGYjznj93101Uehp4beUs/K77SVZal+qNGGqkIVLlEB/zXvx3oXdCwCugBKpk/ ChpSSTc1PLihAtI2p3lFStu2sOJWiGrAO4eHBvioWdtp1Te9RtI3ZNnl+NRHmt00o9nx 71S/LlYb56eFzU+EU75zd5kmvMFS7oFSsxV8MUgPRvru7VRqmcNiJg2m0aJ0N48Qxc1p wAeZqExB2E26Xb6048kOOT5Uo+fiuyiBTHmhhvGvd2aFeBoyeS3iRCn9jaZrTqM/6AJy 9uFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601132; x=1732205932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o3RScEb/zQMeNBIY0PtZD1/ZjJQ2IegD9nNkwkqM6gc=; b=tji8fsKTS9oGyZvURxlYuGQOZV10u6TFfRsUCq1CEyt8SJc9ZRs76y7vUIabKkHdX3 tXhX/DyePT71ivOPf5rJCp1u+QQues7Ppf+kBQk1oduXrEa9ZL7VjLq9gb+uyOCr9JMA BgEGaxsrxlyqlF6beZtGd2/njLhjSczQrfb6py4RaYP3jHnp3iBcAdaTPGFZjdyZneNd mtXeQvVbBgQHfUVBhNse2vHqlqHxGnFYal/bwvHl3z4W4ECKexHUBzB4rEHnVXAJVk+1 qywhebVtlu7In2ERICUdMvFPjIjCLBt+a4i8v0hvBAjmAnbnohXu+fRjjRHP8VvYKoTD iXjA== X-Forwarded-Encrypted: i=1; AJvYcCXeWgCsdxbFcgpe9oQflJp03eERU/D8BWcv5JKaNsTxx1VryB7/AeVlCPLzA41IOpnAEGXApb4BC2HqEQ==@lists.infradead.org X-Gm-Message-State: AOJu0Yy5jJHaW3PCAIMBcJr1Mm42wtuC8bqp4PFrpdvLgm/ZYkjIaG+D 0uEzEmulL49SVBjqTvdcQaWZexj9Av9eNlHjQUNnnsLQjO7RphDTb7AHS1kKOfY= X-Google-Smtp-Source: AGHT+IETarykQuvm6+z3/CASGfAXpcrdoszeWN3rsEIL+bc92gQplNjgpnYXoIwCDFze+tOTvORF1Q== X-Received: by 2002:a05:600c:3c8f:b0:431:4e25:fe42 with SMTP id 5b1f17b1804b1-432b751e28fmr192523985e9.32.1731601132365; Thu, 14 Nov 2024 08:18:52 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab72184sm24967935e9.2.2024.11.14.08.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:51 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 04/15] iommu/riscv: report iommu capabilities Date: Thu, 14 Nov 2024 17:18:49 +0100 Message-ID: <20241114161845.502027-21-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081853_794153_E5051D6A X-CRM114-Status: UNSURE ( 9.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Tomasz Jeznach Report RISC-V IOMMU capabilities required by VFIO subsystem to enable PCIe device assignment. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 8a05def774bd..3fe4ceba8dd3 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1462,6 +1462,17 @@ static struct iommu_group *riscv_iommu_device_group(struct device *dev) return generic_device_group(dev); } +static bool riscv_iommu_capable(struct device *dev, enum iommu_cap cap) +{ + switch (cap) { + case IOMMU_CAP_CACHE_COHERENCY: + case IOMMU_CAP_DEFERRED_FLUSH: + return true; + default: + return false; + } +} + static int riscv_iommu_of_xlate(struct device *dev, const struct of_phandle_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -1526,6 +1537,7 @@ static void riscv_iommu_release_device(struct device *dev) static const struct iommu_ops riscv_iommu_ops = { .pgsize_bitmap = SZ_4K, .of_xlate = riscv_iommu_of_xlate, + .capable = riscv_iommu_capable, .identity_domain = &riscv_iommu_identity_domain, .blocked_domain = &riscv_iommu_blocking_domain, .release_domain = &riscv_iommu_blocking_domain, From patchwork Thu Nov 14 16:18:50 2024 Content-Type: text/plain; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265e16sm28762605e9.12.2024.11.14.08.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:53 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 05/15] iommu/riscv: use data structure instead of individual values Date: Thu, 14 Nov 2024 17:18:50 +0100 Message-ID: <20241114161845.502027-22-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081855_623089_A670CE41 X-CRM114-Status: GOOD ( 13.42 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Zong Li The parameter will be increased when we need to set up more bit fields in the device context. Use a data structure to wrap them up. Signed-off-by: Zong Li Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 3fe4ceba8dd3..9d7945dc3c24 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1001,7 +1001,7 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain, * interim translation faults. */ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, - struct device *dev, u64 fsc, u64 ta) + struct device *dev, struct riscv_iommu_dc *new_dc) { struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct riscv_iommu_dc *dc; @@ -1035,10 +1035,10 @@ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, for (i = 0; i < fwspec->num_ids; i++) { dc = riscv_iommu_get_dc(iommu, fwspec->ids[i]); tc = READ_ONCE(dc->tc); - tc |= ta & RISCV_IOMMU_DC_TC_V; + tc |= new_dc->ta & RISCV_IOMMU_DC_TC_V; - WRITE_ONCE(dc->fsc, fsc); - WRITE_ONCE(dc->ta, ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->fsc, new_dc->fsc); + WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1315,20 +1315,20 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_domain *domain = iommu_domain_to_riscv(iommu_domain); struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); - u64 fsc, ta; + struct riscv_iommu_dc dc = {0}; if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; - fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); - ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | - RISCV_IOMMU_PC_TA_V; + dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + dc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | + RISCV_IOMMU_PC_TA_V; if (riscv_iommu_bond_link(domain, dev)) return -ENOMEM; - riscv_iommu_iodir_update(iommu, dev, fsc, ta); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain = domain; @@ -1419,9 +1419,12 @@ static int riscv_iommu_attach_blocking_domain(struct iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); + struct riscv_iommu_dc dc = {0}; + + dc.fsc = RISCV_IOMMU_FSC_BARE; /* Make device context invalid, translation requests will fault w/ #258 */ - riscv_iommu_iodir_update(iommu, dev, RISCV_IOMMU_FSC_BARE, 0); + riscv_iommu_iodir_update(iommu, dev, &dc); riscv_iommu_bond_unlink(info->domain, dev); info->domain = NULL; @@ -1440,8 +1443,12 @@ static int riscv_iommu_attach_identity_domain(struct iommu_domain *iommu_domain, { struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27fc8esm29713515e9.21.2024.11.14.08.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:54 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 06/15] iommu/riscv: support GSCID and GVMA invalidation command Date: Thu, 14 Nov 2024 17:18:51 +0100 Message-ID: <20241114161845.502027-23-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081857_442191_3E0442EB X-CRM114-Status: GOOD ( 16.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Zong Li This patch adds a ID Allocator for GSCID and a wrap for setting up GSCID in IOTLB invalidation command. Set up iohgatp to enable second stage table and flush stage-2 table if the GSCID is set. The GSCID of domain should be freed when release domain. GSCID will be allocated for parent domain in nested IOMMU process. Signed-off-by: Zong Li Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-bits.h | 7 +++++++ drivers/iommu/riscv/iommu.c | 32 ++++++++++++++++++++++++++------ 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h index 98daf0e1a306..d72b982cf9bf 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -715,6 +715,13 @@ static inline void riscv_iommu_cmd_inval_vma(struct riscv_iommu_command *cmd) cmd->dword1 = 0; } +static inline void riscv_iommu_cmd_inval_gvma(struct riscv_iommu_command *cmd) +{ + cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | + FIELD_PREP(RISCV_IOMMU_CMD_FUNC, RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA); + cmd->dword1 = 0; +} + static inline void riscv_iommu_cmd_inval_set_addr(struct riscv_iommu_command *cmd, u64 addr) { diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 9d7945dc3c24..ef38a1bb3eca 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -45,6 +45,10 @@ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) +/* IOMMU GSCID allocation namespace. */ +static DEFINE_IDA(riscv_iommu_gscids); +#define RISCV_IOMMU_MAX_GSCID (BIT(16) - 1) + /* Device resource-managed allocations */ struct riscv_iommu_devres { void *addr; @@ -801,6 +805,7 @@ struct riscv_iommu_domain { struct list_head bonds; spinlock_t lock; /* protect bonds list updates. */ int pscid; + int gscid; bool amo_enabled; int numa_node; unsigned int pgd_mode; @@ -954,15 +959,20 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain, /* * IOTLB invalidation request can be safely omitted if already sent - * to the IOMMU for the same PSCID, and with domain->bonds list + * to the IOMMU for the same PSCID/GSCID, and with domain->bonds list * arranged based on the device's IOMMU, it's sufficient to check * last device the invalidation was sent to. */ if (iommu == prev) continue; - riscv_iommu_cmd_inval_vma(&cmd); - riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + if (domain->gscid) { + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_gscid(&cmd, domain->gscid); + } else { + riscv_iommu_cmd_inval_vma(&cmd); + riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid); + } if (len && len < RISCV_IOMMU_IOTLB_INVAL_LIMIT) { for (iova = start; iova < end; iova += PAGE_SIZE) { riscv_iommu_cmd_inval_set_addr(&cmd, iova); @@ -1039,6 +1049,7 @@ static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu, WRITE_ONCE(dc->fsc, new_dc->fsc); WRITE_ONCE(dc->ta, new_dc->ta & RISCV_IOMMU_PC_TA_PSCID); + WRITE_ONCE(dc->iohgatp, new_dc->iohgatp); /* Update device context, write TC.V as the last step. */ dma_wmb(); WRITE_ONCE(dc->tc, tc); @@ -1287,8 +1298,10 @@ static void riscv_iommu_free_paging_domain(struct iommu_domain *iommu_domain) WARN_ON(!list_empty(&domain->bonds)); - if ((int)domain->pscid > 0) + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); + if (domain->gscid > 0) + ida_free(&riscv_iommu_gscids, domain->gscid); riscv_iommu_pte_free(domain, _io_pte_entry(pfn, _PAGE_TABLE), NULL); kfree(domain); @@ -1320,8 +1333,15 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; - dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | - FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + if (domain->gscid) { + dc.iohgatp = FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, domain->pgd_mode) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | + FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, virt_to_pfn(domain->pgd_root)); + } else { + dc.fsc = FIELD_PREP(RISCV_IOMMU_PC_FSC_MODE, domain->pgd_mode) | + FIELD_PREP(RISCV_IOMMU_PC_FSC_PPN, virt_to_pfn(domain->pgd_root)); + } + dc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; From patchwork Thu Nov 14 16:18:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24455D68B34 for ; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac1f94asm25135835e9.39.2024.11.14.08.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:18:59 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 07/15] iommu/riscv: Move definitions to iommu.h Date: Thu, 14 Nov 2024 17:18:52 +0100 Message-ID: <20241114161845.502027-24-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081901_087230_98AFB6F2 X-CRM114-Status: GOOD ( 22.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org In order to add the interrupt remapping support in a separate file, share definitions through the header, as well as making some functions public. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-bits.h | 4 ++ drivers/iommu/riscv/iommu.c | 71 ++++---------------------------- drivers/iommu/riscv/iommu.h | 54 ++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 62 deletions(-) diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h index d72b982cf9bf..d3d98dbed709 100644 --- a/drivers/iommu/riscv/iommu-bits.h +++ b/drivers/iommu/riscv/iommu-bits.h @@ -36,6 +36,10 @@ #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) +/* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */ +#define riscv_iommu_phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << 10)) +#define riscv_iommu_ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << 12)) + /* 5.3 IOMMU Capabilities (64bits) */ #define RISCV_IOMMU_REG_CAPABILITIES 0x0000 #define RISCV_IOMMU_CAPABILITIES_VERSION GENMASK_ULL(7, 0) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index ef38a1bb3eca..6e8ea3d22ff5 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -24,23 +24,10 @@ #include "iommu-bits.h" #include "iommu.h" -/* Timeouts in [us] */ -#define RISCV_IOMMU_QCSR_TIMEOUT 150000 -#define RISCV_IOMMU_QUEUE_TIMEOUT 150000 -#define RISCV_IOMMU_DDTP_TIMEOUT 10000000 -#define RISCV_IOMMU_IOTINVAL_TIMEOUT 90000000 - /* Number of entries per CMD/FLT queue, should be <= INT_MAX */ #define RISCV_IOMMU_DEF_CQ_COUNT 8192 #define RISCV_IOMMU_DEF_FQ_COUNT 4096 -/* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */ -#define phys_to_ppn(pa) (((pa) >> 2) & (((1ULL << 44) - 1) << 10)) -#define ppn_to_phys(pn) (((pn) << 2) & (((1ULL << 44) - 1) << 12)) - -#define dev_to_iommu(dev) \ - iommu_get_iommu_dev(dev, struct riscv_iommu_device, iommu) - /* IOMMU PSCID allocation namespace. */ static DEFINE_IDA(riscv_iommu_pscids); #define RISCV_IOMMU_MAX_PSCID (BIT(20) - 1) @@ -177,7 +164,7 @@ static int riscv_iommu_queue_alloc(struct riscv_iommu_device *iommu, if (!queue->base) return -ENOMEM; - qb = phys_to_ppn(queue->phys) | + qb = riscv_iommu_phys_to_ppn(queue->phys) | FIELD_PREP(RISCV_IOMMU_QUEUE_LOG2SZ_FIELD, logsz); /* Update base register and read back to verify hw accepted our write */ @@ -480,15 +467,15 @@ static irqreturn_t riscv_iommu_cmdq_process(int irq, void *data) } /* Send command to the IOMMU command queue */ -static void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, - struct riscv_iommu_command *cmd) +void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, + struct riscv_iommu_command *cmd) { riscv_iommu_queue_send(&iommu->cmdq, cmd, sizeof(*cmd)); } /* Send IOFENCE.C command and wait for all scheduled commands to complete. */ -static void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, - unsigned int timeout_us) +void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, + unsigned int timeout_us) { struct riscv_iommu_command cmd; unsigned int prod; @@ -614,7 +601,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iomm do { ddt = READ_ONCE(*(unsigned long *)ddtp); if (ddt & RISCV_IOMMU_DDTE_V) { - ddtp = __va(ppn_to_phys(ddt)); + ddtp = __va(riscv_iommu_ppn_to_phys(ddt)); break; } @@ -622,7 +609,7 @@ static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iomm if (!ptr) return NULL; - new = phys_to_ppn(__pa(ptr)) | RISCV_IOMMU_DDTE_V; + new = riscv_iommu_phys_to_ppn(__pa(ptr)) | RISCV_IOMMU_DDTE_V; old = cmpxchg_relaxed((unsigned long *)ddtp, ddt, new); if (old == ddt) { @@ -687,7 +674,7 @@ static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu) if (ddtp & RISCV_IOMMU_DDTP_BUSY) return -EBUSY; - iommu->ddt_phys = ppn_to_phys(ddtp); + iommu->ddt_phys = riscv_iommu_ppn_to_phys(ddtp); if (iommu->ddt_phys) iommu->ddt_root = devm_ioremap(iommu->dev, iommu->ddt_phys, PAGE_SIZE); @@ -734,7 +721,7 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iommu_device *iommu, do { rq_ddtp = FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE, rq_mode); if (rq_mode > RISCV_IOMMU_DDTP_IOMMU_MODE_BARE) - rq_ddtp |= phys_to_ppn(iommu->ddt_phys); + rq_ddtp |= riscv_iommu_phys_to_ppn(iommu->ddt_phys); riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_DDTP, rq_ddtp); ddtp = riscv_iommu_read_ddtp(iommu); @@ -799,49 +786,9 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iommu_device *iommu, return 0; } -/* This struct contains protection domain specific IOMMU driver data. */ -struct riscv_iommu_domain { - struct iommu_domain domain; - struct list_head bonds; - spinlock_t lock; /* protect bonds list updates. */ - int pscid; - int gscid; - bool amo_enabled; - int numa_node; - unsigned int pgd_mode; - unsigned long *pgd_root; -}; - #define iommu_domain_to_riscv(iommu_domain) \ container_of(iommu_domain, struct riscv_iommu_domain, domain) -/* Private IOMMU data for managed devices, dev_iommu_priv_* */ -struct riscv_iommu_info { - struct riscv_iommu_domain *domain; -}; - -/* - * Linkage between an iommu_domain and attached devices. - * - * Protection domain requiring IOATC and DevATC translation cache invalidations, - * should be linked to attached devices using a riscv_iommu_bond structure. - * Devices should be linked to the domain before first use and unlinked after - * the translations from the referenced protection domain can no longer be used. - * Blocking and identity domains are not tracked here, as the IOMMU hardware - * does not cache negative and/or identity (BARE mode) translations, and DevATC - * is disabled for those protection domains. - * - * The device pointer and IOMMU data remain stable in the bond struct after - * _probe_device() where it's attached to the managed IOMMU, up to the - * completion of the _release_device() call. The release of the bond structure - * is synchronized with the device release. - */ -struct riscv_iommu_bond { - struct list_head list; - struct rcu_head rcu; - struct device *dev; -}; - static int riscv_iommu_bond_link(struct riscv_iommu_domain *domain, struct device *dev) { diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index b1c4664542b4..dd538b19fbb7 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -17,8 +17,35 @@ #include "iommu-bits.h" +/* Timeouts in [us] */ +#define RISCV_IOMMU_QCSR_TIMEOUT 150000 +#define RISCV_IOMMU_QUEUE_TIMEOUT 150000 +#define RISCV_IOMMU_DDTP_TIMEOUT 10000000 +#define RISCV_IOMMU_IOTINVAL_TIMEOUT 90000000 + +/* This struct contains protection domain specific IOMMU driver data. */ +struct riscv_iommu_domain { + struct iommu_domain domain; + struct list_head bonds; + spinlock_t lock; /* protect bonds list updates. */ + int pscid; + int gscid; + int amo_enabled; + int numa_node; + unsigned int pgd_mode; + unsigned long *pgd_root; +}; + +/* Private IOMMU data for managed devices, dev_iommu_priv_* */ +struct riscv_iommu_info { + struct riscv_iommu_domain *domain; +}; + struct riscv_iommu_device; +#define dev_to_iommu(dev) \ + iommu_get_iommu_dev(dev, struct riscv_iommu_device, iommu) + struct riscv_iommu_queue { atomic_t prod; /* unbounded producer allocation index */ atomic_t head; /* unbounded shadow ring buffer consumer index */ @@ -62,9 +89,36 @@ struct riscv_iommu_device { u64 *ddt_root; }; +/* + * Linkage between an iommu_domain and attached devices. + * + * Protection domain requiring IOATC and DevATC translation cache invalidations, + * should be linked to attached devices using a riscv_iommu_bond structure. + * Devices should be linked to the domain before first use and unlinked after + * the translations from the referenced protection domain can no longer be used. + * Blocking and identity domains are not tracked here, as the IOMMU hardware + * does not cache negative and/or identity (BARE mode) translations, and DevATC + * is disabled for those protection domains. + * + * The device pointer and IOMMU data remain stable in the bond struct after + * _probe_device() where it's attached to the managed IOMMU, up to the + * completion of the _release_device() call. The release of the bond structure + * is synchronized with the device release. + */ +struct riscv_iommu_bond { + struct list_head list; + struct rcu_head rcu; + struct device *dev; +}; + int riscv_iommu_init(struct riscv_iommu_device *iommu); void riscv_iommu_remove(struct riscv_iommu_device *iommu); +void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, + struct riscv_iommu_command *cmd); +void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, + unsigned int timeout_us); + #define riscv_iommu_readl(iommu, addr) \ readl_relaxed((iommu)->reg + (addr)) From patchwork Thu Nov 14 16:18:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AA98D68B33 for ; Thu, 14 Nov 2024 16:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R8w8C/5kZu+MQKmr1wkJCdJsARZupKXAAVwQyaHTnSU=; b=GF+vexX3DgSAs1 zxTl560uqfiV0FaPgp6aMgjQ7SjdX31AN3edohLdI0YXLKG+zzA5Xn6G5ryg6NWr15qScBiXd8D+l /k5+5EZY73FT/B/aw8uZ6UQOIJXK47nenUa3OnEmCavl5ISM9Waj/PuNFGvBIxqHvAgayuPPTTbQI i2+/ePE9ziEHHgLfllz1XG3WsigaN1GrWJZd7HwRqQkC2Xf2Dfw6/ro3c1g72daFW0Kz82nDQK5ij 5s5wf+LgShDzAmee4w13qwnuH3ZOE6T2nPDyp3B8RBeGDsLc6nGdhffHUrecwcGJVwt6soZpDebZB 5UpaXXYjlZesuFqxyuDw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYk-000000005Av-2dXH; Thu, 14 Nov 2024 16:19:06 +0000 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYh-0000000053E-0btn for linux-riscv@lists.infradead.org; Thu, 14 Nov 2024 16:19:04 +0000 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-43167ff0f91so7196075e9.1 for ; Thu, 14 Nov 2024 08:19:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601141; x=1732205941; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VmyPhlw9y/X/fnXH6ufVz2Fv/AglekMjgv19lGdZt0M=; b=KE9OFUWFQzFUjPcc5kcmYg3GlM4Z8AzuyhvUcRrC7YGGs5VnHyyTKoyUZ8Ghu7Dw0y ZNv2rQZW+ifQvtdONtP7BbwB5cJtQzoMqJ8fJGeYnckJ8RlK8JweMoA5cu2rsrUyteg+ yIA8y4b0mds5dYzq56xKjE8Ifkh0J4BbFwoDkofM4BFX13I6E/2MsbHbvipXwNnOwnq9 dctUhXFXel4CR6V6GhN9y5/tgAlu6pW3Sp0ZM30lHxQLsI/HnARApsYBCFxKVSFOXPMQ va67Cy6QoICCn4uTqv7qlnTFptv2n1FlETe2L8lEkO3JX1A91NSTi3iQRzdk7djxC/tl eKug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601141; x=1732205941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VmyPhlw9y/X/fnXH6ufVz2Fv/AglekMjgv19lGdZt0M=; b=Fi8jCbEfn+5mYOamNw1reGurK20Ze7gihj/iCZmyEJLZIMOaf5yFebtq/EzMX26jfD XkQnUbeJsxxNqu1yVQtJHTz+OBqzrFGwcaq2H+6MZG0p0YUib6hHID8dTYgRmao4SlRE eNFQ57y7gWYrXKxYuR2yxT5A519D0oWrV50AA2joGfNmMiNPyA372++YSSHr44dptBxw 2liiWbRmY3n0yNzO/K84DigEsHZi9QCeMW+7M2zPOBtSiz+vq5zGi7XUILC1NndfZXyL +eZVWYBgikPb5f4QBl6ckhg9oKEkZqhQrrhnN7oX4wjqkw81thSS05DQC8hGlsGisVBq Xjbw== X-Forwarded-Encrypted: i=1; AJvYcCX/XSRVY4YNAXTiKIv/y2lHklWDAYiliZCqFTB4ivtDAAINbijSmzBT0zYPpqIFi1MisRetxkQ1qgdUOA==@lists.infradead.org X-Gm-Message-State: AOJu0YyT6gDGC5xcHDzdU3dp/t90lzAGBNIk+ysv16MJCfXyTGoiuLm8 Zw/Q3tLbPRY6L+451+y0jCB4ttpKHXHUgrBkHh+hUaGi8n0yMS19Ob/epQ0pq64= X-Google-Smtp-Source: AGHT+IEurYWNfkgEG6OVCqRhsfT6EytEjQqOu8Vk3V55flsbBNhf08vSjr2U+chyzyCkXFZDditk7A== X-Received: by 2002:a05:6000:2aa:b0:37d:4ef1:1820 with SMTP id ffacd0b85a97d-3820df88797mr5457081f8f.40.1731601141065; Thu, 14 Nov 2024 08:19:01 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada2da2sm1862201f8f.15.2024.11.14.08.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:00 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 08/15] iommu/riscv: Add IRQ domain for interrupt remapping Date: Thu, 14 Nov 2024 17:18:53 +0100 Message-ID: <20241114161845.502027-25-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081903_235076_0DA689F6 X-CRM114-Status: GOOD ( 28.37 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This is just a skeleton. Until irq_set_vcpu_affinity() is implemented the IRQ domain doesn't serve any purpose. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/Makefile | 2 +- drivers/iommu/riscv/iommu-ir.c | 209 +++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 43 ++++++- drivers/iommu/riscv/iommu.h | 21 ++++ 4 files changed, 270 insertions(+), 5 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-ir.c diff --git a/drivers/iommu/riscv/Makefile b/drivers/iommu/riscv/Makefile index f54c9ed17d41..8420dd1776cb 100644 --- a/drivers/iommu/riscv/Makefile +++ b/drivers/iommu/riscv/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_RISCV_IOMMU) += iommu.o iommu-platform.o +obj-$(CONFIG_RISCV_IOMMU) += iommu.o iommu-ir.o iommu-platform.o obj-$(CONFIG_RISCV_IOMMU_PCI) += iommu-pci.o diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c new file mode 100644 index 000000000000..c177e064b205 --- /dev/null +++ b/drivers/iommu/riscv/iommu-ir.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * IOMMU Interrupt Remapping + * + * Copyright © 2024 Ventana Micro Systems Inc. + */ +#include +#include + +#include "../iommu-pages.h" +#include "iommu.h" + +static size_t riscv_iommu_ir_get_msipte_idx(struct riscv_iommu_domain *domain, + phys_addr_t msi_pa) +{ + phys_addr_t addr = msi_pa >> 12; + size_t idx; + + if (domain->group_index_bits) { + phys_addr_t group_mask = BIT(domain->group_index_bits) - 1; + phys_addr_t group_shift = domain->group_index_shift - 12; + phys_addr_t group = (addr >> group_shift) & group_mask; + phys_addr_t mask = domain->msiptp.msi_addr_mask & ~(group_mask << group_shift); + + idx = addr & mask; + idx |= group << fls64(mask); + } else { + idx = addr & domain->msiptp.msi_addr_mask; + } + + return idx; +} + +static struct riscv_iommu_msipte *riscv_iommu_ir_get_msipte(struct riscv_iommu_domain *domain, + phys_addr_t msi_pa) +{ + size_t idx; + + if (((msi_pa >> 12) & ~domain->msiptp.msi_addr_mask) != domain->msiptp.msi_addr_pattern) + return NULL; + + idx = riscv_iommu_ir_get_msipte_idx(domain, msi_pa); + return &domain->msi_root[idx]; +} + +static size_t riscv_iommu_ir_nr_msiptes(struct riscv_iommu_domain *domain) +{ + phys_addr_t base = domain->msiptp.msi_addr_pattern << 12; + phys_addr_t max_addr = base | (domain->msiptp.msi_addr_mask << 12); + size_t max_idx = riscv_iommu_ir_get_msipte_idx(domain, max_addr); + + return max_idx + 1; +} + +static struct irq_chip riscv_iommu_irq_chip = { + .name = "IOMMU-IR", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, +}; + +static int riscv_iommu_irq_domain_alloc_irqs(struct irq_domain *irqdomain, + unsigned int irq_base, unsigned int nr_irqs, + void *arg) +{ + struct irq_data *data; + int i, ret; + + ret = irq_domain_alloc_irqs_parent(irqdomain, irq_base, nr_irqs, arg); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + data = irq_domain_get_irq_data(irqdomain, irq_base + i); + data->chip = &riscv_iommu_irq_chip; + } + + return 0; +} + +static const struct irq_domain_ops riscv_iommu_irq_domain_ops = { + .alloc = riscv_iommu_irq_domain_alloc_irqs, + .free = irq_domain_free_irqs_parent, +}; + +static const struct msi_parent_ops riscv_iommu_msi_parent_ops = { + .prefix = "IR-", + .supported_flags = MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX, + .required_flags = MSI_FLAG_USE_DEF_DOM_OPS | + MSI_FLAG_USE_DEF_CHIP_OPS, + .init_dev_msi_info = msi_parent_init_dev_msi_info, +}; + +int riscv_iommu_irq_domain_create(struct riscv_iommu_domain *domain, + struct device *dev) +{ + struct riscv_iommu_device *iommu = dev_to_iommu(dev); + struct fwnode_handle *fn; + char *fwname; + + if (domain->irqdomain) { + dev_set_msi_domain(dev, domain->irqdomain); + return 0; + } + + if (!(iommu->caps & RISCV_IOMMU_CAPABILITIES_MSI_FLAT)) { + dev_warn(iommu->dev, "Cannot enable interrupt remapping\n"); + return 0; + } + + spin_lock_init(&domain->msi_lock); + /* + * TODO: The hypervisor should be in control of this size. For now + * we just allocate enough space for 512 VCPUs. + */ + domain->msi_order = 1; + domain->msi_root = iommu_alloc_pages_node(domain->numa_node, + GFP_KERNEL_ACCOUNT, domain->msi_order); + if (!domain->msi_root) + return -ENOMEM; + + fwname = kasprintf(GFP_KERNEL, "IOMMU-IR-%s", dev_name(dev)); + if (!fwname) { + iommu_free_pages(domain->msi_root, domain->msi_order); + return -ENOMEM; + } + + fn = irq_domain_alloc_named_fwnode(fwname); + kfree(fwname); + if (!fn) { + dev_err(iommu->dev, "Couldn't allocate fwnode\n"); + iommu_free_pages(domain->msi_root, domain->msi_order); + return -ENOMEM; + } + + domain->irqdomain = irq_domain_create_hierarchy(dev_get_msi_domain(dev), + 0, 0, fn, + &riscv_iommu_irq_domain_ops, + domain); + if (!domain->irqdomain) { + dev_err(iommu->dev, "Failed to create IOMMU irq domain\n"); + iommu_free_pages(domain->msi_root, domain->msi_order); + irq_domain_free_fwnode(fn); + return -ENOMEM; + } + + domain->irqdomain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT | + IRQ_DOMAIN_FLAG_ISOLATED_MSI; + domain->irqdomain->msi_parent_ops = &riscv_iommu_msi_parent_ops; + irq_domain_update_bus_token(domain->irqdomain, DOMAIN_BUS_MSI_REMAP); + dev_set_msi_domain(dev, domain->irqdomain); + + return 0; +} + +void riscv_iommu_ir_get_resv_regions(struct device *dev, struct list_head *head) +{ + struct riscv_iommu_info *info = dev_iommu_priv_get(dev); + struct riscv_iommu_domain *domain = info->domain; + struct iommu_resv_region *reg; + phys_addr_t base, addr; + size_t nr_pages, i; + + if (!domain || !domain->msiptp.msiptp) + return; + + base = domain->msiptp.msi_addr_pattern << 12; + + if (domain->group_index_bits) { + phys_addr_t group_mask = BIT(domain->group_index_bits) - 1; + phys_addr_t group_shift = domain->group_index_shift - 12; + phys_addr_t mask = domain->msiptp.msi_addr_mask & ~(group_mask << group_shift); + + nr_pages = mask + 1; + } else { + nr_pages = domain->msiptp.msi_addr_mask + 1; + } + + for (i = 0; i < BIT(domain->group_index_bits); i++) { + addr = base | (i << domain->group_index_shift); + reg = iommu_alloc_resv_region(addr, nr_pages * 4096, + 0, IOMMU_RESV_MSI, GFP_KERNEL); + if (reg) + list_add_tail(®->list, head); + } +} + +void riscv_iommu_irq_domain_remove(struct riscv_iommu_domain *domain) +{ + struct fwnode_handle *fn; + + if (!domain->irqdomain) + return; + + iommu_free_pages(domain->msi_root, domain->msi_order); + + fn = domain->irqdomain->fwnode; + irq_domain_remove(domain->irqdomain); + irq_domain_free_fwnode(fn); +} + +void riscv_iommu_irq_domain_unlink(struct riscv_iommu_domain *domain, + struct device *dev) +{ + if (!domain || !domain->irqdomain) + return; + + dev_set_msi_domain(dev, domain->irqdomain->parent); +} diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index 6e8ea3d22ff5..c4a47b21c58f 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -943,7 +943,8 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain, rcu_read_unlock(); } -#define RISCV_IOMMU_FSC_BARE 0 +#define RISCV_IOMMU_FSC_BARE 0 +#define RISCV_IOMMU_IOHGATP_BARE 0 /* * Update IODIR for the device. @@ -1245,6 +1246,8 @@ static void riscv_iommu_free_paging_domain(struct iommu_domain *iommu_domain) WARN_ON(!list_empty(&domain->bonds)); + riscv_iommu_irq_domain_remove(domain); + if (domain->pscid > 0) ida_free(&riscv_iommu_pscids, domain->pscid); if (domain->gscid > 0) @@ -1276,10 +1279,30 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_device *iommu = dev_to_iommu(dev); struct riscv_iommu_info *info = dev_iommu_priv_get(dev); struct riscv_iommu_dc dc = {0}; + int ret; if (!riscv_iommu_pt_supported(iommu, domain->pgd_mode)) return -ENODEV; + if (riscv_iommu_bond_link(domain, dev)) + return -ENOMEM; + + if (iommu_domain->type == IOMMU_DOMAIN_UNMANAGED) { + domain->gscid = ida_alloc_range(&riscv_iommu_gscids, 1, + RISCV_IOMMU_MAX_GSCID, GFP_KERNEL); + if (domain->gscid < 0) { + riscv_iommu_bond_unlink(domain, dev); + return -ENOMEM; + } + + ret = riscv_iommu_irq_domain_create(domain, dev); + if (ret) { + riscv_iommu_bond_unlink(domain, dev); + ida_free(&riscv_iommu_gscids, domain->gscid); + return ret; + } + } + if (domain->gscid) { dc.iohgatp = FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, domain->pgd_mode) | FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) | @@ -1292,10 +1315,9 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain, dc.ta = FIELD_PREP(RISCV_IOMMU_PC_TA_PSCID, domain->pscid) | RISCV_IOMMU_PC_TA_V; - if (riscv_iommu_bond_link(domain, dev)) - return -ENOMEM; - riscv_iommu_iodir_update(iommu, dev, &dc); + + riscv_iommu_irq_domain_unlink(info->domain, dev); riscv_iommu_bond_unlink(info->domain, dev); info->domain = domain; @@ -1389,9 +1411,12 @@ static int riscv_iommu_attach_blocking_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_dc dc = {0}; dc.fsc = RISCV_IOMMU_FSC_BARE; + dc.iohgatp = RISCV_IOMMU_IOHGATP_BARE; /* Make device context invalid, translation requests will fault w/ #258 */ riscv_iommu_iodir_update(iommu, dev, &dc); + + riscv_iommu_irq_domain_unlink(info->domain, dev); riscv_iommu_bond_unlink(info->domain, dev); info->domain = NULL; @@ -1413,15 +1438,24 @@ static int riscv_iommu_attach_identity_domain(struct iommu_domain *iommu_domain, struct riscv_iommu_dc dc = {0}; dc.fsc = RISCV_IOMMU_FSC_BARE; + dc.iohgatp = RISCV_IOMMU_IOHGATP_BARE; dc.ta = RISCV_IOMMU_PC_TA_V; riscv_iommu_iodir_update(iommu, dev, &dc); + + riscv_iommu_irq_domain_unlink(info->domain, dev); riscv_iommu_bond_unlink(info->domain, dev); info->domain = NULL; return 0; } +static void riscv_iommu_get_resv_regions(struct device *dev, + struct list_head *head) +{ + riscv_iommu_ir_get_resv_regions(dev, head); +} + static struct iommu_domain riscv_iommu_identity_domain = { .type = IOMMU_DOMAIN_IDENTITY, .ops = &(const struct iommu_domain_ops) { @@ -1516,6 +1550,7 @@ static const struct iommu_ops riscv_iommu_ops = { .blocked_domain = &riscv_iommu_blocking_domain, .release_domain = &riscv_iommu_blocking_domain, .domain_alloc_paging = riscv_iommu_alloc_paging_domain, + .get_resv_regions = riscv_iommu_get_resv_regions, .device_group = riscv_iommu_device_group, .probe_device = riscv_iommu_probe_device, .release_device = riscv_iommu_release_device, diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index dd538b19fbb7..6ce71095781c 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -23,6 +23,12 @@ #define RISCV_IOMMU_DDTP_TIMEOUT 10000000 #define RISCV_IOMMU_IOTINVAL_TIMEOUT 90000000 +struct riscv_iommu_msiptp_state { + u64 msiptp; + u64 msi_addr_mask; + u64 msi_addr_pattern; +}; + /* This struct contains protection domain specific IOMMU driver data. */ struct riscv_iommu_domain { struct iommu_domain domain; @@ -34,6 +40,13 @@ struct riscv_iommu_domain { int numa_node; unsigned int pgd_mode; unsigned long *pgd_root; + u32 group_index_bits; + u32 group_index_shift; + int msi_order; + struct riscv_iommu_msipte *msi_root; + spinlock_t msi_lock; + struct riscv_iommu_msiptp_state msiptp; + struct irq_domain *irqdomain; }; /* Private IOMMU data for managed devices, dev_iommu_priv_* */ @@ -119,6 +132,14 @@ void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, unsigned int timeout_us); +int riscv_iommu_irq_domain_create(struct riscv_iommu_domain *domain, + struct device *dev); +void riscv_iommu_irq_domain_remove(struct riscv_iommu_domain *domain); +void riscv_iommu_irq_domain_unlink(struct riscv_iommu_domain *domain, + struct device *dev); +void riscv_iommu_ir_get_resv_regions(struct device *dev, + struct list_head *head); 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da265ca8sm28719625e9.14.2024.11.14.08.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:02 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 09/15] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch Date: Thu, 14 Nov 2024 17:18:54 +0100 Message-ID: <20241114161845.502027-26-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081904_889449_ED278B4A X-CRM114-Status: UNSURE ( 7.79 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Tomasz Jeznach Enable KVM/VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- arch/riscv/kvm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index 0c3cbb0915ff..333d95da8ebe 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -29,10 +29,12 @@ config KVM select KVM_GENERIC_DIRTYLOG_READ_PROTECT select KVM_GENERIC_HARDWARE_ENABLING select KVM_MMIO + select KVM_VFIO select KVM_XFER_TO_GUEST_WORK select KVM_GENERIC_MMU_NOTIFIER select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS + select SRCU help Support hosting virtualized guest machines. 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae161d8sm1901964f8f.78.2024.11.14.08.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:04 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 10/15] RISC-V: KVM: Add irqbypass skeleton Date: Thu, 14 Nov 2024 17:18:55 +0100 Message-ID: <20241114161845.502027-27-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081906_881037_EB7D5937 X-CRM114-Status: GOOD ( 12.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add all the functions needed to wire up irqbypass support. kvm_arch_update_irqfd_routing() is left unimplemented, so return false from kvm_arch_has_irq_bypass(). Signed-off-by: Andrew Jones --- arch/riscv/include/asm/kvm_host.h | 3 ++ arch/riscv/kvm/Kconfig | 1 + arch/riscv/kvm/aia_imsic.c | 6 ++++ arch/riscv/kvm/vm.c | 60 +++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 35eab6e0f4ae..fef7422939f6 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -114,6 +114,9 @@ struct kvm_arch { /* AIA Guest/VM context */ struct kvm_aia aia; + +#define __KVM_HAVE_ARCH_ASSIGNED_DEVICE + atomic_t assigned_device_count; }; struct kvm_cpu_trap { diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig index 333d95da8ebe..9a4feb1e671d 100644 --- a/arch/riscv/kvm/Kconfig +++ b/arch/riscv/kvm/Kconfig @@ -21,6 +21,7 @@ config KVM tristate "Kernel-based Virtual Machine (KVM) support (EXPERIMENTAL)" depends on RISCV_SBI && MMU select HAVE_KVM_IRQCHIP + select HAVE_KVM_IRQ_BYPASS select HAVE_KVM_IRQ_ROUTING select HAVE_KVM_MSI select HAVE_KVM_VCPU_ASYNC_IOCTL diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index a8085cd8215e..64b1f3713dd5 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -727,6 +727,12 @@ void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu) kvm_riscv_aia_free_hgei(old_vsfile_cpu, old_vsfile_hgei); } +int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, + uint32_t guest_irq, bool set) +{ + return -ENXIO; +} + int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu) { unsigned long flags; diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index 7396b8654f45..9c5837518c1a 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -11,6 +11,9 @@ #include #include #include +#include + +#include const struct _kvm_stats_desc kvm_vm_stats_desc[] = { KVM_GENERIC_VM_STATS() @@ -55,6 +58,63 @@ void kvm_arch_destroy_vm(struct kvm *kvm) kvm_riscv_aia_destroy_vm(kvm); } +void kvm_arch_start_assignment(struct kvm *kvm) +{ + atomic_inc(&kvm->arch.assigned_device_count); +} +EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); + +void kvm_arch_end_assignment(struct kvm *kvm) +{ + atomic_dec(&kvm->arch.assigned_device_count); +} +EXPORT_SYMBOL_GPL(kvm_arch_end_assignment); + +bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm) +{ + return arch_atomic_read(&kvm->arch.assigned_device_count); +} +EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); + +bool kvm_arch_has_irq_bypass(void) +{ + return false; +} + +int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, + struct irq_bypass_producer *prod) +{ + struct kvm_kernel_irqfd *irqfd = + container_of(cons, struct kvm_kernel_irqfd, consumer); + int ret; + + irqfd->producer = prod; + kvm_arch_start_assignment(irqfd->kvm); + ret = kvm_arch_update_irqfd_routing(irqfd->kvm, prod->irq, irqfd->gsi, true); + if (ret) + kvm_arch_end_assignment(irqfd->kvm); + + return ret; +} + +void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, + struct irq_bypass_producer *prod) +{ + struct kvm_kernel_irqfd *irqfd = + container_of(cons, struct kvm_kernel_irqfd, consumer); + int ret; + + WARN_ON(irqfd->producer != prod); + irqfd->producer = NULL; + + ret = kvm_arch_update_irqfd_routing(irqfd->kvm, prod->irq, irqfd->gsi, false); + if (ret) + pr_info("irq bypass consumer (token %p) unregistration fails: %d\n", + irqfd->consumer.token, ret); + + kvm_arch_end_assignment(irqfd->kvm); +} + int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irql, bool line_status) { From patchwork Thu Nov 14 16:18:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AB7BD68B34 for ; Thu, 14 Nov 2024 16:19:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dab76dafsm25510275e9.10.2024.11.14.08.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:05 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 11/15] RISC-V: Define irqbypass vcpu_info Date: Thu, 14 Nov 2024 17:18:56 +0100 Message-ID: <20241114161845.502027-28-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081908_438858_62B12537 X-CRM114-Status: UNSURE ( 7.06 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The vcpu_info parameter to irq_set_vcpu_affinity() effectively defines an arch specific IOMMU <=> hypervisor protocol. Provide a definition for the RISCV IOMMU. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/irq.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 7b038f3b7cb0..8588667cbb5f 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -23,6 +23,15 @@ void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); struct fwnode_handle *riscv_get_intc_hwnode(void); +struct riscv_iommu_vcpu_info { + u64 msi_addr_pattern; + u64 msi_addr_mask; + u32 group_index_bits; + u32 group_index_shift; + u64 gpa; + u64 hpa; +}; + #ifdef CONFIG_ACPI enum riscv_irqchip_type { From patchwork Thu Nov 14 16:18:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9937D68B33 for ; Thu, 14 Nov 2024 16:19:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EmCiIXIfYwNbKG3QxZltF195sD/SlA0tHhGzL/3eWzA=; b=Z748JnDUK2CJaM wdbrS6S3KVB629TzYHIyWU/O7CuLjXYp8616DhzRF+9HkNe0D4CKxaL5fN9fk2iiGA+f4r92uVHqg TXbvcyqRiz7ckJEPxBR4/SnKgIBkZaLhib6SlAgss4orykpVgLDE5J591XraFwtqkPRQhwVnWEH3j qrH/lcSWWdGTUUcLOMnCLwAT2iQxLNuwiONHAZ35muoQuMc+hl7yp/agxQ1nf6W7iNCzpq8ESe19v hWP9jz7djWJ0gRsjjDTYxK2Nkrc52R3s8tIjQQAg1ONGeFzZDsBlfV8zqvF3gRm9sUerzaVz3+C+1 2P46civG2nzWTfskwLyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYt-000000005SV-43sf; Thu, 14 Nov 2024 16:19:16 +0000 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYn-000000005E8-387Q for linux-riscv@lists.infradead.org; Thu, 14 Nov 2024 16:19:11 +0000 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-37d6a2aa748so499810f8f.1 for ; Thu, 14 Nov 2024 08:19:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601147; x=1732205947; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+uTuyHOKGUnE3VHWBJ7LYW/wszuVbaF5PQNKaXjnEr8=; b=EfIrSNV3hLkjtjLS/HB5+Krl6LlKnQYhRqILNODVPWw3oomWoEySn/qlvdBHIKKXwZ iCnHABT4le1BpGUuinvS51CN/gBSpd+Xo9HZ/BbsmQumZjNyJIKG81ciHV7qAOxf8Rhn cq2Bel6XZnUTMjkhalNAZVtla64ZqADhcDrvmdua0uNA1qUo1PLmsV5j9ksZEJF24D9s zuJzQlRwd1ATGqmzsSI+AkgOxB39QngCEDij2PFzRr9Qkc9w9UHLNP5yU9u/WPc1gUvK gMQUPLwSNyitwbBz+tvajbkavgX3MrdEb8dbDDlHov/2ipqF30LLzx4r8VGQd6sR+Ox1 Ov8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601147; x=1732205947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+uTuyHOKGUnE3VHWBJ7LYW/wszuVbaF5PQNKaXjnEr8=; b=vL7S6ue93mTwUo814ihKfbANaWFuBSYmT8t34LOUYJCYkQ/HWvT9A9PR94cuK3bQqC PWjOIqWr9TJ5hBaAz0u1fNmIOBraXpuoW2GjMwmGM/jTtM9ZlLQ2qAL4yP5GtwURgz/d RZEvZ2I0ZyIR+Ik5sK0TQnIUrx3gWClIAZHh2t+M/wg0iInhQSvS2TV3v0H2i++Q7ASQ kQbKUWe8kNsMaqCJ1AhkRsV/NtqbMFcQ9Z78vMoZ8SCIMCNV276CzWo+ZS00NoRdxcuX GWgfvEoXAIgFT976hFv3wLC1HiOhelKO99+KxKYKmgpFybi0l7JaiFO4+/B39QphjLqH bgiQ== X-Forwarded-Encrypted: i=1; AJvYcCVAgcM+5scqiLyyLs40s3VRK3TkZNHZryt4LYmAJQ693MRve+I0sYHPXieDmzv9ZADUpiM4opzzqSaWLg==@lists.infradead.org X-Gm-Message-State: AOJu0YzcOQwTSnvYIJv3PeEV6ir0WGtOpASZKZgC7GT0+3ndUuvCSs/V Cb0leJxAHBhdapJADRoTgbnfKjwnta/aL6qPTuyffKFI11ct9YngJ3gD0QCjld4= X-Google-Smtp-Source: AGHT+IF+dux3jioiQujAjXbkRVUUE8HYuaL/Pb+N/XvgW2ONJ3mvlvI5/3yMLnI7JF+vXby3PurS7Q== X-Received: by 2002:a05:6000:156b:b0:37d:498a:a233 with SMTP id ffacd0b85a97d-382185391demr2252298f8f.43.1731601147550; Thu, 14 Nov 2024 08:19:07 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ada4076sm1858965f8f.16.2024.11.14.08.19.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:07 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 12/15] iommu/riscv: Add guest file irqbypass support Date: Thu, 14 Nov 2024 17:18:57 +0100 Message-ID: <20241114161845.502027-29-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081909_861291_6BFDAFF3 X-CRM114-Status: GOOD ( 22.06 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Implement irq_set_vcpu_affinity() in the RISCV IOMMU driver. irq_set_vcpu_affinity() is the channel from a hypervisor to the IOMMU needed to ensure that assigned devices which direct MSIs to guest IMSIC addresses will have those MSI writes redirected to their corresponding guest interrupt files. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu-ir.c | 151 +++++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 4 +- drivers/iommu/riscv/iommu.h | 3 + 3 files changed, 156 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c index c177e064b205..958270450ec1 100644 --- a/drivers/iommu/riscv/iommu-ir.c +++ b/drivers/iommu/riscv/iommu-ir.c @@ -7,6 +7,8 @@ #include #include +#include + #include "../iommu-pages.h" #include "iommu.h" @@ -52,10 +54,159 @@ static size_t riscv_iommu_ir_nr_msiptes(struct riscv_iommu_domain *domain) return max_idx + 1; } +static void riscv_iommu_ir_msitbl_inval(struct riscv_iommu_domain *domain, + struct riscv_iommu_msipte *pte) +{ + struct riscv_iommu_bond *bond; + struct riscv_iommu_device *iommu, *prev; + struct riscv_iommu_command cmd; + u64 addr; + + addr = pfn_to_phys(FIELD_GET(RISCV_IOMMU_MSIPTE_PPN, pte->pte)); + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_inval_set_addr(&cmd, addr); + + /* Like riscv_iommu_iotlb_inval(), synchronize with riscv_iommu_bond_link() */ + smp_mb(); + + rcu_read_lock(); + + prev = NULL; + list_for_each_entry_rcu(bond, &domain->bonds, list) { + iommu = dev_to_iommu(bond->dev); + + if (iommu == prev) + continue; + + riscv_iommu_cmd_send(iommu, &cmd); + riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); + prev = iommu; + } + + rcu_read_unlock(); +} + +static void riscv_iommu_ir_msitbl_update(struct riscv_iommu_domain *domain, + struct riscv_iommu_msiptp_state *msiptp) +{ + struct riscv_iommu_bond *bond; + struct riscv_iommu_device *iommu, *prev; + struct riscv_iommu_command cmd; + struct iommu_fwspec *fwspec; + struct riscv_iommu_dc *dc; + int i; + + /* Like riscv_iommu_ir_msitbl_inval(), synchronize with riscv_iommu_bond_link() */ + smp_mb(); + rcu_read_lock(); + + prev = NULL; + list_for_each_entry_rcu(bond, &domain->bonds, list) { + iommu = dev_to_iommu(bond->dev); + fwspec = dev_iommu_fwspec_get(bond->dev); + + for (i = 0; i < fwspec->num_ids; i++) { + dc = riscv_iommu_get_dc(iommu, fwspec->ids[i]); + WRITE_ONCE(dc->msiptp, msiptp->msiptp); + WRITE_ONCE(dc->msi_addr_mask, msiptp->msi_addr_mask); + WRITE_ONCE(dc->msi_addr_pattern, msiptp->msi_addr_pattern); + } + + dma_wmb(); + + if (iommu == prev) + continue; + + riscv_iommu_cmd_inval_gvma(&cmd); + riscv_iommu_cmd_send(iommu, &cmd); + riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); + prev = iommu; + } + + rcu_read_unlock(); +} + +static int riscv_iommu_ir_msitbl_init(struct riscv_iommu_domain *domain, + struct riscv_iommu_vcpu_info *vcpu_info) +{ + domain->msiptp.msi_addr_pattern = vcpu_info->msi_addr_pattern; + domain->msiptp.msi_addr_mask = vcpu_info->msi_addr_mask; + domain->group_index_bits = vcpu_info->group_index_bits; + domain->group_index_shift = vcpu_info->group_index_shift; + + if (riscv_iommu_ir_nr_msiptes(domain) * sizeof(*domain->msi_root) > PAGE_SIZE * 2) + return -ENOMEM; + + domain->msiptp.msiptp = virt_to_pfn(domain->msi_root) | + FIELD_PREP(RISCV_IOMMU_DC_MSIPTP_MODE, + RISCV_IOMMU_DC_MSIPTP_MODE_FLAT); + + riscv_iommu_ir_msitbl_update(domain, &domain->msiptp); + + return 0; +} + +static int riscv_iommu_irq_set_vcpu_affinity(struct irq_data *data, void *info) +{ + struct riscv_iommu_vcpu_info *vcpu_info = info; + struct riscv_iommu_domain *domain = data->domain->host_data; + struct riscv_iommu_msipte *pte; + int ret = -EINVAL; + u64 pteval; + + if (WARN_ON(domain->domain.type != IOMMU_DOMAIN_UNMANAGED)) + return ret; + + spin_lock(&domain->msi_lock); + + if (!domain->msiptp.msiptp) { + if (WARN_ON(!vcpu_info)) + goto out_unlock; + + ret = riscv_iommu_ir_msitbl_init(domain, vcpu_info); + if (ret) + goto out_unlock; + } else if (!vcpu_info) { + /* + * Nothing to do here since we don't track host_irq <=> msipte mappings + * nor reference count the ptes. If we did do that tracking then we would + * decrement the reference count of the pte for the host_irq and possibly + * clear its valid bit if it was the last one mapped. + */ + ret = 0; + goto out_unlock; + } else if (WARN_ON(vcpu_info->msi_addr_pattern != domain->msiptp.msi_addr_pattern || + vcpu_info->msi_addr_mask != domain->msiptp.msi_addr_mask || + vcpu_info->group_index_bits != domain->group_index_bits || + vcpu_info->group_index_shift != domain->group_index_shift)) { + goto out_unlock; + } + + pte = riscv_iommu_ir_get_msipte(domain, vcpu_info->gpa); + if (!pte) + goto out_unlock; + + pteval = FIELD_PREP(RISCV_IOMMU_MSIPTE_M, 3) | + riscv_iommu_phys_to_ppn(vcpu_info->hpa) | + FIELD_PREP(RISCV_IOMMU_MSIPTE_V, 1); + + if (pte->pte != pteval) { + pte->pte = pteval; + riscv_iommu_ir_msitbl_inval(domain, pte); + } + + ret = 0; + +out_unlock: + spin_unlock(&domain->msi_lock); + return ret; +} + static struct irq_chip riscv_iommu_irq_chip = { .name = "IOMMU-IR", .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, + .irq_set_vcpu_affinity = riscv_iommu_irq_set_vcpu_affinity, }; static int riscv_iommu_irq_domain_alloc_irqs(struct irq_domain *irqdomain, diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index c4a47b21c58f..46ac228ba7ac 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -544,8 +544,8 @@ static irqreturn_t riscv_iommu_fltq_process(int irq, void *data) } /* Lookup and initialize device context info structure. */ -static struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iommu, - unsigned int devid) +struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iommu, + unsigned int devid) { const bool base_format = !(iommu->caps & RISCV_IOMMU_CAPABILITIES_MSI_FLAT); unsigned int depth; diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 6ce71095781c..2ca76edf48f5 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -127,6 +127,9 @@ struct riscv_iommu_bond { int riscv_iommu_init(struct riscv_iommu_device *iommu); void riscv_iommu_remove(struct riscv_iommu_device *iommu); +struct riscv_iommu_dc *riscv_iommu_get_dc(struct riscv_iommu_device *iommu, + unsigned int devid); + void riscv_iommu_cmd_send(struct riscv_iommu_device *iommu, struct riscv_iommu_command *cmd); void riscv_iommu_cmd_sync(struct riscv_iommu_device *iommu, From patchwork Thu Nov 14 16:18:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875450 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7D4ED68B35 for ; Thu, 14 Nov 2024 16:19:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da28b76fsm29185835e9.28.2024.11.14.08.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:08 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 13/15] RISC-V: KVM: Add guest file irqbypass support Date: Thu, 14 Nov 2024 17:18:58 +0100 Message-ID: <20241114161845.502027-30-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081910_642200_F93664FA X-CRM114-Status: GOOD ( 18.23 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Implement kvm_arch_update_irqfd_routing() which makes irq_set_vcpu_affinity() calls whenever the assigned device updates its target addresses and whenever the hypervisor has migrated a VCPU to another CPU (which requires changing the guest interrupt file). Signed-off-by: Andrew Jones --- arch/riscv/kvm/aia_imsic.c | 132 ++++++++++++++++++++++++++++++++++++- arch/riscv/kvm/vm.c | 2 +- 2 files changed, 130 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kvm/aia_imsic.c b/arch/riscv/kvm/aia_imsic.c index 64b1f3713dd5..6a7c23e25f79 100644 --- a/arch/riscv/kvm/aia_imsic.c +++ b/arch/riscv/kvm/aia_imsic.c @@ -11,11 +11,13 @@ #include #include #include +#include #include #include #include #include #include +#include #define IMSIC_MAX_EIX (IMSIC_MAX_ID / BITS_PER_TYPE(u64)) @@ -676,6 +678,14 @@ static void imsic_swfile_update(struct kvm_vcpu *vcpu, imsic_swfile_extirq_update(vcpu); } +static u64 kvm_riscv_aia_msi_addr_mask(struct kvm_aia *aia) +{ + u64 group_mask = BIT(aia->nr_group_bits) - 1; + + return (group_mask << (aia->nr_group_shift - IMSIC_MMIO_PAGE_SHIFT)) | + (BIT(aia->nr_hart_bits + aia->nr_guest_bits) - 1); +} + void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu) { unsigned long flags; @@ -730,7 +740,120 @@ void kvm_riscv_vcpu_aia_imsic_release(struct kvm_vcpu *vcpu) int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set) { - return -ENXIO; + struct irq_data *irqdata = irq_get_irq_data(host_irq); + struct kvm_irq_routing_table *irq_rt; + struct kvm_vcpu *vcpu; + unsigned long tmp, flags; + int idx, ret = -ENXIO; + + if (!set) + return irq_set_vcpu_affinity(host_irq, NULL); + + idx = srcu_read_lock(&kvm->irq_srcu); + irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); + if (guest_irq >= irq_rt->nr_rt_entries || + hlist_empty(&irq_rt->map[guest_irq])) { + pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", + guest_irq, irq_rt->nr_rt_entries); + goto out; + } + + kvm_for_each_vcpu(tmp, vcpu, kvm) { + struct imsic *imsic = vcpu->arch.aia_context.imsic_state; + gpa_t ippn = vcpu->arch.aia_context.imsic_addr >> IMSIC_MMIO_PAGE_SHIFT; + struct kvm_aia *aia = &kvm->arch.aia; + struct kvm_kernel_irq_routing_entry *e; + + hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { + struct msi_msg msg[2] = { + { + .address_hi = e->msi.address_hi, + .address_lo = e->msi.address_lo, + .data = e->msi.data, + }, + }; + struct riscv_iommu_vcpu_info vcpu_info = { + .msi_addr_mask = kvm_riscv_aia_msi_addr_mask(aia), + .group_index_bits = aia->nr_group_bits, + .group_index_shift = aia->nr_group_shift, + }; + gpa_t target, tppn; + + if (e->type != KVM_IRQ_ROUTING_MSI) + continue; + + target = ((gpa_t)e->msi.address_hi << 32) | e->msi.address_lo; + tppn = target >> IMSIC_MMIO_PAGE_SHIFT; + + WARN_ON(target & (IMSIC_MMIO_PAGE_SZ - 1)); + + if (ippn != tppn) + continue; + + vcpu_info.msi_addr_pattern = tppn & ~vcpu_info.msi_addr_mask; + vcpu_info.gpa = target; + + read_lock_irqsave(&imsic->vsfile_lock, flags); + + if (WARN_ON_ONCE(imsic->vsfile_cpu < 0)) { + read_unlock_irqrestore(&imsic->vsfile_lock, flags); + goto out; + } + + vcpu_info.hpa = imsic->vsfile_pa; + + ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); + if (ret) { + read_unlock_irqrestore(&imsic->vsfile_lock, flags); + goto out; + } + + irq_data_get_irq_chip(irqdata)->irq_write_msi_msg(irqdata, msg); + + read_unlock_irqrestore(&imsic->vsfile_lock, flags); + } + } + + ret = 0; +out: + srcu_read_unlock(&kvm->irq_srcu, idx); + return ret; +} + +static int kvm_riscv_vcpu_irq_update(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm = vcpu->kvm; + struct imsic *imsic = vcpu->arch.aia_context.imsic_state; + struct kvm_aia *aia = &kvm->arch.aia; + u64 mask = kvm_riscv_aia_msi_addr_mask(aia); + u64 target = vcpu->arch.aia_context.imsic_addr; + struct riscv_iommu_vcpu_info vcpu_info = { + .msi_addr_pattern = (target >> IMSIC_MMIO_PAGE_SHIFT) & ~mask, + .msi_addr_mask = mask, + .group_index_bits = aia->nr_group_bits, + .group_index_shift = aia->nr_group_shift, + .gpa = target, + .hpa = imsic->vsfile_pa, + }; + struct kvm_kernel_irqfd *irqfd; + int host_irq, ret; + + spin_lock_irq(&kvm->irqfds.lock); + + list_for_each_entry(irqfd, &kvm->irqfds.items, list) { + if (!irqfd->producer) + continue; + host_irq = irqfd->producer->irq; + ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); + if (ret) { + spin_unlock_irq(&kvm->irqfds.lock); + return ret; + } + } + + spin_unlock_irq(&kvm->irqfds.lock); + + return 0; } int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu) @@ -797,14 +920,17 @@ int kvm_riscv_vcpu_aia_imsic_update(struct kvm_vcpu *vcpu) if (ret) goto fail_free_vsfile_hgei; - /* TODO: Update the IOMMU mapping ??? */ - /* Update new IMSIC VS-file details in IMSIC context */ write_lock_irqsave(&imsic->vsfile_lock, flags); + imsic->vsfile_hgei = new_vsfile_hgei; imsic->vsfile_cpu = vcpu->cpu; imsic->vsfile_va = new_vsfile_va; imsic->vsfile_pa = new_vsfile_pa; + + /* Update the IOMMU mapping */ + kvm_riscv_vcpu_irq_update(vcpu); + write_unlock_irqrestore(&imsic->vsfile_lock, flags); /* diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index 9c5837518c1a..5f697d9a37da 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -78,7 +78,7 @@ EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device); bool kvm_arch_has_irq_bypass(void) { - return false; + return true; } int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, From patchwork Thu Nov 14 16:18:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0CF6D68B34 for ; Thu, 14 Nov 2024 16:19:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LVEyhBTNHcMAQXZs6TGePcO8JqAk5vBLSa9WOHLp0Mg=; b=TJrGMkQj4Z4laV DWDLFwddlg2wdVDPXdVSDIZICXFdKmihsSICn8t3OvwlZmdhPv9DaWoBsKf7XfC5xlh6LdnuCcZzA R3O8gI4EdU9iM/QTWEgtOO9SmZZ3VTj0TzgkvdGz4lqJpaxSqggOUH9yw+YPCGfGXPoXi+0qODazM d6349WFGQPENXvgemq95g+XYp78noU+YDeBPBxOSEDbyl3jwLGoHav5lsfRiI30hCP5umKh2f6NpS WMK7c3TlaflsV1C2zo7SKiO80Z74vuirhAj4sVmhheowvky6FusWa6FxZu9MSYF36FRqsussqWVtq ICDiRNHX76G+JTadFTrQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYx-000000005Yn-0wVq; Thu, 14 Nov 2024 16:19:19 +0000 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYq-000000005Jh-2QpV for linux-riscv@lists.infradead.org; Thu, 14 Nov 2024 16:19:14 +0000 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4315839a7c9so7603335e9.3 for ; Thu, 14 Nov 2024 08:19:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601150; x=1732205950; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BmqNGe/T2iE9PlV9lB2/3K3MC1TQA7fI1NussKF1DE0=; b=n+EdAlLW3TmUhfnweGgRuCitKpOyzkU0eU3KKXfDp+SDhmaATLxnURQoZQiRiXLr44 rGbqFwsg9A4DG/U8B+PDAwovOKmWaY1+Y8Sy0OxnvueXX6dnB8CfWdsYOeu2WubtDBQ2 IkcUnhKGgFtM2wtL7tBQ19cctsL8LszpNsflA4avxKioI/1Y2XUoEovrm12p89+iGyTJ cHBlPMXam3FOy67Dpvk3gHnjqWJ5T//r2Rdp6V2ET3+lesy6oQHJyf5PjxhbYi10AO7o 6H3O/hWl3rr6TIAkJn/yol7xLxHChYAynswrEiScBSX3/VzDP+Qsi1Wur3coJnjikR8h tdaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601150; x=1732205950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BmqNGe/T2iE9PlV9lB2/3K3MC1TQA7fI1NussKF1DE0=; b=YVQ6A+c8EqerIC6F9Jw7FdpMNc3GrYDlSovmHY9TRughX0L2+RudtOE4RAscxEs9j4 vJuMfw2bwdwQnwzeNRtcwBIzu2c3fCIuDI/CdA+Qfj6tQztZ5wkinkbElfdrzqMG8V4G DhYsBIrPv+ObcD58Gypn+aLkL1/XZeCBMt/a7iENXMKe4J2xpdWI7FFIfU/d9vix0a80 IcOmZdE+ETVAinCPDcATcXvK0e6QGeQaNP44LrgaZbVPfT+DTxcp5ULbuXoAAzuF3cII +NSVKkZOmCSSUHS/GHxe9isay2vT4WY+bpTCQPwXAd1WojcBms8EDCLtGIzo51zKDcSs th7g== X-Forwarded-Encrypted: i=1; AJvYcCXU+1UmdUnF4ev56FS7jFbt/tWuF2rsTdMzB8CbQcNSBQS4fSyTYuG6v9OW4E4luUPaXYiQujqXW7hQQQ==@lists.infradead.org X-Gm-Message-State: AOJu0Yy3jcODtgrIXn1ON/Habqh1IhjmI672uLgW9NrkQv5tRx54kSon EYKnJpJzmU0iFhIRISAovh/37b+P2KS/3Ly0gkv5lXCPWGHzR6sFjxOlD1qEb/g= X-Google-Smtp-Source: AGHT+IGMbtDDWmvKWsj/Ybdc9TgUB55aFH3ajhr0ZnMlCbsRayCj2n5LaLaeoDlbaJzuEn6VOd9B/g== X-Received: by 2002:a05:600c:8715:b0:431:93d8:e1a1 with SMTP id 5b1f17b1804b1-432b751bcc2mr209410385e9.27.1731601150428; Thu, 14 Nov 2024 08:19:10 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821adbe779sm1834550f8f.60.2024.11.14.08.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:09 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 14/15] vfio: enable IOMMU_TYPE1 for RISC-V Date: Thu, 14 Nov 2024 17:18:59 +0100 Message-ID: <20241114161845.502027-31-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081912_643276_D3E56B0D X-CRM114-Status: UNSURE ( 9.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Tomasz Jeznach Enable VFIO support on RISC-V architecture. Signed-off-by: Tomasz Jeznach Signed-off-by: Andrew Jones --- drivers/vfio/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vfio/Kconfig b/drivers/vfio/Kconfig index ceae52fd7586..ad62205b4e45 100644 --- a/drivers/vfio/Kconfig +++ b/drivers/vfio/Kconfig @@ -39,7 +39,7 @@ config VFIO_GROUP config VFIO_CONTAINER bool "Support for the VFIO container /dev/vfio/vfio" - select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64) + select VFIO_IOMMU_TYPE1 if MMU && (X86 || S390 || ARM || ARM64 || RISCV) depends on VFIO_GROUP default y help From patchwork Thu Nov 14 16:19:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 13875452 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CBA4D68B33 for ; Thu, 14 Nov 2024 16:19:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XyMCzNRP9G5Cgwisaobpyb9kpkQlqvMrskZeEm4mJMg=; b=txEnU3USD1onJo ol5a+FV4ksV8si0bfpC3hlygPPMug3jW3unggVq6j9EFysGQmSa1dYfuOrsWns6xpa++IOKY2bdmQ HN+7i/T+c/RE99hxXd3ECC7ojg4yDYNQkHoyQT46lxVB7F3lpAMmJEcgtGNmaBWBiWF2iNTH7EuRo xThp48aGsPaWQFrUIp86Ff7QwesH4VN+6YHnxwJSJ7IyE2qkqlqPWyxVb7JJZGcpjgaT9FtqnilkL p2PL2CDZ5UIX4KHtr5BdrqGAYq8OUbkpqgWlmR1kA92oUTsYUeSY5dzF0TecZtrsjonkDY0ja/EH7 PIWZZ3rr72EMb+qj6FPw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYz-000000005d0-0zKE; Thu, 14 Nov 2024 16:19:21 +0000 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tBcYs-000000005Mg-10Sa for linux-riscv@lists.infradead.org; Thu, 14 Nov 2024 16:19:15 +0000 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4315e9e9642so7301135e9.0 for ; Thu, 14 Nov 2024 08:19:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731601152; x=1732205952; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bLyjPEUjYy3GGHllbim/73zpVvmemz3R8H3vfZF+LqU=; b=cvm6aO2dSgJV0zx5euWCE6fjcKMMPz1jU7oJjdYzUUBQtOC/X48aG2oZtYhb1hNq27 jrETBWSnOWg2LabmDtc4+tZ+VNgji/GQcFjTvEV7bd+LvBecQaCKTTKcoXj+VZvKtkCP MxEHhEMkMtzBQDP1pWx+QxnZGq93DF2CEXNkpNNZ5QQY/gsgXLcXRglIDzZs6YcKMKZD y5Z+Pfuf1nIkJvfuTeMY6/NOP77UcN3Izv16SgAr9GofdvJo2gt3canv/8TlbYmlRn5r QmiRVf3TLVQ31diKW+OpDxb80Z7seAKSTpf6x8esT2JV1zsUgxGKGr8L3qYtxJXzQbC3 3K7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731601152; x=1732205952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bLyjPEUjYy3GGHllbim/73zpVvmemz3R8H3vfZF+LqU=; b=i0HWEGF7wPPrIfqLxzMpkUnMaRENB56RK3C6TA0Y3OtY+RBHnj3nZqXWPK4CpQIh9p n3huA1anSsCrAUh6j6MckfZ5OADeuBY0Hlp+h9nFycKk0mkBqUPJM1iqJNZapBxhtI+U 80o5DRmoxDnnkFA9mYsdw5OsuiQXOWHlBCZZj43u+aeZyZK2/xxYfrxVMNVsOp8WtdO4 ZeCvb1i+ybQ73NclH+ikq5HYeKnt0UEW388Nira0RVAPsPa17/ZL5PJNVpQg8VqaoWGr f5sDgYtbBl/0PluTFnGUIwNWKwjKpyngTfEEv/QuxL0hx8mSU7m8cr0y7LgjfD19Iy3f D/hg== X-Forwarded-Encrypted: i=1; AJvYcCVeGAp8NdXvSxPYsDIvjbvBGyUKk0vuwwzrkHcv5+ehi8tBbqGD83NSZQc8B8q0IuMzpmXZhe5WJZlTSg==@lists.infradead.org X-Gm-Message-State: AOJu0YyGy/NPFGf4jz914D1wlvMf9BPS80hFJFujyKLGMrSQTLJqrOEU E7gYNbPYoyVc8Nt0veH/ak2Cr1UbWbcPOVbzIWSCRE9Cb9k/KOL02ivhekS/bUE= X-Google-Smtp-Source: AGHT+IHKQidNVhwcm1UkvoSFM0iFKvguMA4Koj+yRoQBZD+zU91sO767fbB1E85gsh6vbgzv0SLQ3g== X-Received: by 2002:a05:600c:c08:b0:42c:bd27:4c12 with SMTP id 5b1f17b1804b1-432d4aae6b7mr76573235e9.10.1731601152220; Thu, 14 Nov 2024 08:19:12 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da298a41sm29066525e9.38.2024.11.14.08.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:19:11 -0800 (PST) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tjeznach@rivosinc.com, zong.li@sifive.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, anup@brainfault.org, atishp@atishpatra.org, tglx@linutronix.de, alex.williamson@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Subject: [RFC PATCH 15/15] RISC-V: defconfig: Add VFIO modules Date: Thu, 14 Nov 2024 17:19:00 +0100 Message-ID: <20241114161845.502027-32-ajones@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241114161845.502027-17-ajones@ventanamicro.com> References: <20241114161845.502027-17-ajones@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241114_081914_288831_FF04F023 X-CRM114-Status: UNSURE ( 7.47 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add the VFIO modules to the defconfig to complement KVM now that there is IOMMU support. Signed-off-by: Andrew Jones --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index b4a37345703e..10fc9d84a28c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -242,6 +242,8 @@ CONFIG_RTC_DRV_SUN6I=y CONFIG_DMADEVICES=y CONFIG_DMA_SUN6I=m CONFIG_DW_AXI_DMAC=y +CONFIG_VFIO=m +CONFIG_VFIO_PCI=m CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y