From patchwork Sat Nov 16 08:18:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877518 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E27D320DF4; Sat, 16 Nov 2024 08:19:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745158; cv=none; b=kU4fs+ILH1iqBShvYQJeKjK+Wcs/t5RA/PvYdEZRp7VkNHXCvalbATCOkaVVOtkP0yc++bXJ52Em3RkNE1z9uoodzMHLN8x5EQd6E7nkNutME0K71f9dOeHJAABnDphunpnKfyVEJmpjzaqfDMzrEl5GOaAuMum0uF3Y5Yn8dyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745158; c=relaxed/simple; bh=J+DVNJlAR1atRomw7H5TuhZTdYIIbEgomihxOMAoX5M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F3uwI+AE0t/bDT4/FDKuVTC3KUfqmezrM61UwQKgR2Vntaf0Vz+A/1lHJI97w4xvO8WRnrdB2c8duEpTmEkIOMbs1NVL8XRP/CI1ghLZ9Jp4OKo9tyiDbnor6K70on9rEA7XlNcE+nsKO3R0PxGOZpvR7gBpePOQ3yhOxiwxsb0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uIyUD/yv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uIyUD/yv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F0D1C4CEC3; Sat, 16 Nov 2024 08:19:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731745157; bh=J+DVNJlAR1atRomw7H5TuhZTdYIIbEgomihxOMAoX5M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=uIyUD/yvUSrEoTE/S3wJaDxbs82yNXWlktu7Lm37wCtP7d42O4HY4HpHDRV9B7FDv iFaH9I84SURPSxIJxjmoVKcELPFdYuEYOX/5aCumHg3xFBUVCJ7cObU6jhyILcf86G VFb5dtUF+t3KIRokoM9wvcyN7WjW8x0IalhCmCuwaf7UQ4UPlL/5U+5DsRga8X+X1z 8eRQw7iI/NqjesAlnHwmLxtR2eYq44eJAtL5D1csJvhc9XotIlYerliZZtbnpHsPVw wYaqC1I6BHQ2jYJ8Wgw7lKhWNNjMHSKbFs22kBzP272TCsa9oatmJ+xqjEfH/zI8Ek yJiGpPdpcHHBQ== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:22 +0100 Subject: [PATCH v3 1/6] PCI: mediatek-gen3: Add missing reset_control_deassert() for mac_rst in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-1-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Even if this is not a real issue since Airoha EN7581 SoC does not require the mac reset line, add missing reset_control_deassert() for mac reset line in mtk_pcie_en7581_power_up() callback. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 64ef8ff71b0357b9bf9ad8484095b7aa60c22271..4d1c797a32c236faf79428eb8a83708e9c4f21d8 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -942,6 +942,9 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* MAC power on and enable transaction layer clocks */ + reset_control_deassert(pcie->mac_reset); + pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -976,6 +979,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) err_clk_prepare: pm_runtime_put_sync(dev); pm_runtime_disable(dev); + reset_control_assert(pcie->mac_reset); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); err_phy_deassert: phy_power_off(pcie->phy); From patchwork Sat Nov 16 08:18:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877519 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2372020DF4; Sat, 16 Nov 2024 08:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745163; cv=none; b=EXCmKRd+Px0EXCtPfNPC/OTPh+7ss+romuB7t0mdFyKrTSyAQc+AXT4GAn4LWmtFZNBFKt1tpytVXRXZfJgj5x7vUZBzl74MpScKBMLxSo+sgQMoEYurVKQ1DGSeA+OpNNd+E0sDnSppR6IB2T42yjA+14j+yh3b5tEXQB1DLo4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745163; c=relaxed/simple; bh=VOD7JgWg4ieAEy60C9NaBSC0zOJOaSCD6UKWyZp1TWA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cz8LTUSFmrgCfM4CXi8IS/blTXfXFtyJo2pVxY2uWv4C3L0LN4s7AzEIYLQvIDErgBJ3Lhf3rqfMNhhP2cuc0yaFgyv2Wq2wKjNZzFu+o4fbpHAgi/CR+Z7sFnMfs0jSn4elSKLbWVciCVkz0Byh1iNTteK4KGwe9a7qUMxxIzY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p4dytTL7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p4dytTL7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3A2C2C4CEC3; Sat, 16 Nov 2024 08:19:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731745163; bh=VOD7JgWg4ieAEy60C9NaBSC0zOJOaSCD6UKWyZp1TWA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=p4dytTL7PmB5uuVo8kHqNi+uQnyHKGGNHbqKHneCSAuSdHiiO+hCqv0zY33lUMdfW PEir62JmXbl3OuC3s12c/RUedKzSQPf0r7DWk98BGH0c66Gr074jud0YAfCUj5J25M cjkBuqPLr4S2GVA7ZFQRYqYyueSSaN7ORia/VAGeCJv5zjfFEB3/DdeOZrNtyleMXU 5XNsCtvAQm3g5LZXFD3NEhH9DJPNSq/BJ4syX/wzoo0rwLP6eaLPa4i4kPfT8o6zYM ZLcXBVFcFb2hIommYc1Y5WD4xj4TJVsHvF2+SZ0yuRzGNcGKpK8n0arjmPKPGV1WLT MZod396/j55SA== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:23 +0100 Subject: [PATCH v3 2/6] PCI: mediatek-gen3: rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-2-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Replace clk_bulk_prepare() and clk_bulk_enable() with clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 4d1c797a32c236faf79428eb8a83708e9c4f21d8..3cfcb45d31508142d28d338ff213f70de9b4e608 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -948,12 +948,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -966,17 +960,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_prepare_enable; } return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); reset_control_assert(pcie->mac_reset); From patchwork Sat Nov 16 08:18:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877520 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16C4638382; Sat, 16 Nov 2024 08:19:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745168; cv=none; b=SX0jhgVy1HcZZvr9/yTlI4HpC01hufVz4S4YX7P2e3sUAn4XD6fRxDTNCmiNJ8cWqAvelbGBulZFQHoC5D9ucr/ci6Pe/J4k5FqsF2IEyrmZkl2N5fVMzDqpcco5eOtinxIkks72K7MJMPrPgrLky7CO0Qxgc/D1xLGz+gORr8Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745168; c=relaxed/simple; bh=CUcpugj82iytRhkjUR6sYhraDFJqW4jyvGhHZ4iOlOk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nMY3sAtuQlZrOfDMqWik3dcBhlNcmuS9eS+MRRtHmWQS/BHU9mh0sZCF7dEf5ZiGvaqzQvs6ahgpeUPVZ3z2Pf5pBrHVHARUq7VUSdktt5QE4FIxHSwprdzKBqgccUteJYcQJ5RvkTOMXHyBwnhvKobKejp8b+MIrpv4VE3eWJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P7DdJ2rG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P7DdJ2rG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D218C4CEC3; Sat, 16 Nov 2024 08:19:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731745167; bh=CUcpugj82iytRhkjUR6sYhraDFJqW4jyvGhHZ4iOlOk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P7DdJ2rGanYqWy+VDkD9X3pI8THRiN03JohFbl667luBJl7Yn3yoG/P63tawO39Jq 8rQafq1KqXYnU0O+jt5uek9eCUHJCy9Iuu1c9wykYNnOQml7FtbLFRNqNg8ToIiyo5 a+pIQxDoS5N2TAYSqYah0QyOv6PpikXr0+zAk0wD479Z04Q/yXmZejx8tfc0mTY2sb M94xBZXdDPhT49KaBvCZP2/tVfWldWhDWe4YOVB490prK45are4cqYB/1rkK39C+NO QeZ8asnNf4g/LDsdrzT2I14S/DNCRL+CPydhtUjknBoIVfEs42VOCmzCT/G6Iesicy V6+J902OoXlvg== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:24 +0100 Subject: [PATCH v3 3/6] PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-3-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 In order to make the code more readable, the reset_control_bulk_assert() for PHY reset lines is moved to make it pair with reset_control_bulk_deassert() in mtk_pcie_power_up() and mtk_pcie_en7581_power_up(). The same change is done for reset_control_assert() used to assert MAC reset line. Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 3cfcb45d31508142d28d338ff213f70de9b4e608..2b80edd4462ad4e9f2a5d192db7f99307113eb8a 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -125,6 +125,8 @@ #define MAX_NUM_PHY_RESETS 3 +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -912,6 +914,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) int err; u32 val; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + /* * Wait for the time needed to complete the bulk assert in * mtk_pcie_setup for EN7581 SoC. @@ -986,6 +996,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); if (err) { @@ -1070,14 +1089,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * counter since the bulk is shared. */ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie); From patchwork Sat Nov 16 08:18:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877521 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1447338382; Sat, 16 Nov 2024 08:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745172; cv=none; b=q0af4yUfRl+bqQ4gEeJuvDoBJZ+85ZGII+6g4RbbVkFk/9ZFud3x1H1ibGcRyKoY39gTLH+j5Rxx6OwkR1Ik4t9ohHAjt6I/zDVLT42tdZMp3oRzJ+jE7DHSggBTjzCHliTFYIBlhRjcXnQD+H5aDj2x/STA348TKAKcWK2ukVM= ARC-Message-Signature: i=1; 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b=MO5STveOVD0odbSgLIzSj/yq1GdC7poAi7FEnmHg+3sKxl4fm0Aqp6/mvYCGHq5Jo IlnRpPxwGsZZZbTCIqwFWml87iKrbTZOgXkT4x4SdPGCaSXxD+ySsinDvstOy4f20X QPAfXVTugoivf4Rt+OPYCJ2NUaNpec5IJbjGl+CIJXrBkzGSE/l91lRxft3DnOBpyA uBasviRc7HqVfUHf9t/oFITErP3ptGDhSZ2tcI8s01amyOWeHYM52rSaq80jxbC8Vi ME4uodSh3QS8xpRiNXtwRMQ3X544fERN1CrVKqNGZV/fLlwqcHYGH1Z8Qg2AlpB7nF MT9/VM5giFWXA== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:25 +0100 Subject: [PATCH v3 4/6] PCI: mediatek-gen3: Add comment about initialization order in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-4-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike MediaTek PCIe controller, the Airoha EN7581 requires PHY initialization and power-on before PHY reset deassert. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 2b80edd4462ad4e9f2a5d192db7f99307113eb8a..dd30530a43b1097871acc9e76a7534f30819432d 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -928,6 +928,10 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* + * Unlike the MediaTek controllers, the Airoha EN7581 requires PHY + * initialization and power-on before PHY reset deassert. + */ err = phy_init(pcie->phy); if (err) { dev_err(dev, "failed to initialize PHY\n"); From patchwork Sat Nov 16 08:18:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877522 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9059238382; Sat, 16 Nov 2024 08:19:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745176; cv=none; b=gMEUcaLAzoAJZ2aYH/XmU2OXN+iGz7Plt6NbriFxam/R1oKcfBiSpV3kfSdYwwEuIyD16JQMAF1yw4z+7epj2v9ga/G/Z8JRhHsQVqpiew8h0HF27R5fDuhIFn5mdh7t+mvXVpH50MFrVb+ChjNLrdKr8HsSfFmsGa/yNxCeYDU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745176; c=relaxed/simple; bh=L4hA2wy50Ckn1zmHwXFzkEw586yHIeg2jaZbtr70EFA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Lj5O/ELgxsfW1WuO4++0SqW6bw5UbDkzjt3zg1Lnxq7NjP4jLhJ2V4WFZ9qCJW8yILw5tgBuJPbwrVIttvf6P/oDhnW51kECEXjUrA//MZmbfTRtlqMK/0/VL65VlkhQ7VqZs25pJk7akAii8M5rRM/UqdMPCV6g5koZEo9embA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Tot5XOPX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Tot5XOPX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9F20C4CEC3; Sat, 16 Nov 2024 08:19:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731745176; bh=L4hA2wy50Ckn1zmHwXFzkEw586yHIeg2jaZbtr70EFA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Tot5XOPXlSP4EzGywdvLL4decfH9hIuKyEHI3PRdHkubDoyx33bpMTXP0dgB11FMB EpsB4VKPrkXoLLY5qJwPP8p0h8+TpXDY/yp5FC2aO3brEcSLtyY5QZ7BDAOKgFHNLI H5Iyi24/jXAfgzBd/GOikwpSz0UHunfxFvlugtVisUpWep3wEKXhpCOacmDT7hKoqO ZjUiFHuknfJknYCC+Cjv8suevXJ8DRM56ZDHePT1+eO6ROnL+Gve3Zx5gdrEr5Bbt0 T6Xh/Dg+5Kpc89OnxvkEciq+6j+k4Je/M6Gie+eO64e+/xVG9YTYGFNkSYBAhAbrbl 9Gn8m2hfOvxMA== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:26 +0100 Subject: [PATCH v3 5/6] PCI: mediatek-gen3: Add reset delay in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-5-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal causing occasional PCIe link down issues. In order to overcome the problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and REG_RESET_CONTROL (0x834) registers available in the clock module running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). In order to make the code more readable, move the wait for the time needed to complete the PCIe reset from en7581_pci_enable() to mtk_pcie_en7581_power_up(). Reduce reset timeout from 250ms to PCIE_T_PVPERL_MS (100ms). Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/clk-en7523.c | 1 - drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); return 0; } diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index dd30530a43b1097871acc9e76a7534f30819432d..795f134e1970c504e8d9588c09a9c3ff51e5397e 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -980,6 +980,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; err_clk_prepare_enable: From patchwork Sat Nov 16 08:18:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13877523 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BD6020DF4; Sat, 16 Nov 2024 08:19:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745181; cv=none; b=ozZUCKmgcUrtaU1bbbK3/7v+/ogjxOaMx60V+EeRJazwoREEg2fjPJBbSs5JVzHjtce+xiSFzzTfUaMwAClZ9qZQpssIz+HkbVdOEMowsfPS+hJZDVdzATSYdWjGnWDof+qu28QhDxpw6oxVNbW/6E6Y6rdIrvK9Lap598WX1yQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731745181; c=relaxed/simple; bh=5ckEAFt3DCXgUGzrfG8vGUMcL5UShRW6eE3OUEf8DWo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q6I4+I6EWstrsdMNVHid3xnmNdehyIwGgdjhRk7IeBgUdFgVsdeaVOlDW5pI7ntN2ktzk1+uMDipeFXxx1ja13bXyFOzE8yDhg2eAWvNRg6zh3y60Gm60avNaUSR2BJV4Mnpu3T10wd443chq6cesNpJ4sjBjugZrqmP/D9cSa4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PHDw2jUn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PHDw2jUn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 711AAC4CEC3; Sat, 16 Nov 2024 08:19:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731745180; bh=5ckEAFt3DCXgUGzrfG8vGUMcL5UShRW6eE3OUEf8DWo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PHDw2jUn3ctkoH1Bf8Glb8QZo2OPAuZJaGTG7vPfibtyxjLOQiCuVCsGyzsPwbOX6 XB6d99IK7HwSlgSHOwTylt7T+sI6dTABaHdgo19bW7Wq5kGcLGwBdSelmGHkxS6KkI WiDncig5kE5mXrxpaT+V2Cxbx3RQdgmWOVx0r5se2XMsqkrp9QODGvwQWtBPzqzrfM 4GtSHbZ4XK2HY7qCBXCh17Bf57Uz53TMWL7zjiN9yCe3KKwzxZrroWjO8n6PmNfQdI xeZAg26j8FtuIB/x2xDJTXqa6h/vl4Fq0wLopnpw/Hh09kUiBFnjaXZ59daii1SJuk r8wLNAvQl1oWg== From: Lorenzo Bianconi Date: Sat, 16 Nov 2024 09:18:27 +0100 Subject: [PATCH v3 6/6] PCI: mediatek-gen3: rely on msleep() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241116-pcie-en7581-fixes-v3-6-f7add3afc27e@kernel.org> References: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> In-Reply-To: <20241116-pcie-en7581-fixes-v3-0-f7add3afc27e@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Since mtk_pcie_en7581_power_up() runs in non-atomic context, rely on msleep() routine instead of mdelay(). Signed-off-by: Lorenzo Bianconi Reviewed-by: AngeloGioacchino Del Regno --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 795f134e1970c504e8d9588c09a9c3ff51e5397e..aaec0cb6cc1c016d049e8a88148870de560b9ce2 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -926,7 +926,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) * Wait for the time needed to complete the bulk assert in * mtk_pcie_setup for EN7581 SoC. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); /* * Unlike the MediaTek controllers, the Airoha EN7581 requires PHY @@ -954,7 +954,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) * Wait for the time needed to complete the bulk de-assert above. * This time is specific for EN7581 SoC. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); /* MAC power on and enable transaction layer clocks */ reset_control_deassert(pcie->mac_reset);