From patchwork Mon Nov 18 06:02:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878124 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62E3414659C; Mon, 18 Nov 2024 06:02:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909744; cv=none; b=E4xJKe5O2jqErWVD6rpcv37fGnZOy8NDClaTykQgSH9hmjbsa14JOYw8WKGt2vSsN9dbpnB2+y9ndqls3RdmvBR1ZkJXVoVlZ4H+Rnura8euCbN/5CBSpqn+y9wHVXmC0hX8m0Fd0pXh9ARnuX4+AotoLwYQLMFQTmP1A1RimqY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909744; c=relaxed/simple; bh=E6DZgxFASwkXaa+nRaWgDMNGtH9csCAM0/EQpYf//cM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=odlQ5YPyos2q2FdnZopzW3Og9UDEWkaT5UHG+3AE6POuY4XC9aX1xqZciCGKZi7kLu1rxfcLxH/odSUphcVypMM/U4m97cm8bvk6eB6ktc3Xrbr/hXOhmBIEkfH5sOkDgVrBjVi+Bu7lVdzhHRc924UKC7p2VmImu6C+DnP9D6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:07 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 1/7] dt-bindings: net: ftgmac100: support for AST2700 Date: Mon, 18 Nov 2024 14:02:01 +0800 Message-ID: <20241118060207.141048-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org The AST2700 is the 7th generation SoC from Aspeed. Add compatible support for AST2700 in yaml. Signed-off-by: Jacky Chou --- Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 9bcbacb6640d..fffe5c51daa9 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -21,6 +21,7 @@ properties: - aspeed,ast2400-mac - aspeed,ast2500-mac - aspeed,ast2600-mac + - aspeed,ast2700-mac - const: faraday,ftgmac100 reg: @@ -33,7 +34,7 @@ properties: minItems: 1 items: - description: MAC IP clock - - description: RMII RCLK gate for AST2500/2600 + - description: RMII RCLK gate for AST2500/2600/2700 clock-names: minItems: 1 From patchwork Mon Nov 18 06:02:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878125 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A5B714831F; Mon, 18 Nov 2024 06:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909746; cv=none; b=tvXNcPuJRlYEBkbfrswl7KkvikTc89njUt2RVX+amvodI2VwE9e7vNtli85+PT6kI0gL9hJnraDwofeOUHQERRgMoPfXBy5jKPdOYhmyzZeOI/d3iaPtJ3ahsdIiqvznhITa7O5WPrgsxIM1RnnHNF0WYDowRTDfAZ4wo0i3yLE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909746; c=relaxed/simple; bh=lW3Yhn3mcDRma1Y+lv8Hv05//q7fTVEmZq6HiiPgyPQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ja6dBdPVtUI81Os4qpJTvEPHfeDF1f16bysAB2SwZIFkYP5Am8uwu4fFbLVq4KXYvhGUZcnm7v8+FmRXxjqOztymJiFXMFI/nKDXwxXGSluQNXhXBtIBvGYGHLR3cdkbmHBnGbWOs2mhEsfyhAhX111+3/nKFyA4HxhAvibMRnI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:07 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 2/7] net: faraday: Add ARM64 in FTGMAC100 for AST2700 Date: Mon, 18 Nov 2024 14:02:02 +0800 Message-ID: <20241118060207.141048-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org AST2700 is a ARM 64-bit SoC and ftgmac100 adds support 64-bit DMA capability in AST2700. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/faraday/Kconfig b/drivers/net/ethernet/faraday/Kconfig index c699bd6bcbb9..d5a088d88c3d 100644 --- a/drivers/net/ethernet/faraday/Kconfig +++ b/drivers/net/ethernet/faraday/Kconfig @@ -6,7 +6,7 @@ config NET_VENDOR_FARADAY bool "Faraday devices" default y - depends on ARM || COMPILE_TEST + depends on ARM || ARM64 || COMPILE_TEST help If you have a network (Ethernet) card belonging to this class, say Y. @@ -28,8 +28,7 @@ config FTMAC100 config FTGMAC100 tristate "Faraday FTGMAC100 Gigabit Ethernet support" - depends on ARM || COMPILE_TEST - depends on !64BIT || BROKEN + depends on ARM || ARM64 || COMPILE_TEST select PHYLIB select MDIO_ASPEED if MACH_ASPEED_G6 select CRC32 From patchwork Mon Nov 18 06:02:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878126 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E4BF14A099; Mon, 18 Nov 2024 06:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909748; cv=none; b=si8gbcQM0U4j4YRdAvouzRK89OU8g7ofBgsnUxa2tON+k1pmUGtmlmIuqN/G0hNOlVRBCnW5pHsKBxmGLIVb7kQeq1dpGO7EM3sCD0XRNxhUzt1NowmguRm2Vap/Vv3+ISldBke/vMiPeua2U0XzC6UbsP1XsyB/GO2zkrC7vAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909748; c=relaxed/simple; bh=rUbVC87+qBJbqfUjUNj6tUHnPS4oyc962Ejj0aBLm3Q=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=remUwoCAcgCgNQBYcusxyNx7YaAU6+ywqwuql310XxVcd63dINj3l6rJL0x6eurq5df6iHYhFMshCjBnU7l7TfNRZhwjXqxUca+KuHefYfJTUnWp8XuPcg/zDyZxYH2wN6jbbgG/fs6CvBQJ8RTMTEzHFhOjtC7j1mDVoMMpamc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:07 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 3/7] net: ftgmac100: Add reset toggling for Aspeed SOCs Date: Mon, 18 Nov 2024 14:02:03 +0800 Message-ID: <20241118060207.141048-4-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Toggle the SCU reset before hardware initialization. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/ftgmac100.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index 17ec35e75a65..cae23b712a6d 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -98,6 +99,7 @@ struct ftgmac100 { struct work_struct reset_task; struct mii_bus *mii_bus; struct clk *clk; + struct reset_control *rst; /* AST2500/AST2600 RMII ref clock gate */ struct clk *rclk; @@ -1969,10 +1971,29 @@ static int ftgmac100_probe(struct platform_device *pdev) } if (priv->is_aspeed) { + struct reset_control *rst; + err = ftgmac100_setup_clk(priv); if (err) goto err_phy_connect; + rst = devm_reset_control_get_optional(priv->dev, NULL); + if (IS_ERR(rst)) + goto err_register_netdev; + priv->rst = rst; + + err = reset_control_assert(priv->rst); + if (err) { + dev_err(priv->dev, "Failed to reset mac (%d)\n", err); + goto err_register_netdev; + } + usleep_range(10000, 20000); + err = reset_control_deassert(priv->rst); + if (err) { + dev_err(priv->dev, "Failed to deassert mac reset (%d)\n", err); + goto err_register_netdev; + } + /* Disable ast2600 problematic HW arbitration */ if (of_device_is_compatible(np, "aspeed,ast2600-mac")) iowrite32(FTGMAC100_TM_DEFAULT, From patchwork Mon Nov 18 06:02:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878127 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA70314EC60; Mon, 18 Nov 2024 06:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909750; cv=none; b=lGj4wc+Vm3n0N1wFZf3sLQdZEAuks1roAWpvXuG+04VLUucijeZn9zrCvMchMMzwp1Csc2m90WrxQW41+61kEDjPrS/J6M7A21vg7Zx6LDd+H7qVFF2EZJ0W1URkRjDE2X/8hNnA0AGlnMcvSGeHHQ8KfWctWPk+5q/i2POgAgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909750; c=relaxed/simple; bh=n2XTKaJCsH8XAHaHQX2Xfs1h9fKItgAa3nZrIKn7oOg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qMS9F2VWlo9OHs25qEjUzS+joM2/wdibg8MxT/JA0K4ubAMebfBVoCXJHYMfinvwqlivvzB7BALFpCD4FrUyXpD5EWSUB69zum+26XakCtbxeywhygepu2+atnVyIaMb+VTubfuBmou2D2tdURauZjargTUVZUb15t49AWep458= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:07 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:07 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 4/7] net: ftgmac100: Add support for AST2700 Date: Mon, 18 Nov 2024 14:02:04 +0800 Message-ID: <20241118060207.141048-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Add comptaible for AST2700 and set dma mask to 64-bit. The ftgmac100 on AST2700 supports 64-bit DMA. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/ftgmac100.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index cae23b712a6d..5b277285666a 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -1884,7 +1884,8 @@ static int ftgmac100_probe(struct platform_device *pdev) np = pdev->dev.of_node; if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || of_device_is_compatible(np, "aspeed,ast2500-mac") || - of_device_is_compatible(np, "aspeed,ast2600-mac"))) { + of_device_is_compatible(np, "aspeed,ast2600-mac") || + of_device_is_compatible(np, "aspeed,ast2700-mac"))) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); priv->is_aspeed = true; @@ -1967,7 +1968,6 @@ static int ftgmac100_probe(struct platform_device *pdev) dev_err(priv->dev, "MII probe failed!\n"); goto err_ncsi_dev; } - } if (priv->is_aspeed) { @@ -1995,9 +1995,18 @@ static int ftgmac100_probe(struct platform_device *pdev) } /* Disable ast2600 problematic HW arbitration */ - if (of_device_is_compatible(np, "aspeed,ast2600-mac")) + if (of_device_is_compatible(np, "aspeed,ast2600-mac") || + of_device_is_compatible(np, "aspeed,ast2700-mac")) iowrite32(FTGMAC100_TM_DEFAULT, priv->base + FTGMAC100_OFFSET_TM); + + if (of_device_is_compatible(np, "aspeed,ast2700-mac")) { + err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (err) { + dev_err(&pdev->dev, "64-bit DMA enable failed\n"); + goto err_register_netdev; + } + } } /* Default ring sizes */ From patchwork Mon Nov 18 06:02:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878128 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C24DE154C07; Mon, 18 Nov 2024 06:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909752; cv=none; b=nxVadYl4pIkWAR4JPqYZe+4LFEO360yBfORS1+KrG6czjxa7vvFGNtWqMBnN2IdxuqJsm4EeFJ5uVw2mu+XP/Fk7c3up/S7hWdfnnVDsSh/cWvbE6jKyqQvQLP5V3H0IqhQzgAf/9z1OyTXTt1wABdgMdZag3ZnKmpQr99A6rNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909752; c=relaxed/simple; bh=cXUa2VmiqARofsljOnRy12kGelXkzAGPZW3H6CPWai4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I6rFKwhpKy+TgkCkVSMEdmn9/j9z6NAxF8u9Kk5/VupKMqTdZGNmvGrgNiicGbHZNS9QfdljXcPaNclqGXXT7m1r42LfPFxeQpMyYbDfFzELfwU9RV26gveX2GybEFF6xSh+RLykhGFeKuLFWaDR9Xd1LzCxzcRpRS/1oxbDlng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:08 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 5/7] net: ftgmac100: add pin strap configuration for AST2700 Date: Mon, 18 Nov 2024 14:02:05 +0800 Message-ID: <20241118060207.141048-6-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org On AST2700, the RMII/RGMII pin strap is configured by setting MAC 0x50 bit 20. Set to 0 is RGMII and set to 1 is RMII. Use compatible property to distinguish different generations for configuration. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/ftgmac100.c | 5 +++++ drivers/net/ethernet/faraday/ftgmac100.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index 5b277285666a..801fbc89ab09 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -323,6 +323,7 @@ static void ftgmac100_init_hw(struct ftgmac100 *priv) static void ftgmac100_start_hw(struct ftgmac100 *priv) { u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); + struct phy_device *phydev = priv->netdev->phydev; /* Keep the original GMAC and FAST bits */ maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE); @@ -351,6 +352,10 @@ static void ftgmac100_start_hw(struct ftgmac100 *priv) if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) maccr |= FTGMAC100_MACCR_RM_VLAN; + if (of_device_is_compatible(priv->dev->of_node, "aspeed,ast2700-mac") && + phydev && phydev->interface == PHY_INTERFACE_MODE_RMII) + maccr |= FTGMAC100_MACCR_RMII_ENABLE; + /* Hit the HW */ iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); } diff --git a/drivers/net/ethernet/faraday/ftgmac100.h b/drivers/net/ethernet/faraday/ftgmac100.h index 4968f6f0bdbc..c87aa7d7f14c 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.h +++ b/drivers/net/ethernet/faraday/ftgmac100.h @@ -166,6 +166,7 @@ #define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16) #define FTGMAC100_MACCR_RX_BROADPKT (1 << 17) #define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18) +#define FTGMAC100_MACCR_RMII_ENABLE (1 << 20) /* defined in ast2700 */ #define FTGMAC100_MACCR_FAST_MODE (1 << 19) #define FTGMAC100_MACCR_SW_RST (1 << 31) From patchwork Mon Nov 18 06:02:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878129 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5FDE1714C0; Mon, 18 Nov 2024 06:02:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909754; cv=none; b=jSeg6R0k09Eyd+lm13GdigWSiFgPG88TTMusml0fBSy+JeFJHQftZtM1YJGoVOzHXWsfsgMH3iZKF4XST975IWvP18LjkQb3atkXt5fYvl5iv+7iUmLWEfFrz8X8ZFrfdRoiShLbw1b7/hwjtB6+YoqRDg64rDJvcchRljhKwHs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909754; c=relaxed/simple; bh=CteD0tS77FWsRmLThWmEcgv6Dxsu7BJ5UokSmVvoN3k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hCwBt2X82KV/0CZtLD4QbmpB5vJQVnU7BMc8PeoP4kMhfGaK9ip0OAXKpif/lfqgYKPczMIPg8X1HQLEE3/KtFIV8O3I2XaFDrIz8EraCk9zF3aDgOEuCKgD6qI5rInschlNEhwpgiQcwCNc3FDcZbSbeqksJgCz53JDXue4s98= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:08 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 6/7] net: ftgmac100: Add 64-bit DMA support for AST2700 Date: Mon, 18 Nov 2024 14:02:06 +0800 Message-ID: <20241118060207.141048-7-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org In 7th generation of Aspeed, the ftgmac100 supports 64-bit DMA operations because it is 64-bit SoC. Add the high address base registers for TX/RX description and add the high address base fields for packet buffer in TX/RX description. These added registers and fields are reserved in older generations and they will not affect older hardware for accessing read/write operations to them. We have verified these patches in older generations, link AST2600. Run iperf3, tftp, ping and dhcp etc. to confirm that it works normally on the new generation and older generation. In TX/RX description, software will reuse the packet buffer address fields to construct the dma information to unmap these dma region. Filling in these high address fields in tx/rxdesc2 is software, and the hardware just use it to do DMA operation and it does not modify these fields. And, in older generation, the software will assign to ZERO to the fields that added in 7th gereration. Because these older SoCs are 32-bit platforms, the high address will always be ZERO. Therefore, avoid using a lot of conditions to set the physical address on old and new generations. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/ftgmac100.c | 35 ++++++++++++++++++------ drivers/net/ethernet/faraday/ftgmac100.h | 9 ++++++ 2 files changed, 35 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index 801fbc89ab09..f3fbe241edb0 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -267,10 +267,12 @@ static void ftgmac100_init_hw(struct ftgmac100 *priv) iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR); /* Setup RX ring buffer base */ - iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR); + iowrite32(lower_32_bits(priv->rxdes_dma), priv->base + FTGMAC100_OFFSET_RXR_BADR); + iowrite32(upper_32_bits(priv->rxdes_dma), priv->base + FTGMAC100_OFFSET_RXR_BADDR_HIGH); /* Setup TX ring buffer base */ - iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); + iowrite32(lower_32_bits(priv->txdes_dma), priv->base + FTGMAC100_OFFSET_NPTXR_BADR); + iowrite32(upper_32_bits(priv->txdes_dma), priv->base + FTGMAC100_OFFSET_TXR_BADDR_HIGH); /* Configure RX buffer size */ iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE), @@ -432,7 +434,9 @@ static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry, priv->rx_skbs[entry] = skb; /* Store DMA address into RX desc */ - rxdes->rxdes3 = cpu_to_le32(map); + rxdes->rxdes2 = cpu_to_le32(FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, + upper_32_bits(map))); + rxdes->rxdes3 = cpu_to_le32(lower_32_bits(map)); /* Ensure the above is ordered vs clearing the OWN bit */ dma_wmb(); @@ -558,7 +562,8 @@ static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) csum_vlan & 0xffff); /* Tear down DMA mapping, do necessary cache management */ - map = le32_to_cpu(rxdes->rxdes3); + map = le32_to_cpu(rxdes->rxdes3) | + ((le32_to_cpu(rxdes->rxdes2) & FTGMAC100_RXDES2_RXBUF_BADR_HI) << 16); #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU) /* When we don't have an iommu, we can save cycles by not @@ -635,9 +640,12 @@ static void ftgmac100_free_tx_packet(struct ftgmac100 *priv, struct ftgmac100_txdes *txdes, u32 ctl_stat) { - dma_addr_t map = le32_to_cpu(txdes->txdes3); + dma_addr_t map; size_t len; + map = le32_to_cpu(txdes->txdes3) | + ((le32_to_cpu(txdes->txdes2) & FTGMAC100_TXDES2_TXBUF_BADR_HI) << 16); + if (ctl_stat & FTGMAC100_TXDES0_FTS) { len = skb_headlen(skb); dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE); @@ -791,7 +799,9 @@ static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, f_ctl_stat |= FTGMAC100_TXDES0_FTS; if (nfrags == 0) f_ctl_stat |= FTGMAC100_TXDES0_LTS; - txdes->txdes3 = cpu_to_le32(map); + txdes->txdes2 = cpu_to_le32(FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, + upper_32_bits((ulong)map))); + txdes->txdes3 = cpu_to_le32(lower_32_bits(map)); txdes->txdes1 = cpu_to_le32(csum_vlan); /* Next descriptor */ @@ -819,7 +829,9 @@ static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, ctl_stat |= FTGMAC100_TXDES0_LTS; txdes->txdes0 = cpu_to_le32(ctl_stat); txdes->txdes1 = 0; - txdes->txdes3 = cpu_to_le32(map); + txdes->txdes2 = cpu_to_le32(FIELD_PREP(FTGMAC100_TXDES2_TXBUF_BADR_HI, + upper_32_bits((ulong)map))); + txdes->txdes3 = cpu_to_le32(lower_32_bits(map)); /* Next one */ pointer = ftgmac100_next_tx_pointer(priv, pointer); @@ -894,7 +906,10 @@ static void ftgmac100_free_buffers(struct ftgmac100 *priv) for (i = 0; i < priv->rx_q_entries; i++) { struct ftgmac100_rxdes *rxdes = &priv->rxdes[i]; struct sk_buff *skb = priv->rx_skbs[i]; - dma_addr_t map = le32_to_cpu(rxdes->rxdes3); + dma_addr_t map; + + map = le32_to_cpu(rxdes->rxdes3) | + ((le32_to_cpu(rxdes->rxdes2) & FTGMAC100_RXDES2_RXBUF_BADR_HI) << 16); if (!skb) continue; @@ -993,7 +1008,9 @@ static void ftgmac100_init_rings(struct ftgmac100 *priv) for (i = 0; i < priv->rx_q_entries; i++) { rxdes = &priv->rxdes[i]; rxdes->rxdes0 = 0; - rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma); + rxdes->rxdes2 = cpu_to_le32(FIELD_PREP(FTGMAC100_RXDES2_RXBUF_BADR_HI, + upper_32_bits(priv->rx_scratch_dma))); + rxdes->rxdes3 = cpu_to_le32(lower_32_bits(priv->rx_scratch_dma)); } /* Mark the end of the ring */ rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask); diff --git a/drivers/net/ethernet/faraday/ftgmac100.h b/drivers/net/ethernet/faraday/ftgmac100.h index c87aa7d7f14c..ac39b864a80c 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.h +++ b/drivers/net/ethernet/faraday/ftgmac100.h @@ -57,6 +57,13 @@ #define FTGMAC100_OFFSET_RX_RUNT 0xc0 #define FTGMAC100_OFFSET_RX_CRCER_FTL 0xc4 #define FTGMAC100_OFFSET_RX_COL_LOST 0xc8 +/* reserved 0xcc - 0x174 */ +#define FTGMAC100_OFFSET_TXR_BADDR_LOW 0x178 /* ast2700 */ +#define FTGMAC100_OFFSET_TXR_BADDR_HIGH 0x17c /* ast2700 */ +#define FTGMAC100_OFFSET_HPTXR_BADDR_LOW 0x180 /* ast2700 */ +#define FTGMAC100_OFFSET_HPTXR_BADDR_HIGH 0x184 /* ast2700 */ +#define FTGMAC100_OFFSET_RXR_BADDR_LOW 0x188 /* ast2700 */ +#define FTGMAC100_OFFSET_RXR_BADDR_HIGH 0x18C /* ast2700 */ /* * Interrupt status register & interrupt enable register @@ -226,6 +233,7 @@ struct ftgmac100_txdes { #define FTGMAC100_TXDES1_TX2FIC (1 << 30) #define FTGMAC100_TXDES1_TXIC (1 << 31) +#define FTGMAC100_TXDES2_TXBUF_BADR_HI GENMASK(18, 16) /* * Receive descriptor, aligned to 16 bytes */ @@ -272,4 +280,5 @@ struct ftgmac100_rxdes { #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26) #define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27) +#define FTGMAC100_RXDES2_RXBUF_BADR_HI GENMASK(18, 16) #endif /* __FTGMAC100_H */ From patchwork Mon Nov 18 06:02:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Chou X-Patchwork-Id: 13878130 X-Patchwork-Delegate: kuba@kernel.org Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C17851885BF; Mon, 18 Nov 2024 06:02:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909756; cv=none; b=ErM7Hv9/E8AN0rgsUdWXEw8LxVSKcJIY4JeHCJmtZaEvoI/m8/INxEKrmnSgqG2Z7eXoDyUIKVcfOMKpRB7ZU+SliM5e/aZvWDzh6bXounjwFiQQg76zVWY9y8ls/uPVA30LH372AFct5/NoOn9SsA5p+yapyHro7j3qBOBQYrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731909756; c=relaxed/simple; bh=BrnSBQjmH8umjO3cZA20Vy89Syvf3RzFwQj/MF+vmIQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QmORFE/4LZnOtYPYvNDOor8xsz8sTLNIg/9n52ZD/MMdOfj/Q7jscrdTbNzKxYKwO++cc21koAyjyAO8SPibvAgg4p5AuPr+2wcXWGgKTNdMevJTzFrI3QQTSx75bfGm1f0dS+BVv88b2MRdXWUaTk248iMBd9bFjQjIk4wdeGs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 18 Nov 2024 14:02:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 18 Nov 2024 14:02:08 +0800 From: Jacky Chou To: , , , , , , , , , , , CC: Subject: [net-next v2 7/7] net: ftgmac100: remove extra newline symbols Date: Mon, 18 Nov 2024 14:02:07 +0800 Message-ID: <20241118060207.141048-8-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241118060207.141048-1-jacky_chou@aspeedtech.com> References: <20241118060207.141048-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Remove some unnecessary newline symbols in code. Signed-off-by: Jacky Chou --- drivers/net/ethernet/faraday/ftgmac100.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index f3fbe241edb0..0ba41c59072a 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -575,7 +575,6 @@ static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); #endif - /* Resplenish rx ring */ ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC); priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer); @@ -1273,7 +1272,6 @@ static int ftgmac100_poll(struct napi_struct *napi, int budget) more = ftgmac100_rx_packet(priv, &work_done); } while (more && work_done < budget); - /* The interrupt is telling us to kick the MAC back to life * after an RX overflow */ @@ -1363,7 +1361,6 @@ static void ftgmac100_reset(struct ftgmac100 *priv) if (priv->mii_bus) mutex_lock(&priv->mii_bus->mdio_lock); - /* Check if the interface is still up */ if (!netif_running(netdev)) goto bail; @@ -1462,7 +1459,6 @@ static void ftgmac100_adjust_link(struct net_device *netdev) if (netdev->phydev) mutex_lock(&netdev->phydev->lock); - } static int ftgmac100_mii_probe(struct net_device *netdev)