From patchwork Tue Nov 19 10:45:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13879707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A08FFD62078 for ; Tue, 19 Nov 2024 10:55:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B24C610E617; Tue, 19 Nov 2024 10:55:02 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PvDcktG/"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A16810E17E; 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19 Nov 2024 02:55:00 -0800 X-CSE-ConnectionGUID: DOwja6mrTGevnLpUuk7tRw== X-CSE-MsgGUID: 6qbKk/8ORGqLt3eJc9tHhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="89937417" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:54:58 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCHv2 1/8] drm/i915/histogram: Define registers for histogram Date: Tue, 19 Nov 2024 16:15:14 +0530 Message-Id: <20241119104521.575377-2-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add the register/bit definitions for global histogram. v2: Intended the register contents, removed unused regs (Jani) Signed-off-by: Arun R Murthy --- .../drm/i915/display/intel_histogram_regs.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_histogram_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h new file mode 100644 index 000000000000..1252b4f339a6 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_HISTOGRAM_REGS_H__ +#define __INTEL_HISTOGRAM_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* GLOBAL_HIST related registers */ +#define _DPST_CTL_A 0x490C0 +#define _DPST_CTL_B 0x491C0 +#define DPST_CTL(pipe) _MMIO_PIPE(pipe, _DPST_CTL_A, _DPST_CTL_B) +#define DPST_CTL_IE_HIST_EN REG_BIT(31) +#define DPST_CTL_RESTORE REG_BIT(28) +#define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) +#define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) +#define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) +#define DPST_CTL_BIN_REG_FUNC_SEL REG_BIT(11) +#define DPST_CTL_BIN_REG_FUNC_TC REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 0) +#define DPST_CTL_BIN_REG_FUNC_IE REG_FIELD_PREP(DPST_CTL_BIN_REG_FUNC_SEL, 1) +#define DPST_CTL_BIN_REG_MASK REG_GENMASK(6, 0) +#define DPST_CTL_BIN_REG_CLEAR REG_FIELD_PREP(DPST_CTL_BIN_REG_MASK, 0) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_2INT_8FRAC REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 1) +#define DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC REG_FIELD_PREP(DPST_CTL_IE_TABLE_VALUE_FORMAT, 0) +#define DPST_CTL_HIST_MODE_YUV REG_FIELD_PREP(DPST_CTL_HIST_MODE, 0) +#define DPST_CTL_HIST_MODE_HSV REG_FIELD_PREP(DPST_CTL_HIST_MODE, 1) + +#define _DPST_GUARD_A 0x490C8 +#define _DPST_GUARD_B 0x491C8 +#define DPST_GUARD(pipe) _MMIO_PIPE(pipe, _DPST_GUARD_A, _DPST_GUARD_B) +#define DPST_GUARD_HIST_INT_EN REG_BIT(31) +#define DPST_GUARD_HIST_EVENT_STATUS REG_BIT(30) +#define DPST_GUARD_INTERRUPT_DELAY_MASK REG_GENMASK(29, 22) +#define DPST_GUARD_INTERRUPT_DELAY(val) REG_FIELD_PREP(DPST_GUARD_INTERRUPT_DELAY_MASK, val) +#define DPST_GUARD_THRESHOLD_GB_MASK REG_GENMASK(21, 0) +#define DPST_GUARD_THRESHOLD_GB(val) REG_FIELD_PREP(DPST_GUARD_THRESHOLD_GB_MASK, val) + +#define _DPST_BIN_A 0x490C4 +#define _DPST_BIN_B 0x491C4 +#define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) +#define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) +#define DPST_BIN_BUSY REG_BIT(31) + +#endif /* __INTEL_HISTOGRAM_REGS_H__ */ From patchwork Tue Nov 19 10:45:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13879708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EC79D62077 for ; Tue, 19 Nov 2024 10:55:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B94310E619; Tue, 19 Nov 2024 10:55:03 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OsLf9Bc8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A12410E617; Tue, 19 Nov 2024 10:55:02 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="89937424" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:00 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCHv4 2/8] drm/i915/histogram: Add support for histogram Date: Tue, 19 Nov 2024 16:15:15 +0530 Message-Id: <20241119104521.575377-3-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Statistics is generated from the image frame that is coming to display and an event is sent to user after reading this histogram data. This statistics/histogram is then shared with the user upon getting a request from user. User can then use this histogram and generate an enhancement factor. This enhancement factor can be multiplied/added with the incoming pixel data frame. v2: forward declaration in header file along with error handling (Jani) v3: Replaced i915 with intel_display (Suraj) v4: Removed dithering enable/disable (Vandita) New patch for histogram register definitions (Suraj) Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/Makefile | 1 + .../drm/i915/display/intel_display_types.h | 2 + .../gpu/drm/i915/display/intel_histogram.c | 195 ++++++++++++++++++ .../gpu/drm/i915/display/intel_histogram.h | 35 ++++ 4 files changed, 233 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_histogram.c create mode 100644 drivers/gpu/drm/i915/display/intel_histogram.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index e465828d748f..97141b4def3b 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -267,6 +267,7 @@ i915-y += \ display/intel_hdcp.o \ display/intel_hdcp_gsc.o \ display/intel_hdcp_gsc_message.o \ + display/intel_histogram.o \ display/intel_hotplug.o \ display/intel_hotplug_irq.o \ display/intel_hti.o \ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 339e4b0f7698..351441efd10a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1414,6 +1414,8 @@ struct intel_crtc { /* for loading single buffered registers during vblank */ struct pm_qos_request vblank_pm_qos; + struct intel_histogram *histogram; + #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; #endif diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c new file mode 100644 index 000000000000..e751977fc6f7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include +#include +#include + +#include "i915_reg.h" +#include "i915_drv.h" +#include "intel_display.h" +#include "intel_histogram_regs.h" +#include "intel_histogram.h" +#include "intel_display_types.h" +#include "intel_de.h" + +#define HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT 300 // 3.0% of the pipe's current pixel count. +#define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000 // Precision factor for threshold guardband. +#define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04 + +struct intel_histogram { + struct intel_crtc *crtc; + struct delayed_work work; + bool enable; + bool can_enable; + u32 bin_data[HISTOGRAM_BIN_COUNT]; +}; + +int intel_histogram_atomic_check(struct intel_crtc *intel_crtc) +{ + struct intel_histogram *histogram = intel_crtc->histogram; + + /* TODO: Restrictions for enabling histogram */ + histogram->can_enable = true; + + return 0; +} + +static int intel_histogram_enable(struct intel_crtc *intel_crtc) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + int pipe = intel_crtc->pipe; + u64 res; + u32 gbandthreshold; + + if (!histogram) + return -EINVAL; + + if (!histogram->can_enable) + return -EINVAL; + + if (histogram->enable) + return 0; + + /* enable histogram, clear DPST_BIN reg and select TC function */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT, + DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV | + DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); + + /* Re-Visit: check if wait for one vblank is required */ + drm_crtc_wait_one_vblank(&intel_crtc->base); + + /* + * TODO: one time programming: Program GuardBand Threshold. + * To be moved to modeset path + */ + res = (intel_crtc->config->hw.adjusted_mode.vtotal * + intel_crtc->config->hw.adjusted_mode.htotal); + + gbandthreshold = (res * HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT) / + HISTOGRAM_GUARDBAND_PRECISION_FACTOR; + + /* Enable histogram interrupt mode */ + intel_de_rmw(display, DPST_GUARD(pipe), + DPST_GUARD_THRESHOLD_GB_MASK | + DPST_GUARD_INTERRUPT_DELAY_MASK | DPST_GUARD_HIST_INT_EN, + DPST_GUARD_THRESHOLD_GB(gbandthreshold) | + DPST_GUARD_INTERRUPT_DELAY(HISTOGRAM_DEFAULT_GUARDBAND_DELAY) | + DPST_GUARD_HIST_INT_EN); + + /* Clear pending interrupts has to be done on separate write */ + intel_de_rmw(display, DPST_GUARD(pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); + + histogram->enable = true; + + return 0; +} + +static void intel_histogram_disable(struct intel_crtc *intel_crtc) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + int pipe = intel_crtc->pipe; + + if (!histogram) + return; + + /* If already disabled return */ + if (histogram->enable) + return; + + /* Clear pending interrupts and disable interrupts */ + intel_de_rmw(display, DPST_GUARD(pipe), + DPST_GUARD_HIST_INT_EN | DPST_GUARD_HIST_EVENT_STATUS, 0); + + /* disable DPST_CTL Histogram mode */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_IE_HIST_EN, 0); + + histogram->enable = false; +} + +int intel_histogram_update(struct intel_crtc *intel_crtc, bool enable) +{ + if (enable) + return intel_histogram_enable(intel_crtc); + + intel_histogram_disable(intel_crtc); + return 0; +} + +int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) +{ + struct intel_histogram *histogram = intel_crtc->histogram; + struct intel_display *display = to_intel_display(intel_crtc); + int pipe = intel_crtc->pipe; + int i = 0; + + if (!histogram) + return -EINVAL; + + if (!histogram->enable) { + drm_err(display->drm, "histogram not enabled"); + return -EINVAL; + } + + if (!data) { + drm_err(display->drm, "enhancement LUT data is NULL"); + return -EINVAL; + } + + /* + * Set DPST_CTL Bin Reg function select to IE + * Set DPST_CTL Bin Register Index to 0 + */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, + DPST_CTL_BIN_REG_FUNC_IE | DPST_CTL_BIN_REG_CLEAR); + + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + intel_de_rmw(display, DPST_BIN(pipe), + DPST_BIN_DATA_MASK, data[i]); + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); + } + + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_ENHANCEMENT_MODE_MASK | DPST_CTL_IE_MODI_TABLE_EN, + DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); + + /* Once IE is applied, change DPST CTL to TC */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_TC); + + return 0; +} + +void intel_histogram_finish(struct intel_crtc *intel_crtc) +{ + struct intel_histogram *histogram = intel_crtc->histogram; + + kfree(histogram); +} + +int intel_histogram_init(struct intel_crtc *intel_crtc) +{ + struct intel_histogram *histogram; + + /* Allocate histogram internal struct */ + histogram = kzalloc(sizeof(*histogram), GFP_KERNEL); + if (!histogram) { + return -ENOMEM; + } + + intel_crtc->histogram = histogram; + histogram->crtc = intel_crtc; + histogram->can_enable = false; + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h new file mode 100644 index 000000000000..9d66724f9c53 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_HISTOGRAM_H__ +#define __INTEL_HISTOGRAM_H__ + +#include + +struct intel_crtc; + +#define HISTOGRAM_BIN_COUNT 32 +#define HISTOGRAM_IET_LENGTH 33 + +enum intel_global_hist_status { + INTEL_HISTOGRAM_ENABLE, + INTEL_HISTOGRAM_DISABLE, +}; + +enum intel_global_histogram { + INTEL_HISTOGRAM, +}; + +enum intel_global_hist_lut { + INTEL_HISTOGRAM_PIXEL_FACTOR, +}; + +int intel_histogram_atomic_check(struct intel_crtc *intel_crtc); +int intel_histogram_update(struct intel_crtc *intel_crtc, bool enable); +int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data); +int intel_histogram_init(struct intel_crtc *intel_crtc); +void intel_histogram_finish(struct intel_crtc *intel_crtc); + +#endif /* __INTEL_HISTOGRAM_H__ */ From patchwork Tue Nov 19 10:45:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13879709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB9A3D6207F for ; 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X-CSE-ConnectionGUID: 53K4fFmeR76W4tJuBYQC2A== X-CSE-MsgGUID: TUGFAGyGT2iLHEdEF2EFfQ== X-IronPort-AV: E=McAfee;i="6700,10204,11260"; a="43075353" X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="43075353" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 02:55:03 -0800 X-CSE-ConnectionGUID: vmNndl28Q12oKseNkYWogQ== X-CSE-MsgGUID: 5HJMqHhtQOeBaTPIvAezaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="89937432" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:02 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy , Suraj Kandpal Subject: [PATCH 3/8] drm/xe: Add histogram support to Xe builds Date: Tue, 19 Nov 2024 16:15:16 +0530 Message-Id: <20241119104521.575377-4-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Histogram added as part of i915/display driver. Adding the same for xe as well. Signed-off-by: Arun R Murthy Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/xe/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index a93e6fcc0ad9..d383b0d35d8e 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -245,6 +245,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_hdcp.o \ i915-display/intel_hdcp_gsc_message.o \ i915-display/intel_hdmi.o \ + i915-display/intel_histogram.o \ i915-display/intel_hotplug.o \ i915-display/intel_hotplug_irq.o \ i915-display/intel_hti.o \ From patchwork Tue Nov 19 10:45:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13879710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E244D6DDFE for ; Tue, 19 Nov 2024 10:55:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C7E910E622; Tue, 19 Nov 2024 10:55:07 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="VwBFZB9D"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id D19ED10E622; Tue, 19 Nov 2024 10:55:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732013705; x=1763549705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wsm/DVtImrWiJDKUQA18Vvy49mDLM2MDojnyM1d9Vf0=; b=VwBFZB9DQmEZ1UF+52l7MRLlKaPOrmXXVOhPzu6/48DbPD/cIu6BJBdb JS5+9OunvboG7L7ztaXd8mxv+jxl7p37mYENHdgB7Mq89rrFsA6AZHflf v3CXiVlp7OzGqnuVm7BRudgq79CBUpPvlYkwCMQfcuqO3+hero0Dd/Nr9 9ZgQF7FlZt7Cfd9K9oadMgqPsKbLaWwjqCPEStgdJBHDjdkkssDQtvFZb UfO7i8CivgS5wJfel/S93K0qBrWeh5EHiTUmioN3HXhAag2QBGnDqYUaN 5fQld/XzOBHQAeb+Qff6dAnQl1xEfkPZyn85Oz8X0NlXzIBBiHK8UoLLq g==; X-CSE-ConnectionGUID: g89+x2CWQkSO7x0vuPPg/Q== X-CSE-MsgGUID: tA4r9shcQ5WOr1s7UNjbCA== X-IronPort-AV: E=McAfee;i="6700,10204,11260"; a="43075355" X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="43075355" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 02:55:05 -0800 X-CSE-ConnectionGUID: /VbV5oVRRO2CV2NrNLROew== X-CSE-MsgGUID: rCL1ay8dSwuVdOTzZ3Kt7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="89937438" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:04 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCHv4 4/8] drm/i915/histogram: histogram interrupt handling Date: Tue, 19 Nov 2024 16:15:17 +0530 Message-Id: <20241119104521.575377-5-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Upon enabling histogram an interrupt is trigerred after the generation of the statistics. This patch registers the histogram interrupt and handles the interrupt. v2: Added intel_crtc backpointer to intel_histogram struct (Jani) Removed histogram_wq and instead use dev_priv->unodered_eq (Jani) v3: Replaced drm_i915_private with intel_display (Suraj) Refactored the histogram read code (Jani) v4: Rebased after addressing comments on patch 1 Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_display_irq.c | 6 +- .../gpu/drm/i915/display/intel_histogram.c | 93 +++++++++++++++++++ .../gpu/drm/i915/display/intel_histogram.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 5 +- 4 files changed, 104 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index f0d3bdb5fc60..cb60c9db4418 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -20,6 +20,7 @@ #include "intel_fdi_regs.h" #include "intel_fifo_underrun.h" #include "intel_gmbus.h" +#include "intel_histogram.h" #include "intel_hotplug_irq.h" #include "intel_pipe_crc_regs.h" #include "intel_pmdemand.h" @@ -1179,6 +1180,9 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) if (iir & GEN8_PIPE_FIFO_UNDERRUN) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); + if (iir & GEN9_PIPE_HISTOGRAM_EVENT) + intel_histogram_irq_handler(display, pipe); + fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv); if (fault_errors) drm_err_ratelimited(&dev_priv->drm, @@ -1764,7 +1768,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) | - GEN8_PIPE_CDCLK_CRC_DONE; + GEN8_PIPE_CDCLK_CRC_DONE | GEN9_PIPE_HISTOGRAM_EVENT; u32 de_pipe_enables; u32 de_port_masked = gen8_de_port_aux_mask(dev_priv); u32 de_port_enables; diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index e751977fc6f7..16f29923ef10 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -18,6 +18,8 @@ #define HISTOGRAM_GUARDBAND_THRESHOLD_DEFAULT 300 // 3.0% of the pipe's current pixel count. #define HISTOGRAM_GUARDBAND_PRECISION_FACTOR 10000 // Precision factor for threshold guardband. #define HISTOGRAM_DEFAULT_GUARDBAND_DELAY 0x04 +#define HISTOGRAM_BIN_READ_RETRY_COUNT 5 +#define HISTOGRAM_BIN_READ_DELAY 2 struct intel_histogram { struct intel_crtc *crtc; @@ -27,6 +29,92 @@ struct intel_histogram { u32 bin_data[HISTOGRAM_BIN_COUNT]; }; +static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) +{ + struct intel_display *display = to_intel_display(intel_crtc); + struct intel_histogram *histogram = intel_crtc->histogram; + u8 index, retry_count; + u32 dpstbin; + + index = 0; + retry_count = 0; + + while (index < HISTOGRAM_BIN_COUNT) { + dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); + if (!(dpstbin & DPST_BIN_BUSY)) { + histogram->bin_data[index] = dpstbin & DPST_BIN_DATA_MASK; + index++; + } else { + /* + * If DPST_BIN busy bit is set, then set the + * DPST_CTL bin reg index to 0 and proceed + * from beginning. + */ + retry_count++; + if (retry_count > HISTOGRAM_BIN_READ_RETRY_COUNT) { + drm_err(display->drm, "Histogram bin read failed with max retry\n"); + return false; + } + /* Add a delay before retrying */ + fsleep(HISTOGRAM_BIN_READ_DELAY); + index = 0; + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_BIN_REG_FUNC_SEL | + DPST_CTL_BIN_REG_MASK, 0); + } + } + return true; +} + +static void intel_histogram_handle_int_work(struct work_struct *work) +{ + struct intel_histogram *histogram = container_of(work, + struct intel_histogram, work.work); + struct intel_crtc *intel_crtc = histogram->crtc; + struct intel_display *display = to_intel_display(intel_crtc); + char *histogram_event[] = {"HISTOGRAM=1", NULL}; + + /* + * TODO: PSR to be exited while reading the Histogram data + * Set DPST_CTL Bin Reg function select to TC + * Set DPST_CTL Bin Register Index to 0 + */ + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + if (intel_histogram_get_data(intel_crtc)) { + /* Notify user for Histogram rediness */ + if (kobject_uevent_env(&display->drm->primary->kdev->kobj, + KOBJ_CHANGE, histogram_event)) + drm_err(display->drm, + "sending HISTOGRAM event failed\n"); + } + + /* Enable histogram interrupt */ + intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, + DPST_GUARD_HIST_INT_EN); + + /* Clear histogram interrupt by setting histogram interrupt status bit*/ + intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), + DPST_GUARD_HIST_EVENT_STATUS, 1); +} + +void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe) +{ + struct intel_crtc *intel_crtc = + to_intel_crtc(drm_crtc_from_index(display->drm, pipe)); + struct intel_histogram *histogram = intel_crtc->histogram; + struct drm_i915_private *i915 = to_i915(intel_crtc->base.dev); + + if (!histogram->enable) { + drm_err(display->drm, + "spurious interrupt, histogram not enabled\n"); + return; + } + + queue_delayed_work(i915->unordered_wq, + &histogram->work, 0); +} + int intel_histogram_atomic_check(struct intel_crtc *intel_crtc) { struct intel_histogram *histogram = intel_crtc->histogram; @@ -113,6 +201,7 @@ static void intel_histogram_disable(struct intel_crtc *intel_crtc) intel_de_rmw(display, DPST_CTL(pipe), DPST_CTL_IE_HIST_EN, 0); + cancel_delayed_work(&histogram->work); histogram->enable = false; } @@ -174,6 +263,7 @@ void intel_histogram_finish(struct intel_crtc *intel_crtc) { struct intel_histogram *histogram = intel_crtc->histogram; + cancel_delayed_work_sync(&histogram->work); kfree(histogram); } @@ -191,5 +281,8 @@ int intel_histogram_init(struct intel_crtc *intel_crtc) histogram->crtc = intel_crtc; histogram->can_enable = false; + INIT_DEFERRABLE_WORK(&histogram->work, + intel_histogram_handle_int_work); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_histogram.h b/drivers/gpu/drm/i915/display/intel_histogram.h index 9d66724f9c53..14f2425e3038 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.h +++ b/drivers/gpu/drm/i915/display/intel_histogram.h @@ -9,6 +9,8 @@ #include struct intel_crtc; +struct intel_display; +enum pipe; #define HISTOGRAM_BIN_COUNT 32 #define HISTOGRAM_IET_LENGTH 33 @@ -27,6 +29,7 @@ enum intel_global_hist_lut { }; int intel_histogram_atomic_check(struct intel_crtc *intel_crtc); +void intel_histogram_irq_handler(struct intel_display *display, enum pipe pipe); int intel_histogram_update(struct intel_crtc *intel_crtc, bool enable); int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data); int intel_histogram_init(struct intel_crtc *intel_crtc); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7a35be56b7ef..40a7c6a77bcc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1605,7 +1605,7 @@ #define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26) #define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25) #define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24) -#define PIPE_DPST_EVENT_ENABLE (1UL << 23) +#define PIPE_HISTOGRAM_EVENT_ENABLE (1UL << 23) #define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22) #define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22) #define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21) @@ -1628,7 +1628,7 @@ #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10) #define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9) #define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8) -#define PIPE_DPST_EVENT_STATUS (1UL << 7) +#define PIPE_HISTOGRAM_EVENT_STATUS (1UL << 7) #define PIPE_A_PSR_STATUS_VLV (1UL << 6) #define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6) #define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5) @@ -2470,6 +2470,7 @@ #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ #define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) +#define GEN9_PIPE_HISTOGRAM_EVENT REG_BIT(12) /* skl+ */ #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */ From patchwork Tue Nov 19 10:45:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13879712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4E9BD44142 for ; Tue, 19 Nov 2024 10:55:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 187B710E628; Tue, 19 Nov 2024 10:55:10 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="k0T95uol"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id EC4B510E627; Tue, 19 Nov 2024 10:55:07 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="89937444" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:06 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCHv5 5/8] drm/i915/histogram: Add crtc properties for global histogram Date: Tue, 19 Nov 2024 16:15:18 +0530 Message-Id: <20241119104521.575377-6-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" CRTC properties have been added for enable/disable histogram, reading the histogram data and writing the IET data. "HISTOGRAM_EN" is the crtc property to enable/disable the global histogram and takes a value 0/1 accordingly. "Histogram" is a crtc property to read the binary histogram data. "Global IET" is a crtc property to write the IET binary LUT data. v2: Read the histogram blob data before sending uevent (Jani) v3: use drm_property_replace_blob_from_id (Vandita) Add substruct for histogram in intel_crtc_state (Jani) v4: Rebased after addressing comments on patch 1 v5: histogram check with old/new crtc_state (Suraj) Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_atomic.c | 5 + drivers/gpu/drm/i915/display/intel_crtc.c | 168 +++++++++++++++++- drivers/gpu/drm/i915/display/intel_crtc.h | 5 + drivers/gpu/drm/i915/display/intel_display.c | 18 ++ .../drm/i915/display/intel_display_types.h | 13 ++ .../gpu/drm/i915/display/intel_histogram.c | 6 + 6 files changed, 214 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 03dc54c802d3..a0d64a20b01e 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -246,6 +246,8 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi); + if (crtc_state->histogram.global_iet) + drm_property_blob_get(crtc_state->histogram.global_iet); /* copy color blobs */ if (crtc_state->hw.degamma_lut) drm_property_blob_get(crtc_state->hw.degamma_lut); @@ -278,6 +280,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->dsb_color_vblank = NULL; crtc_state->dsb_commit = NULL; crtc_state->use_dsb = false; + crtc_state->histogram.histogram_enable_changed = false; return &crtc_state->uapi; } @@ -314,6 +317,8 @@ intel_crtc_destroy_state(struct drm_crtc *crtc, drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank); drm_WARN_ON(crtc->dev, crtc_state->dsb_commit); + if (crtc_state->histogram.global_iet) + drm_property_blob_put(crtc_state->histogram.global_iet); __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); intel_crtc_free_hw_state(crtc_state); if (crtc_state->dp_tunnel_ref.tunnel) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index a2c528d707f4..3be81a5a789b 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "i915_vgpu.h" #include "i9xx_plane.h" @@ -27,6 +28,7 @@ #include "intel_drrs.h" #include "intel_dsi.h" #include "intel_fifo_underrun.h" +#include "intel_histogram.h" #include "intel_pipe_crc.h" #include "intel_psr.h" #include "intel_sprite.h" @@ -210,6 +212,7 @@ static struct intel_crtc *intel_crtc_alloc(void) static void intel_crtc_free(struct intel_crtc *crtc) { intel_crtc_destroy_state(&crtc->base, crtc->base.state); + intel_histogram_finish(crtc); kfree(crtc); } @@ -229,6 +232,66 @@ static int intel_crtc_late_register(struct drm_crtc *crtc) return 0; } +static int intel_crtc_get_property(struct drm_crtc *crtc, + const struct drm_crtc_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_i915_private *i915 = to_i915(crtc->dev); + const struct intel_crtc_state *intel_crtc_state = + to_intel_crtc_state(state); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + + if (property == intel_crtc->histogram_en_property) { + *val = intel_crtc_state->histogram.histogram_enable; + } else if (property == intel_crtc->global_iet_property) { + *val = (intel_crtc_state->histogram.global_iet) ? + intel_crtc_state->histogram.global_iet->base.id : 0; + } else if (property == intel_crtc->histogram_property) { + *val = (intel_crtc_state->histogram.histogram) ? + intel_crtc_state->histogram.histogram->base.id : 0; + } else { + drm_err(&i915->drm, + "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + return -EINVAL; + } + + return 0; +} + +static int intel_crtc_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct drm_property *property, + u64 val) +{ + struct drm_i915_private *i915 = to_i915(crtc->dev); + struct intel_crtc_state *intel_crtc_state = + to_intel_crtc_state(state); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + bool replaced = false; + + if (property == intel_crtc->histogram_en_property) { + intel_crtc_state->histogram.histogram_enable = val; + return 0; + } + + if (property == intel_crtc->global_iet_property) { + drm_property_replace_blob_from_id(crtc->dev, + &intel_crtc_state->histogram.global_iet, + val, + sizeof(uint32_t) * HISTOGRAM_IET_LENGTH, + -1, &replaced); + if (replaced) + intel_crtc_state->histogram.global_iet_changed = true; + return 0; + } + + drm_dbg_atomic(&i915->drm, "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); + return -EINVAL; +} + #define INTEL_CRTC_FUNCS \ .set_config = drm_atomic_helper_set_config, \ .destroy = intel_crtc_destroy, \ @@ -238,7 +301,9 @@ static int intel_crtc_late_register(struct drm_crtc *crtc) .set_crc_source = intel_crtc_set_crc_source, \ .verify_crc_source = intel_crtc_verify_crc_source, \ .get_crc_sources = intel_crtc_get_crc_sources, \ - .late_register = intel_crtc_late_register + .late_register = intel_crtc_late_register, \ + .atomic_set_property = intel_crtc_set_property, \ + .atomic_get_property = intel_crtc_get_property static const struct drm_crtc_funcs bdw_crtc_funcs = { INTEL_CRTC_FUNCS, @@ -383,6 +448,10 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) intel_color_crtc_init(crtc); intel_drrs_crtc_init(crtc); intel_crtc_crc_init(crtc); + intel_histogram_init(crtc); + + /* Initialize crtc properties */ + intel_crtc_add_property(crtc); cpu_latency_qos_add_request(&crtc->vblank_pm_qos, PM_QOS_DEFAULT_VALUE); @@ -737,3 +806,100 @@ void intel_pipe_update_end(struct intel_atomic_state *state, out: intel_psr_unlock(new_crtc_state); } + +static const struct drm_prop_enum_list histogram_enable_names[] = { + { INTEL_HISTOGRAM_DISABLE, "Disable" }, + { INTEL_HISTOGRAM_ENABLE, "Enable" }, +}; + +/** + * intel_attach_histogram_en_property() - add property to enable/disable histogram + * @intel_crtc: pointer to the struct intel_crtc on which the global histogram is to + * be enabled/disabled + * + * "HISTOGRAM_EN" is the crtc propety to enable/disable global histogram + */ +void intel_attach_histogram_en_property(struct intel_crtc *intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + + prop = intel_crtc->histogram_en_property; + if (!prop) { + prop = drm_property_create_enum(dev, 0, + "Histogram_Enable", + histogram_enable_names, + ARRAY_SIZE(histogram_enable_names)); + if (!prop) + return; + + intel_crtc->histogram_en_property = prop; + } + + drm_object_attach_property(&crtc->base, prop, 0); +} + +/** + * intel_attach_global_iet_property() - add property to write Image Enhancement data + * @intel_crtc: pointer to the struct intel_crtc on which global histogram is enabled + * + * "Global IET" is the crtc property to write the Image Enhancement LUT binary data + */ +void intel_attach_global_iet_property(struct intel_crtc *intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + + prop = intel_crtc->global_iet_property; + if (!prop) { + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB | DRM_MODE_PROP_ATOMIC, + "Global IET", 0); + if (!prop) + return; + + intel_crtc->global_iet_property = prop; + } + + drm_object_attach_property(&crtc->base, prop, 0); +} + +/** + * intel_attach_histogram_property() - crtc property to read the histogram. + * @intel_crtc: pointer to the struct intel_crtc on which the global histogram + * was enabled. + * "Global Histogram" is the crtc property to read the binary histogram data. + */ +void intel_attach_histogram_property(struct intel_crtc *intel_crtc) +{ + struct drm_crtc *crtc = &intel_crtc->base; + struct drm_device *dev = crtc->dev; + struct drm_property *prop; + struct drm_property_blob *blob; + + prop = intel_crtc->histogram_property; + if (!prop) { + prop = drm_property_create(dev, DRM_MODE_PROP_BLOB | + DRM_MODE_PROP_ATOMIC | + DRM_MODE_PROP_IMMUTABLE, + "Global Histogram", 0); + if (!prop) + return; + + intel_crtc->histogram_property = prop; + } + blob = drm_property_create_blob(dev, sizeof(uint32_t) * HISTOGRAM_BIN_COUNT, NULL); + intel_crtc->config->histogram.histogram = blob; + + drm_object_attach_property(&crtc->base, prop, blob->base.id); +} + +int intel_crtc_add_property(struct intel_crtc *intel_crtc) +{ + intel_attach_histogram_en_property(intel_crtc); + intel_attach_histogram_property(intel_crtc); + intel_attach_global_iet_property(intel_crtc); + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index de54ae1deedf..4e0a3c43d4f8 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -7,6 +7,7 @@ #define _INTEL_CRTC_H_ #include +#include enum i9xx_plane_id; enum pipe; @@ -59,4 +60,8 @@ void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, enum pipe pipe); void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc); +int intel_crtc_add_property(struct intel_crtc *intel_crtc); +void intel_attach_histogram_en_property(struct intel_crtc *intel_crtc); +void intel_attach_global_iet_property(struct intel_crtc *intel_crtc); +void intel_attach_histogram_property(struct intel_crtc *intel_crtc); #endif diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e790a2de5b3d..0c3008a2d774 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -93,6 +93,7 @@ #include "intel_fifo_underrun.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h" +#include "intel_histogram.h" #include "intel_hotplug.h" #include "intel_link_bw.h" #include "intel_lvds.h" @@ -4607,6 +4608,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (ret) return ret; + /* HISTOGRAM changed */ + if (crtc_state->histogram.histogram_enable_changed) + return intel_histogram_atomic_check(crtc); + return 0; } @@ -6826,6 +6831,11 @@ int intel_atomic_check(struct drm_device *dev, if (new_crtc_state->uapi.scaling_filter != old_crtc_state->uapi.scaling_filter) new_crtc_state->uapi.mode_changed = true; + + /* Histogram updates */ + if (old_crtc_state->histogram.histogram_enable != + new_crtc_state->histogram.histogram_enable) + new_crtc_state->histogram.histogram_enable_changed = true; } intel_vrr_check_modeset(state); @@ -7892,6 +7902,14 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) */ old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit); + + /* Re-Visit: HISTOGRAM related stuff */ + if (new_crtc_state->histogram.histogram_enable_changed) + intel_histogram_update(crtc, + new_crtc_state->histogram.histogram_enable); + if (new_crtc_state->histogram.global_iet_changed) + intel_histogram_set_iet_lut(crtc, + (u32 *)new_crtc_state->histogram.global_iet->data); } /* Underruns don't always raise interrupts, so check manually */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 351441efd10a..300e90998463 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1306,6 +1306,15 @@ struct intel_crtc_state { /* LOBF flag */ bool has_lobf; + + /* Histogram data */ + struct { + int histogram_enable; + struct drm_property_blob *global_iet; + struct drm_property_blob *histogram; + bool global_iet_changed; + bool histogram_enable_changed; + } histogram; }; enum intel_pipe_crc_source { @@ -1415,6 +1424,10 @@ struct intel_crtc { struct pm_qos_request vblank_pm_qos; struct intel_histogram *histogram; + /* HISTOGRAM properties */ + struct drm_property *histogram_en_property; + struct drm_property *global_iet_property; + struct drm_property *histogram_property; #ifdef CONFIG_DEBUG_FS struct intel_pipe_crc pipe_crc; diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index 16f29923ef10..cba65f4260cd 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -82,6 +82,11 @@ static void intel_histogram_handle_int_work(struct work_struct *work) intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); if (intel_histogram_get_data(intel_crtc)) { + drm_property_replace_global_blob(display->drm, + &intel_crtc->config->histogram.histogram, + sizeof(histogram->bin_data), + histogram->bin_data, &intel_crtc->base.base, + intel_crtc->histogram_property); /* Notify user for Histogram rediness */ if (kobject_uevent_env(&display->drm->primary->kdev->kobj, KOBJ_CHANGE, histogram_event)) @@ -203,6 +208,7 @@ static void intel_histogram_disable(struct intel_crtc *intel_crtc) cancel_delayed_work(&histogram->work); histogram->enable = false; + intel_crtc->config->histogram.histogram_enable = false; } int intel_histogram_update(struct intel_crtc *intel_crtc, bool enable) From patchwork Tue Nov 19 10:45:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13879711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 287E9D44143 for ; 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X-CSE-ConnectionGUID: KGDHGPTmQwKCSCvaystrcw== X-CSE-MsgGUID: dVFdr+FxQtqyAwx1A+cE6w== X-IronPort-AV: E=McAfee;i="6700,10204,11260"; a="43075363" X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="43075363" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2024 02:55:09 -0800 X-CSE-ConnectionGUID: 9A3hAa/vQiSmqXDFwbgDwA== X-CSE-MsgGUID: tqMJL6eDQUO2pYKCPpYGkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,165,1728975600"; d="scan'208";a="89937453" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:08 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCH 6/8] drm/i915/histogram: histogram delay counter doesnt reset Date: Tue, 19 Nov 2024 16:15:19 +0530 Message-Id: <20241119104521.575377-7-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The delay counter for histogram does not reset and as a result the histogram bin never gets updated. Workaround would be to use save and restore histogram register. Wa: 14014889975 Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_histogram.c | 17 +++++++++++++++++ .../gpu/drm/i915/display/intel_histogram_regs.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index cba65f4260cd..fdcc64677e96 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -74,6 +74,11 @@ static void intel_histogram_handle_int_work(struct work_struct *work) struct intel_display *display = to_intel_display(intel_crtc); char *histogram_event[] = {"HISTOGRAM=1", NULL}; + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 12, 13)) + intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), + DPST_CTL_RESTORE, 0); + /* * TODO: PSR to be exited while reading the Histogram data * Set DPST_CTL Bin Reg function select to TC @@ -94,6 +99,12 @@ static void intel_histogram_handle_int_work(struct work_struct *work) "sending HISTOGRAM event failed\n"); } + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 12, 13)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_write(display, DPST_CTL(intel_crtc->pipe), intel_de_read(display, + DPST_CTL(intel_crtc->pipe)) | DPST_CTL_RESTORE); + /* Enable histogram interrupt */ intel_de_rmw(display, DPST_GUARD(intel_crtc->pipe), DPST_GUARD_HIST_INT_EN, DPST_GUARD_HIST_INT_EN); @@ -240,6 +251,12 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) return -EINVAL; } + /* Wa: 14014889975 */ + if (IS_DISPLAY_VER(display, 12, 13)) + /* Write the value read from DPST_CTL to DPST_CTL.Interrupt Delay Counter(bit 23:16) */ + intel_de_write(display, DPST_CTL(intel_crtc->pipe), intel_de_read(display, + DPST_CTL(intel_crtc->pipe)) | DPST_CTL_RESTORE); + /* * Set DPST_CTL Bin Reg function select to IE * Set DPST_CTL Bin Register Index to 0 diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index 1252b4f339a6..e50b1448bd40 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -16,6 +16,7 @@ #define DPST_CTL_RESTORE REG_BIT(28) #define DPST_CTL_IE_MODI_TABLE_EN REG_BIT(27) #define DPST_CTL_HIST_MODE REG_BIT(24) +#define DPST_CTL_GUARDBAND_INTERRUPT_DELAY_CNT REG_GENMASK(23, 16) #define DPST_CTL_ENHANCEMENT_MODE_MASK REG_GENMASK(14, 13) #define DPST_CTL_EN_MULTIPLICATIVE REG_FIELD_PREP(DPST_CTL_ENHANCEMENT_MODE_MASK, 2) #define DPST_CTL_IE_TABLE_VALUE_FORMAT REG_BIT(15) From patchwork Tue Nov 19 10:45:20 2024 Content-Type: text/plain; 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d="scan'208";a="89937457" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:10 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCHv4 7/8] drm/i915/histogram: Histogram changes for Display 20+ Date: Tue, 19 Nov 2024 16:15:20 +0530 Message-Id: <20241119104521.575377-8-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In Display 20+, new registers are added for setting index, reading histogram and writing the IET. v2: Removed duplicate code (Jani) v3: Moved histogram core changes to earlier patches (Jani/Suraj) v4: Rebased after addressing comments on patch 1 Signed-off-by: Arun R Murthy --- .../gpu/drm/i915/display/intel_histogram.c | 111 +++++++++++++----- .../drm/i915/display/intel_histogram_regs.h | 25 ++++ 2 files changed, 105 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index fdcc64677e96..beaad9256e01 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -29,6 +29,51 @@ struct intel_histogram { u32 bin_data[HISTOGRAM_BIN_COUNT]; }; +static void set_bin_index_0(struct intel_display *display, enum pipe pipe) +{ + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_IE_INDEX(pipe), + DPST_IE_BIN_INDEX_MASK, DPST_IE_BIN_INDEX(0)); + else + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, + DPST_CTL_BIN_REG_FUNC_IE | DPST_CTL_BIN_REG_CLEAR); +} + +static void write_iet(struct intel_display *display, enum pipe pipe, + u32 *data) +{ + int i; + + if (DISPLAY_VER(display) >= 20) { + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + intel_de_rmw(display, DPST_IE_BIN(pipe), + DPST_IE_BIN_DATA_MASK, + DPST_IE_BIN_DATA(data[i])); + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", + i, data[i]); + } + } else { + for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { + intel_de_rmw(display, DPST_BIN(pipe), + DPST_BIN_DATA_MASK, data[i]); + drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", + i, data[i]); + } + } +} + +static void set_histogram_index_0(struct intel_display *display, enum pipe pipe) +{ + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_HIST_INDEX(pipe), + DPST_HIST_BIN_INDEX_MASK, + DPST_HIST_BIN_INDEX(0)); + else + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); +} + static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) { struct intel_display *display = to_intel_display(intel_crtc); @@ -40,9 +85,13 @@ static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) retry_count = 0; while (index < HISTOGRAM_BIN_COUNT) { - dpstbin = intel_de_read(display, DPST_BIN(intel_crtc->pipe)); + dpstbin = intel_de_read(display, (DISPLAY_VER(display) >= 20 ? + DPST_HIST_BIN(intel_crtc->pipe) : + DPST_BIN(intel_crtc->pipe))); if (!(dpstbin & DPST_BIN_BUSY)) { - histogram->bin_data[index] = dpstbin & DPST_BIN_DATA_MASK; + histogram->bin_data[index] = dpstbin & (DISPLAY_VER(display) >= 20 ? + DPST_HIST_BIN_DATA_MASK : + DPST_BIN_DATA_MASK); index++; } else { /* @@ -58,9 +107,7 @@ static bool intel_histogram_get_data(struct intel_crtc *intel_crtc) /* Add a delay before retrying */ fsleep(HISTOGRAM_BIN_READ_DELAY); index = 0; - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), - DPST_CTL_BIN_REG_FUNC_SEL | - DPST_CTL_BIN_REG_MASK, 0); + set_histogram_index_0(display, intel_crtc->pipe); } } return true; @@ -84,8 +131,8 @@ static void intel_histogram_handle_int_work(struct work_struct *work) * Set DPST_CTL Bin Reg function select to TC * Set DPST_CTL Bin Register Index to 0 */ - intel_de_rmw(display, DPST_CTL(intel_crtc->pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, 0); + set_histogram_index_0(display, intel_crtc->pipe); + if (intel_histogram_get_data(intel_crtc)) { drm_property_replace_global_blob(display->drm, &intel_crtc->config->histogram.histogram, @@ -158,13 +205,20 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc) if (histogram->enable) return 0; - /* enable histogram, clear DPST_BIN reg and select TC function */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | - DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT, - DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | - DPST_CTL_HIST_MODE_HSV | - DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); + if (DISPLAY_VER(display) >= 20) + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE, + DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV); + else + /* enable histogram, clear DPST_BIN reg and select TC function */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE | DPST_CTL_IE_TABLE_VALUE_FORMAT, + DPST_CTL_BIN_REG_FUNC_TC | DPST_CTL_IE_HIST_EN | + DPST_CTL_HIST_MODE_HSV | + DPST_CTL_IE_TABLE_VALUE_FORMAT_1INT_9FRAC); /* Re-Visit: check if wait for one vblank is required */ drm_crtc_wait_one_vblank(&intel_crtc->base); @@ -236,7 +290,6 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) struct intel_histogram *histogram = intel_crtc->histogram; struct intel_display *display = to_intel_display(intel_crtc); int pipe = intel_crtc->pipe; - int i = 0; if (!histogram) return -EINVAL; @@ -261,24 +314,20 @@ int intel_histogram_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data) * Set DPST_CTL Bin Reg function select to IE * Set DPST_CTL Bin Register Index to 0 */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL | DPST_CTL_BIN_REG_MASK, - DPST_CTL_BIN_REG_FUNC_IE | DPST_CTL_BIN_REG_CLEAR); - - for (i = 0; i < HISTOGRAM_IET_LENGTH; i++) { - intel_de_rmw(display, DPST_BIN(pipe), - DPST_BIN_DATA_MASK, data[i]); - drm_dbg_atomic(display->drm, "iet_lut[%d]=%x\n", i, data[i]); + set_bin_index_0(display, pipe); + write_iet(display, pipe, data); + if (DISPLAY_VER(display) < 20) { + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_ENHANCEMENT_MODE_MASK | + DPST_CTL_IE_MODI_TABLE_EN, + DPST_CTL_EN_MULTIPLICATIVE | + DPST_CTL_IE_MODI_TABLE_EN); + /* Once IE is applied, change DPST CTL to TC */ + intel_de_rmw(display, DPST_CTL(pipe), + DPST_CTL_BIN_REG_FUNC_SEL, + DPST_CTL_BIN_REG_FUNC_TC); } - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_ENHANCEMENT_MODE_MASK | DPST_CTL_IE_MODI_TABLE_EN, - DPST_CTL_EN_MULTIPLICATIVE | DPST_CTL_IE_MODI_TABLE_EN); - - /* Once IE is applied, change DPST CTL to TC */ - intel_de_rmw(display, DPST_CTL(pipe), - DPST_CTL_BIN_REG_FUNC_SEL, DPST_CTL_BIN_REG_FUNC_TC); - return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_histogram_regs.h b/drivers/gpu/drm/i915/display/intel_histogram_regs.h index e50b1448bd40..2a52ac9282c1 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram_regs.h +++ b/drivers/gpu/drm/i915/display/intel_histogram_regs.h @@ -44,6 +44,31 @@ #define _DPST_BIN_B 0x491C4 #define DPST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_BIN_A, _DPST_BIN_B) #define DPST_BIN_DATA_MASK REG_GENMASK(23, 0) +#define DPST_BIN_DATA REG_FIELD_PREP(DPST_BIN_DATA_MASK, val) #define DPST_BIN_BUSY REG_BIT(31) +#define _DPST_HIST_INDEX_A 0x490D8 +#define _DPST_HIST_INDEX_B 0x491D8 +#define DPST_HIST_INDEX(pipe) _MMIO_PIPE(pipe, _DPST_HIST_INDEX_A, _DPST_HIST_INDEX_B) +#define DPST_HIST_BIN_INDEX_MASK REG_GENMASK(4, 0) +#define DPST_HIST_BIN_INDEX(val) REG_FIELD_PREP(DPST_HIST_BIN_INDEX_MASK, val) + +#define _DPST_HIST_BIN_A 0x490C4 +#define _DPST_HIST_BIN_B 0x491C4 +#define DPST_HIST_BIN(pipe) _MMIO_PIPE(pipe, _DPST_HIST_BIN_A, _DPST_HIST_BIN_B) +#define DPST_HIST_BIN_BUSY REG_BIT(31) +#define DPST_HIST_BIN_DATA_MASK REG_GENMASK(30, 0) + +#define _DPST_IE_BIN_A 0x490CC +#define _DPST_IE_BIN_B 0x491CC +#define DPST_IE_BIN(pipe) _MMIO_PIPE(pipe, _DPST_IE_BIN_A, _DPST_IE_BIN_B) +#define DPST_IE_BIN_DATA_MASK REG_GENMASK(9, 0) +#define DPST_IE_BIN_DATA(val) REG_FIELD_PREP(DPST_IE_BIN_DATA_MASK, val) + +#define _DPST_IE_INDEX_A 0x490DC +#define _DPST_IE_INDEX_B 0x491DC +#define DPST_IE_INDEX(pipe) _MMIO_PIPE(pipe, _DPST_IE_INDEX_A, _DPST_IE_INDEX_B) +#define DPST_IE_BIN_INDEX_MASK REG_GENMASK(6, 0) +#define DPST_IE_BIN_INDEX(val) REG_FIELD_PREP(DPST_IE_BIN_INDEX_MASK, val) + #endif /* __INTEL_HISTOGRAM_REGS_H__ */ From patchwork Tue Nov 19 10:45:21 2024 Content-Type: text/plain; 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d="scan'208";a="89937461" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa009.fm.intel.com with ESMTP; 19 Nov 2024 02:55:12 -0800 From: Arun R Murthy To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Arun R Murthy Subject: [PATCH 8/8] drm/i915/histogram: Enable pipe dithering Date: Tue, 19 Nov 2024 16:15:21 +0530 Message-Id: <20241119104521.575377-9-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241119104521.575377-1-arun.r.murthy@intel.com> References: <20241119104521.575377-1-arun.r.murthy@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable pipe dithering while enabling histogram to overcome some atrifacts seen on the screen. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_histogram.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_histogram.c b/drivers/gpu/drm/i915/display/intel_histogram.c index beaad9256e01..d3c63da7e491 100644 --- a/drivers/gpu/drm/i915/display/intel_histogram.c +++ b/drivers/gpu/drm/i915/display/intel_histogram.c @@ -29,6 +29,13 @@ struct intel_histogram { u32 bin_data[HISTOGRAM_BIN_COUNT]; }; +static void intel_histogram_enable_dithering(struct intel_display *display, + enum pipe pipe) +{ + intel_de_rmw(display, PIPE_MISC(pipe), PIPE_MISC_DITHER_ENABLE, + PIPE_MISC_DITHER_ENABLE); +} + static void set_bin_index_0(struct intel_display *display, enum pipe pipe) { if (DISPLAY_VER(display) >= 20) @@ -205,6 +212,9 @@ static int intel_histogram_enable(struct intel_crtc *intel_crtc) if (histogram->enable) return 0; + /* Pipe Dithering should be enabled with histogram */ + intel_histogram_enable_dithering(display, pipe); + if (DISPLAY_VER(display) >= 20) intel_de_rmw(display, DPST_CTL(pipe), DPST_CTL_IE_HIST_EN |