From patchwork Tue Nov 19 17:56:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13880390 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F851D26F6 for ; Tue, 19 Nov 2024 17:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732039010; cv=none; b=j94Bz5Fl0F/9SZR1ewzn16TKHbKTcYU/NIe7SSoH5JP2S8n6ZBViIgpgN1gJRmRnmqHjTSSifd73DBEsdJPwhfmyktzsJyddPLV7FR8wujjBVrO7htpEmMTtgJsXuNvRJmPIfZHiiiwuaUAh4Po8JRpTp0VEcGKLkbP9/HMyWPY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732039010; c=relaxed/simple; bh=jYCp8TR7dzoclrZB3zyNwAn2VlLPZL58y51ut7TpNS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oz/uA0Moj5mtkzdS85g2zfunUVSv15PClBT7M8yA/iiyIKGdtkei/NFViEpo2bPGMe1llvMHNqODCP1y8KydxtDU2KqZryfyWyoFG3vK8evXsJPhzIEAC3Ylj2dQ8yfy/0uIBEtH6G4QO5lVcxv73iLIY/77t0BK0wGlUxDg3Zg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=OM0a6WbG; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="OM0a6WbG" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-43161e7bb25so48565305e9.2 for ; Tue, 19 Nov 2024 09:56:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732039006; x=1732643806; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=77Eoli2JKcfvmzeyZfmZcAC8ruXlT3sz4RV/g2sy6qg=; b=OM0a6WbGN4kRpvTMxCmFJtzlXzPxr4CWzs3RGOG6xaoq9KwxyxSYOf/L9GJEuzVCVQ TO9mXD4n0raQOsNIrc40+LmFP7eG9MPxUICMYAYUixfrzeod9THdZ1noKIiKPEmG8KCx 4uFF0IS+7lbYpPZqizWzQIsCfKz/ojKNRawUyRY7hART8wHErAFNOROWyCZCp1sHOGd7 CkhriO2sGSn6RYaDxMKu0q8N9b8iSqhqlr3ZQLUm6FDX3xexJgucFGXKrVMEuKhS9lxt OUeCHdodzZUdnLMsyngGm2ADRplwu0RTSRVpJv0Dqz29wXpyZ+456h3ScktJlnLla6eO B48A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732039006; x=1732643806; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77Eoli2JKcfvmzeyZfmZcAC8ruXlT3sz4RV/g2sy6qg=; b=ND4FtIwGZBkp00iNzqdnWPZW8wGzViLVw9BztwfqoyW7sy4OetYPi4ZgqatoQ+9lRb qmEWe8lW9XhW2/NznMZzh9p4kQQEfxSg/BssSshW2AsBt+Zx9x4cc9iI+nK2O8ltYYYJ GIeDia2Xa6qZnbE3PUY2XtdC5/MdZhNkkam1uDGywVJ4vKctf3hifeoiXgRu5pMXsoDv PvPBrbmqSHYix+hyx5NGWwEh8DyKIFCTB2MzjocDL2wc3fEt3JhHarboXEdL77whFjz8 O6TO7y674DCYnBfoZ+dPptYcHxg0A/kQXwZ1A1Ooe03Cg8ZjBwwvE618hgx3VS+vC3bx 5TLg== X-Forwarded-Encrypted: i=1; AJvYcCXTeM81YYDW6pyQGCvWdkg5up0ScG5dbDCcUBTUAUJLPftSxnel6KSczfN3nIKaFADfgq4+EopkmgfCB9Ew@vger.kernel.org X-Gm-Message-State: AOJu0YzbZ8kdHhGSE6IDHvpBh+Rth0Zsk88q79qmpn8OvYOlAKcAdpLu Sir2jpr4R2kTGlxcws5mWUfYqJPTFnpCLMu7AEFrIPJjXfE9z85Gv7vkUy26On8= X-Google-Smtp-Source: AGHT+IF+Lx7qgtgHAGXdWBZ2QyFola8SI6L7q/xdAwZBh6gOo8f5SFDq9dfDsh2MOCUWBja2J9sv1A== X-Received: by 2002:a05:600c:35c8:b0:430:57f2:bae2 with SMTP id 5b1f17b1804b1-432df791f62mr123906335e9.23.1732039006322; Tue, 19 Nov 2024 09:56:46 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27fe68sm208302275e9.24.2024.11.19.09.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 09:56:45 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:36 +0100 Subject: [PATCH v2 01/11] opp: core: implement dev_pm_opp_get_bw Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-1-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2743; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=jYCp8TR7dzoclrZB3zyNwAn2VlLPZL58y51ut7TpNS0=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFXzHRfip66xeIvRHFGvMRVvKXc3AYGENiBWrVV 6SXuRnuJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRVwAKCRB33NvayMhJ0btFEA CxS/Y3wNk1GVdwKy07e3iKyukBHX2qmyQj6NiA9v2ta5Cz/uPNSaS8Tc32gJESqqwJojuIQlF7k4No DynYwa/WDju9SFUVD1z2cMFL+FCvgSRWaqWCLqR7cGJMvMgyZlMv7zR9WYa7M5wJ/MNzYn91nUDvCa 3//OfR6I3DwpaHFLewgE8rLC9ZB3RLsi4RzMKGsK+IKXcvsbmbPJf+HjgFYMSAc8PW/I2tvWQ/InSy gFFZjfXuvRuLrZWHqT1Gi4rRicne6TRCYpLh4p+BFUxe5KnEGDZg8o3ceWMxwKor4TSaVQQTKsnNWt W/GPR6N7GgzTLxQO6epXobNAUv02VeDNUs66KIY7rUF4qy3sMI6G+aTf9vE0w/g8Fd3u1YaOE3N8o1 nxMzXagpNBdnf9rI110qFeirQMY6ZIp57HyQbmKVK1Vk0R0VM46MLCJdfp5t7I0/NU7NG4If6uYuqK PLKl+kOpOLIq8yaTA/vpvfP5uV0q/3HYIBx/QJAHJIYUtp3PMoCTj+VYqhHaQ6bGrK9iaqwNAorqeO 8VefKlo8kKdPgB6/7ip8k2Y625U0EHqOAdluF4+kCxGD+T0qLHefkoqkSSmaHYSoVHzL7H6hVZZPzq wMkQtSkoWZmSqTLDUZZWPPkznILvnx0n/3S8aVEASCP32GztYdODY1Npp8GQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add and implement the dev_pm_opp_get_bw() to retrieve the OPP's bandwidth in the same way as the dev_pm_opp_get_voltage() helper. Retrieving bandwidth is required in the case of the Adreno GPU where the GPU Management Unit can handle the Bandwidth scaling. The helper can get the peak or average bandwidth for any of the interconnect path. Signed-off-by: Neil Armstrong --- drivers/opp/core.c | 25 +++++++++++++++++++++++++ include/linux/pm_opp.h | 7 +++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 494f8860220d97fc690ebab5ed3b7f5f04f22d73..864b9b99b0129acaffaf45c584c5f34b8bababed 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -106,6 +106,31 @@ static bool assert_single_clk(struct opp_table *opp_table) return !WARN_ON(opp_table->clk_count > 1); } +/** + * dev_pm_opp_get_bw() - Gets the bandwidth corresponding to an opp + * @opp: opp for which voltage has to be returned for + * @peak: select peak or average bandwidth + * @index: bandwidth index + * + * Return: bandwidth in kBps, else return 0 + */ +unsigned long dev_pm_opp_get_bw(struct dev_pm_opp *opp, bool peak, int index) +{ + if (IS_ERR_OR_NULL(opp)) { + pr_err("%s: Invalid parameters\n", __func__); + return 0; + } + + if (index > opp->opp_table->path_count) + return 0; + + if (!opp->bandwidth) + return 0; + + return peak ? opp->bandwidth[index].peak : opp->bandwidth[index].avg; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_get_bw); + /** * dev_pm_opp_get_voltage() - Gets the voltage corresponding to an opp * @opp: opp for which voltage has to be returned for diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 6424692c30b71fca471a1b7d63e018605dd9324b..cd9a257b8e7766d6c8631351a10a845c88414a74 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -106,6 +106,8 @@ struct dev_pm_opp_data { struct opp_table *dev_pm_opp_get_opp_table(struct device *dev); void dev_pm_opp_put_opp_table(struct opp_table *opp_table); +unsigned long dev_pm_opp_get_bw(struct dev_pm_opp *opp, bool peak, int index); + unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp); int dev_pm_opp_get_supplies(struct dev_pm_opp *opp, struct dev_pm_opp_supply *supplies); @@ -209,6 +211,11 @@ static inline struct opp_table *dev_pm_opp_get_opp_table_indexed(struct device * static inline void dev_pm_opp_put_opp_table(struct opp_table *opp_table) {} +static inline unsigned long dev_pm_opp_get_bw(struct dev_pm_opp *opp, bool peak, int index) +{ + return 0; +} + static inline unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp) { return 0; From patchwork Tue Nov 19 17:56:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13880391 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BD2E1D27A0 for ; Tue, 19 Nov 2024 17:56:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732039012; cv=none; b=ZlE7PVwpZYRKHZ85T5KThfVkHYNA5bTOrY/Qa4kaAU0+oeuVXoERBzBRsr0ep9kQwOfJo194hwy9fKhl2DmrydCuE+uxuiWK3lN5jzNngKxCCWNikSGNsLNmqhEpgkiIAxBvgGy2y+pzHE3a2NjulCVh+CKyguwpOeI15KRm9sE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Tue, 19 Nov 2024 09:56:47 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:37 +0100 Subject: [PATCH v2 02/11] drm/msm: adreno: rename quirks that are features Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-2-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10146; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=I07ngYL9Ra1f9h+CP4yA7pd1FaT3h7r+nDReMCfjPD8=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFXvsfG19CuOcSshzsLLrl9P5JiCVdB6NQYWhe+ leGk+k2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRVwAKCRB33NvayMhJ0aqAD/ 9BdW9LZzIoIYl35jeVi9cqCgNGXipLp/slLxcES64BRqOg55WgP8C+mC9AQY0K2p40Vh9Km2z9+QXA FonK8lkCmQXlP8i+4UWolxNN5NeQ0TXbzWqovX6t3o26ubGTzeciItmtaR99LfzgRTNVp6EmpUUFME BYXQRayCUWbyjQfpS62gs+vxwc0AdTaBe18Eh/rfbowEmWxH25J9Btc/LrVIubMwDHtqAz+REGSKui bQG7Gv4+Z2w7m8v35UYqWAqJ7bTl8tFTKYZvo0tGCW7lKu1CZji0ZrIAyzTBhrsZljUUzRpCaAqxCA tSGA3yTLPI8U2MdzektRPFBSEfQU/TlTwSNdFhxdNTAacs1HCHpXnSXATf38I2HsT4OR8f9zynEg/n PZqJ67Lv+iOnZx3ESzZ6ublhomHwSM3zL/Nua3WhLwh7S8jABMdjsAJueh7DuQu1ngJPkiqvBZPDUk aVwH27cPcNRTGmDdMefC5vJGwmcI39uedMVCyJ2TeO3ZA7tENg1xvJgn2anAM5rCSzQx2gKlMNGpnI gFqPqxsD5SzgmFhy397X7jvBeEGSTxdQqGrxyQDGa+YfhDY0OwsvX3dvvGIf8zaLTPPvYf3RgV1NfY rKhaYudkqE+JEI+cQm8DQ5SvLjRBeJWr7QeNLTowDyOSKUUOpJLrSGER9tew== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Half of the current "Quirks" are in fact features, so rename the defines with FEAT instead of QUIRK. They will be moved in a separate bitfield in a second time. No functional changes. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 62 +++++++++++++++--------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++-- 4 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..825c820def315968d508973c8ae40c7c7b646569 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .protect = &a630_protect, @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -864,8 +864,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a620_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -934,8 +934,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -961,8 +961,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -981,8 +981,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .hwcg = a690_hwcg, @@ -1000,8 +1000,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1046,8 +1046,8 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a702_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1355,9 +1355,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "a730_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1377,9 +1377,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1400,9 +1400,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .hwcg = a740_hwcg, @@ -1422,9 +1422,9 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | - ADRENO_QUIRK_HAS_HW_APRIV | - ADRENO_QUIRK_PREEMPTION, + .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + ADRENO_FEAT_HAS_HW_APRIV | + ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .a6xx = &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 019610341df1506c89f44e86b8d1deeb27d61857..2ebd3fac212576a1507e0b6afe2560cd0408dd89 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); adreno_gpu->base.hw_apriv = - !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); + !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) } if ((enable_preemption == 1) || (enable_preemption == -1 && - (config->info->quirks & ADRENO_QUIRK_PREEMPTION))) + (config->info->quirks & ADRENO_FEAT_PREEMPTION))) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); else if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 9ffe91920fbfb4841b28aabec9fbde94539fdd83..09d4569f77528c2a20cabc814668c4c930dd07f1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); + !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e71f420f8b3a8e6cfc52dd1c4d5a63ef3704a07f..8782c25e8a393ec7d9dc23ad450908d039bd08c5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -54,9 +54,10 @@ enum adreno_family { #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) -#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) -#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) -#define ADRENO_QUIRK_PREEMPTION BIT(5) + +#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) +#define ADRENO_FEAT_PREEMPTION BIT(5) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9368; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=0AqIInR9yFwbnFyGS/kSzI6BxCp2Vy864c584EPZMck=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFY6rTJHRArouHKgcaJro3QHLRsFmspb8PEE2bK nanydiiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWAAKCRB33NvayMhJ0fnmD/ 9bX91os7ateFdrwylRii+JOc3pxDsfVPT2napM/PE+NK2gT1KLBFqhCba/Q9w+6flWwIW9DdClnpZl UlwRE95nBjdW0VzPs6b4rL0QMO/PfO9d7um84+sR3NPA9Y1CYSh0iyisTMx943EKiZ7HrBcHqUFRnI sSpp5AJ7HGJE1PHDcCrqMGdvZuE89wX/hnrSfrfkW8WPzOlw4duSBc4rN8yIhieOS9AUXmTxxl0pkC xfL6/K50xTuP4RdLSg6/c7/AtWWV8J8JPH4LO3MUpMVpRMKlhEic1aJmn03Dpu3sQq1wbMaVkiJWUh JvR4vyaZ8xRDP2WZY+ZNefBdZ0xN4WX14lDYFaK5kmknqLdgEbmHkZnQnmL2QKwnK1P+kJkXQ7Xecd okzYpa4VQhmmF1wlpR4Hqt2mICOi7QGYwy23/MmTaT9G6Pyg4Aa3F8pIs5MFQUOOwsNoLJM/uD5M1a 1Pj3aKfNDB9OuL7sXlTApkBYIfZwWaOe8YdjsYG/5XS7btDZsnvGs2yboQi0jQ2ohyO8mwUWMGk83M QU/0BGYjbrbCC5zmiBhAfHGw/RjM5MXaKdubV38zdqAgshmF4NyyqUPyIxWwFMhRLNip0Om6weZA1K GeumTb54WHO3Akqjc0sSKfaXfwmXmciyu5/fuJkNG3MNJpBfrEn8nKKKYfwA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Now the features defines have the right name, introduce a features bitfield and move the features defines in it, fixing all code checking for them. No functional changes intended. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 34 +++++++++++++++--------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +++--- 4 files changed, 24 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 825c820def315968d508973c8ae40c7c7b646569..93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -743,7 +743,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -769,7 +769,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { .protect = &a630_protect, @@ -839,7 +839,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -864,7 +864,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a620_zap.mbn", @@ -892,7 +892,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -911,7 +911,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -934,7 +934,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", @@ -961,7 +961,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", @@ -981,7 +981,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .a6xx = &(const struct a6xx_info) { @@ -1000,7 +1000,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mbn", @@ -1028,7 +1028,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT, + .features = ADRENO_FEAT_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1046,7 +1046,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", @@ -1331,7 +1331,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_HW_APRIV, + .features = ADRENO_FEAT_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a702_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1355,7 +1355,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, @@ -1377,7 +1377,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, @@ -1400,7 +1400,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, @@ -1422,7 +1422,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = 3 * SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_FEAT_HAS_CACHED_COHERENT | + .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | ADRENO_FEAT_PREEMPTION, .init = a6xx_gpu_init, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 2ebd3fac212576a1507e0b6afe2560cd0408dd89..654d0cff421f15901cd4bf33b41e70004634ec75 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2478,7 +2478,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); adreno_gpu->base.hw_apriv = - !!(config->info->quirks & ADRENO_FEAT_HAS_HW_APRIV); + !!(config->info->features & ADRENO_FEAT_HAS_HW_APRIV); /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || @@ -2495,7 +2495,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) } if ((enable_preemption == 1) || (enable_preemption == -1 && - (config->info->quirks & ADRENO_FEAT_PREEMPTION))) + (config->info->features & ADRENO_FEAT_PREEMPTION))) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4); else if (is_a7xx) ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 09d4569f77528c2a20cabc814668c4c930dd07f1..11a228472fa0cef3b6e4e21a366470fbbc3ea8df 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -207,7 +207,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = - !!(info->quirks & ADRENO_FEAT_HAS_CACHED_COHERENT); + !!(info->features & ADRENO_FEAT_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 8782c25e8a393ec7d9dc23ad450908d039bd08c5..4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,9 +55,9 @@ enum adreno_family { #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) -#define ADRENO_FEAT_HAS_HW_APRIV BIT(3) -#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(4) -#define ADRENO_FEAT_PREEMPTION BIT(5) +#define ADRENO_FEAT_HAS_HW_APRIV BIT(0) +#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) +#define ADRENO_FEAT_PREEMPTION BIT(2) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. @@ -98,6 +98,7 @@ struct adreno_info { uint32_t revn; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; + u64 features; u64 quirks; struct msm_gpu *(*init)(struct drm_device *dev); const char *zapfw; From patchwork Tue Nov 19 17:56:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13880393 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1306; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=n7AjLch9953BuDVwIlWrOSl9FaavH+aib8ySJTyoxTo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFYMO7EyC4T4TF/e7BGzAu0nBPzu5e8pKgbvKGl RBFXRhKJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWAAKCRB33NvayMhJ0fSpEA Cw3SShkE7iSaedv/beI78snfZ1LAHYcu9+c9tv42VvGDREihcCBoe3XopqonDAGrx1AXztqeSu5Pz+ 5wrYOc2TTfOSQO//QRHjDNpNPBO9tmrrnf3+aXTMDGlYNtcWpfvY21x7XjKdj4sc4wLzDYVZsehNec cdqKihmWrxbMJEQBWI7vOyDI62OVapFRm589i2jwA8etBaC62AV3fPT2qKkc+0saKe61lgjJLamTWu Uf6uBXvV2n9/ke2JNjgyAI13yG8Z9lumnXayLGTUU3rGmHIFYxev82ZAZpLQDtEeve7hZPQQnqz/c1 YGdOqxcxAK+w0edPQZiqakrPS2TgBCDC2WJwsOUrqmaowXOzhjTNH89iMJksIcc90rPQtSszCK3vib cS4+tweYJJhV0MWolbL0JMFJvaRoPLmCAuiIWY1j8M51AQgS8tn2cgivPmavajsqQhvluHFVrAEI4f 3I4o29J5dozRXWuvbuvyQEWQI6q05TpnAqq6WjYE0PW99ajcvEUXT+oU0+mMCbLl+P/sRYsAD3Niem 2IRU5SkNbdoDSWwa8XwxtIJzE3G+Yk7M33gUfGvqo4CQUhEq+M4c2FCTjTv8DyzmpYg5u8xHS7Fn/y nlVYppeOmQ0H3paslgGx62JPgrw+73piVyUILInwYQXVyoRZuDwY7wfzdTtg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core vote for the interconnect ddr path. While scaling via the interconnect path was sufficient, newer GPUs like the A750 requires specific vote paremeters and bandwidth to achieve full functionality. While the feature will require some data in a6xx_info, it's safer to only enable tested platforms with this flag first. Add a new feature enabling DDR Bandwidth vote via GMU. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -58,6 +58,7 @@ enum adreno_family { #define ADRENO_FEAT_HAS_HW_APRIV BIT(0) #define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1) #define ADRENO_FEAT_PREEMPTION BIT(2) +#define ADRENO_FEAT_GMU_BW_VOTE BIT(3) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8513; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=HBRDsNw9Gt6y+bhLpW3yKrF6dqOXzdwZOiJPQuFbYDc=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFZciGIWjU99nYrv3NSOQ4FRH3hxQiDaFs6246i RlQfCXiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWQAKCRB33NvayMhJ0XaXD/ 9sxJ6sLTAV3AQgvaxK3VtgOkK+SIdgj3aSi5wz27qL4RyV6y8qbCEQDyjmgugrb4QYpZjFjKGoMHgZ YQuzel7XHdq1WQpRC08mWPYYIBqBbIBiRK6LxAJfxS+MpzMaXOv5eljv9M8OvC1eBO4fTpivZVdfBI ckMBHf5ni7J/VHBtjiBMU9p8oTx6MjAlBAemWJ5+q0BJxRUrqsOcqNRxnZRR5gpBj6C9/4SpTMx2kd NHxi14GAmYbOAxGEc8I1iN6v1tmuplGrOoohUd7ANZ2Dp1jYGB8/SKG5cvdTo6JoLZhsadzl/ySp6F KrC0UVqEe+g2tle59g2P7UPPlVr+mHXvEROL8olESrRZuRkDRKoU/W01Aopj2nuaRBiAA0/U95TnZ0 SGxr8hJufYk7h4Z/IdRJwMk24t1126U9Vw5cQJRrJMWPqA+Y9XT+aVxCgBfPr/GpE3Q4YN/MKDRwTH diwf21IVK9cJjkEY6Nu0Z4XcF0LL6cXiilJekN5OjXLdJ4iACvdu5OUAbkbW9rA+lSABkd904VlmbV VNALPpQEHDOXe0sNN6Ih0aWXG0wtPCYSJQJbiabzo39J5LH+7sHwg3ATv2NlxcmNZgKF7GRufL9CPr 3OgJ4F7mJPn/TG2j64jwiI7kN2QrkYKpPQFskVaySRgn9sSKHHecU1LLZ0cg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GMU Management Unit (GMU) can also scale DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. In order to calculate vote values used by the GPU Management Unit (GMU), we need to parse all the possible OPP Bandwidths and create a vote value to be sent to the appropriate Bus Control Modules (BCMs) declared in the GPU info struct. The vote array will then be used to dynamically generate the GMU bw_table sent during the GMU power-up. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 153 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 14 ++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 3 files changed, 168 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 14db7376c712d19446b38152e480bd5a1e0a5198..f6814d92a4edb29ba8a34a34aabb8b2324e9c6a4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "a6xx_gpu.h" @@ -1287,6 +1288,109 @@ static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) return 0; } +/** + * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) + * @unit: divisor used to convert bytes/sec bw value to an RPMh msg + * @width: multiplier used to convert bytes/sec bw value to an RPMh msg + * @vcd: virtual clock domain that this bcm belongs to + * @reserved: reserved field + */ +struct bcm_db { + __le32 unit; + __le16 width; + u8 vcd; + u8 reserved; +}; + +static u64 bcm_div(u64 num, u32 base) +{ + /* Ensure that small votes aren't lost. */ + if (num && num < base) + return 1; + + do_div(num, base); + + return num; +} + +static int a6xx_gmu_rpmh_bw_votes_init(const struct a6xx_info *info, + struct a6xx_gmu *gmu) +{ + const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 }; + unsigned int bcm_index, bw_index; + + /* Retrieve BCM data from cmd-db */ + for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { + size_t count; + + /* Skip unconfigured BCM */ + if (!info->bcm[bcm_index].name) + continue; + + bcm_data[bcm_index] = cmd_db_read_aux_data( + info->bcm[bcm_index].name, + &count); + if (IS_ERR(bcm_data[bcm_index])) + return PTR_ERR(bcm_data[bcm_index]); + + if (!count) + return -EINVAL; + } + + /* Generate BCM votes values for each bandwidth & BCM */ + for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) { + u32 *data = gmu->gpu_bw_votes[bw_index]; + u32 bw = gmu->gpu_bw_table[bw_index]; + + /* Calculations loosely copied from bcm_aggregate() & tcs_cmd_gen() */ + for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { + bool commit = false; + u64 peak, vote; + u16 width; + u32 unit; + + /* Skip unconfigured BCM */ + if (!info->bcm[bcm_index].name || !bcm_data[bcm_index]) + continue; + + if (bcm_index == GMU_MAX_BCMS - 1 || + (bcm_data[bcm_index + 1] && + bcm_data[bcm_index]->vcd != bcm_data[bcm_index + 1]->vcd)) + commit = true; + + if (!bw) { + data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0); + continue; + } + + if (info->bcm[bcm_index].fixed) { + u32 perfmode = 0; + + if (bw >= info->bcm[bcm_index].perfmode_bw) + perfmode = info->bcm[bcm_index].perfmode; + + data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode); + continue; + } + + /* Multiply the bandwidth by the width of the connection */ + width = le16_to_cpu(bcm_data[bcm_index]->width); + peak = bcm_div((u64)bw * width, info->bcm[bcm_index].buswidth); + + /* Input bandwidth value is in KBps, scale the value to BCM unit */ + unit = le32_to_cpu(bcm_data[bcm_index]->unit); + vote = bcm_div(peak * 1000ULL, unit); + + if (vote > BCM_TCS_CMD_VOTE_MASK) + vote = BCM_TCS_CMD_VOTE_MASK; + + data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote); + } + } + + return 0; +} + /* Return the 'arc-level' for the given frequency */ static unsigned int a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq) @@ -1390,12 +1494,15 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, * The GMU votes with the RPMh for itself and on behalf of the GPU but we need * to construct the list of votes on the CPU and send it over. Query the RPMh * voltage levels and build the votes + * The GMU can also vote for DDR interconnects, use the OPP bandwidth entries + * and BCM parameters to build the votes. */ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; struct msm_gpu *gpu = &adreno_gpu->base; int ret; @@ -1407,6 +1514,10 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); + /* Build the interconnect votes */ + if (adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) + ret |= a6xx_gmu_rpmh_bw_votes_init(info, gmu); + return ret; } @@ -1442,6 +1553,38 @@ static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, return index; } +static int a6xx_gmu_build_bw_table(struct device *dev, unsigned long *bandwidths, + u32 size) +{ + int count = dev_pm_opp_get_opp_count(dev); + struct dev_pm_opp *opp; + int i, index = 0; + unsigned int bandwidth = 1; + + /* + * The OPP table doesn't contain the "off" bandwidth level so we need to + * add 1 to the table size to account for it + */ + + if (WARN(count + 1 > size, + "The GMU bandwidth table is being truncated\n")) + count = size - 1; + + /* Set the "off" bandwidth */ + bandwidths[index++] = 0; + + for (i = 0; i < count; i++) { + opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0); + if (IS_ERR(opp)) + break; + + dev_pm_opp_put(opp); + bandwidths[index++] = bandwidth++; + } + + return index; +} + static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); @@ -1472,6 +1615,16 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) gmu->current_perf_index = gmu->nr_gpu_freqs - 1; + /* + * The GMU also handles GPU Interconnect Votes so build a list + * of DDR bandwidths from the GPU OPP table + */ + if (adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) + gmu->nr_gpu_bws = a6xx_gmu_build_bw_table(&gpu->pdev->dev, + gmu->gpu_bw_table, ARRAY_SIZE(gmu->gpu_bw_table)); + + gmu->current_perf_index = gmu->nr_gpu_freqs - 1; + /* Build the list of RPMh votes that we'll send to the GMU */ return a6xx_gmu_rpmh_votes_init(gmu); } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index b4a79f88ccf45cfe651c86d2a9da39541c5772b3..03603eadc0f9ed866899c95e99f333a511ebc3c1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -19,6 +19,16 @@ struct a6xx_gmu_bo { u64 iova; }; +#define GMU_MAX_BCMS 3 + +struct a6xx_bcm { + char *name; + unsigned int buswidth; + bool fixed; + unsigned int perfmode; + unsigned int perfmode_bw; +}; + /* * These define the different GMU wake up options - these define how both the * CPU and the GMU bring up the hardware @@ -82,6 +92,10 @@ struct a6xx_gmu { unsigned long gpu_freqs[16]; u32 gx_arc_votes[16]; + int nr_gpu_bws; + unsigned long gpu_bw_table[16]; + u32 gpu_bw_votes[16][GMU_MAX_BCMS]; + int nr_gmu_freqs; unsigned long gmu_freqs[4]; u32 cx_arc_votes[4]; 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Tue, 19 Nov 2024 09:56:52 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27fe68sm208302275e9.24.2024.11.19.09.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 09:56:52 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:41 +0100 Subject: [PATCH v2 06/11] drm/msm: adreno: dynamically generate GMU bw table Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-6-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2755; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=8YGZ9WKDiwlY9CXdycHEn+g53UomsCDyNV7cpV/GbpI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFZkDlMgucCKOVG3spwNDcQZ0ZydMSrArihhW/Y vFgoe8OJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWQAKCRB33NvayMhJ0bjFD/ 9Mm8Si6vY3yrr2jLQmK9hIOxIo7VQGaygEeTkajDIJBFkFAFPQXGV5BNeb7ZEWXTXcNYlDIqs0qRb1 JOF/h1vPRq3pDdOEnG5JcF45su6IX9V935mkZDOhynF9D4dfaVySkMl8vSYI8PbBxLQSzj/vLcVd8o YGiWIm+8ZzZ5yT5UxZLeEeyjrBP5tOcyw6EmgiLf0snPQYsDadgXnpDO3+E71tmdcUHMsVGwJsEqTr g0uYhy3CsZK9eGEcyH3BvnjPQg2xP4ln6pEXC49Et1S9kpcpRzlZ6NPvBK5Li+TNX3GCL3eg3/ciUw 0x4TkUHAtlTQl2K7c/Ucm6rhadLnn8y86WWnlVepGCHZx1K3upgvczZbs/6mtob5xrp8xgfJWH/vbB BmTy+I6vhg+a9nle+Scw+KpcTF2L7UMam1Kiu4vKcXiniSHVO3GMwAp4845Mpc4PrwYiIofLS/0mUX zdMoAGfH8G7hzfQ/B4YNsXQAZ3cIuvC5XESP35Whkjtd635QbmeB6XFkhUrkofR6A8bY81WRuWltqP XuTJ4hq777J3vSZB/xSkBbj6T40vviF+j+CiwcJOLnja5qAYzgbmbi1jNRDstLj68//tK3vEU/gKW6 menmwvCUhLMg4vKU3j5zhTxgQRw3ZlwdCmTDWchXJnGvzssONP8cVOc1nQ/g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GPU Management Unit (GMU) can also scale the ddr bandwidth along the frequency and power domain level, but for now we statically fill the bw_table with values from the downstream driver. Only the first entry is used, which is a disable vote, so we currently rely on scaling via the linux interconnect paths. Let's dynamically generate the bw_table with the vote values previously calculated from the OPPs. Those entried will then be used by the GMU when passing the appropriate bandwidth level while voting for a gpu frequency. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 39 ++++++++++++++++++++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index cb8844ed46b29c4569d05eb7a24f7b27e173190f..0c8aa9f8cabe1d9cb20445a4274b728236a99fad 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -621,6 +621,36 @@ static void a740_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) msg->cnoc_cmds_data[1][0] = 0x60000001; } +static void a740_generate_bw_table(struct adreno_gpu *adreno_gpu, struct a6xx_gmu *gmu, + struct a6xx_hfi_msg_bw_table *msg) +{ + const struct a6xx_info *info = adreno_gpu->info->a6xx; + unsigned int i, j; + + msg->ddr_wait_bitmask = 0x7; + + for (i = 0; i < 3; i++) { + if (!info->bcm[i].name) + break; + msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcm[i].name); + } + msg->ddr_cmds_num = i; + + for (i = 0; i < gmu->nr_gpu_bws; ++i) + for (j = 0; j < msg->ddr_cmds_num; j++) + msg->ddr_cmds_data[i][j] = gmu->gpu_bw_votes[i][j]; + msg->bw_level_num = gmu->nr_gpu_bws; + + /* TODO also generate CNOC commands */ + + msg->cnoc_cmds_num = 1; + msg->cnoc_wait_bitmask = 0x1; + + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[1][0] = 0x60000001; +} + static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ @@ -690,9 +720,12 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) a690_build_bw_table(msg); else if (adreno_is_a730(adreno_gpu)) a730_build_bw_table(msg); - else if (adreno_is_a740_family(adreno_gpu)) - a740_build_bw_table(msg); - else + else if (adreno_is_a740_family(adreno_gpu)) { + if ((adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) && gmu->nr_gpu_bws) + a740_generate_bw_table(adreno_gpu, gmu, msg); + else + a740_build_bw_table(msg); + } else a6xx_build_bw_table(msg); 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4053; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=c7fkpIfYHl8TuODfNcVaZw49taK0J/XE1pU9iIsovJs=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFasiiUa76I7e45RA1Hi7Q21xQOjgCMFbyW66oO L9CsJWiJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWgAKCRB33NvayMhJ0U1ID/ 9TgCEMSBNEoWaJNnj7wI7ZeW8V0mFeGvJuZbG+m0iDktGvAgf48GWNp32l2ez1Ae2hlcTT/ipCedq+ KX3gG7jEthsl4UJK54VwuKNobkGuTWAUOGnEUJ4dmS48nGKzq1lGLAedYW09jAlP/VL8eU5DflyZ88 mVuTFgv1sUkArErC/hYLXIAJvS4XHrKWBlxjAOwD5ntq+/1QTN+DWdpeOcAx+DT/7/FKXAZGOntZoa TC+8v2VeBUaKdlkycdGOiW/ja5YhxzgyvGwA0GTu8Lx+/sAG9MPknUzrX/NX0odjFilaJwYaeD91QJ VSvWijltOjhC9zG7xwisx67iNp7n2zpYTWj+/E82teMa+Kg2cY3l1coBqf6E6Hz4u0Y9qOnzgkMc3S cY8X+Yfrz5ZoBB1fSYLbczhJC42JdHDn9Qxus6lDZaIXcPdhDJz+E/x0iQ/WfIx57FEFpAaIxf/8iW WZFDvnqaOf82kMr1Z00A+fQuaEkstUEs106qjUmzVtj5Z5snqph8WXr4UrlRNe8lHGga4/xO/tJHAZ prZ4OHjmO8VDlSxaLHXk18wbA5vNavwpG4twgbMpkI4wMLCZB0D65lNfxe6cj7zFwIYIkSogwJx9zO Mai061ny1cuNbLBBAjIf02c91+tWBreDcn5/cDa528U2c/yNNf/UIFtcyPhg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GMU Management Unit (GMU) can also scale the DDR Bandwidth along the Frequency and Power Domain level, until now we left the OPP core scale the OPP bandwidth via the interconnect path. In order to enable bandwidth voting via the GPU Management Unit (GMU), when an opp is set by devfreq we also look for the corresponding bandwidth index in the previously generated bw_table and pass this value along the frequency index to the GMU. Since we now vote for all resources via the GMU, setting the OPP is no more needed, so we can completely skip calling dev_pm_opp_set_opp() in this situation. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 17 +++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 6 +++--- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index f6814d92a4edb29ba8a34a34aabb8b2324e9c6a4..dc2d0035544e7848e5c4ea27f1ea9a191f9c4991 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -113,6 +113,7 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; u32 perf_index; + u32 bw_index = 0; unsigned long gpu_freq; int ret = 0; @@ -125,6 +126,16 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, if (gpu_freq == gmu->gpu_freqs[perf_index]) break; + /* If enabled, find the corresponding DDR bandwidth index */ + if ((adreno_gpu->info->features & ADRENO_FEAT_GMU_BW_VOTE) && gmu->nr_gpu_bws) { + unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); + + for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { + if (bw == gmu->gpu_bw_table[bw_index]) + break; + } + } + gmu->current_perf_index = perf_index; gmu->freq = gmu->gpu_freqs[perf_index]; @@ -140,8 +151,10 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, return; if (!gmu->legacy) { - a6xx_hfi_set_freq(gmu, perf_index); - dev_pm_opp_set_opp(&gpu->pdev->dev, opp); + a6xx_hfi_set_freq(gmu, perf_index, bw_index); + /* With Bandwidth voting, we now vote for all resources, so skip OPP set */ + if (!bw_index) + dev_pm_opp_set_opp(&gpu->pdev->dev, opp); return; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 03603eadc0f9ed866899c95e99f333a511ebc3c1..a42cdd0261872a08033a368af1434492c075b3fd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -207,7 +207,7 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu); int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); void a6xx_hfi_stop(struct a6xx_gmu *gmu); int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); -int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); +int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int perf_index, int bw_index); bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index 0c8aa9f8cabe1d9cb20445a4274b728236a99fad..2d8e144e3453b30e7d3a22c9252e516763c39b83 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -759,13 +759,13 @@ static int a6xx_hfi_send_core_fw_start(struct a6xx_gmu *gmu) sizeof(msg), NULL, 0); } -int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index) +int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int freq_index, int bw_index) { struct a6xx_hfi_gx_bw_perf_vote_cmd msg = { 0 }; msg.ack_type = 1; /* blocking */ - msg.freq = index; - msg.bw = 0; /* TODO: bus scaling */ + msg.freq = freq_index; + msg.bw = bw_index; return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_GX_BW_PERF_VOTE, &msg, sizeof(msg), NULL, 0); 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1851; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=oXkj1C6Jx8yUMHy3C9MjrWlRZXnbo4AjWBLbi4B14uI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFaHpmsc8d0QhqhvhKQzuhIHbOW/nweLHVI4J4K yOvheo2JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWgAKCRB33NvayMhJ0a6wD/ wMgXLGer+Gwmpc2QXN/wUIVfxGxIJekwSowXEGKXdUnynbp8xruE7XqMXPRugx8J70wKaRkPVIDBAq YlvzhmgygfqOd99bB4cxv/m+LhYaB/sqeIpGxXxIFg9JUTmOww07+g5wSg8uS6g4x/6m/AE1QW6inw 6Vi/BiDDegOqKGTC04oXy/3wuJGJkjx/hLAsfoQnmKO6rNLc7nlepQN+a86EgENOC9uP5dWo51XxiH Qcw0D+UEhPz7Sywxlxx7/x7hYR42vAQ9XIZE6df2tJtl+qSn5RqVSdnuk+VpVOZeN5GLzycCdaAQZZ +BpzDDGet1cB9RPKolF1+3rtxHRPKGaf44xlgrXdngpLlCDX3feji1t2DqUyVLy26qj+wBGcF3yC62 5zcZUam9IXez+ZA6dmDUpWQ8bDHDUN8pH/tnJQ5NxqC5H2AUPhl6X7UgH1GVhn4wBI6oACdLFbfRLS cMR6fJTddxi7KPzvhhZo+GYeEA1oP/PnjjCSPMzGW/h+tSi/RVAGm5s/NBp+sO//57MwUqIIcmMYhO 74L35njgwh0bb2h+YhE8Sbonu83uTFPWOvTov/B+Qp8FRQOiZkHZnmAgPO6L5jvzvJUZhLOTrl/Tda bmMyLXaUOA/pQYp//Bky30nqQHwALOEFRZJO8MR5XVxt+ciFfsVHs8vCb7uQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE When requesting a DDR bandwidth level along a GPU frequency level via the GMU, we can also specify the bus bandwidth usage in a 16bit quantitized value. For now simply request the maximum bus usage. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 +++++++++++ drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index dc2d0035544e7848e5c4ea27f1ea9a191f9c4991..36c0f67fd8e109aabf09a0804bacbed3593c39d7 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -134,6 +134,17 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, if (bw == gmu->gpu_bw_table[bw_index]) break; } + + if (bw_index) { + /* + * Append AB vote to the maximum bus usage. + * AB represents a quantitized 16bit value of the + * max ddr bandwidth we could use, let's simply + * request the maximum for now. + */ + bw_index |= AB_VOTE(MAX_AB_VOTE); + bw_index |= AB_VOTE_ENABLE; + } } gmu->current_perf_index = perf_index; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h index 528110169398f69f16443a29a1594d19c36fb595..52ba4a07d7b9a709289acd244a751ace9bdaab5d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -173,6 +173,11 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd { u32 bw; }; +#define AB_VOTE_MASK GENMASK(31, 16) +#define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1) +#define AB_VOTE(vote) FIELD_PREP(AB_VOTE_MASK, (vote)) +#define AB_VOTE_ENABLE BIT(8) + #define HFI_H2F_MSG_PREPARE_SLUMBER 33 struct a6xx_hfi_prep_slumber_cmd { From patchwork Tue Nov 19 17:56:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13880397 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ACF81D86CE for ; Tue, 19 Nov 2024 17:56:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732039020; cv=none; b=PgtBs1kZYnwi+omN4GFPhr7mdrsHBe9HvkbdxjNV+HaJnLYWDF8fpKiFx8IwwdPdcc4bDMfnxvaYbYAAuMUxke2kaLqWoWmHlqKHFEzqjcIYZgxJ5oaa1dLtAY+J9BMpCr+tAz6erUs2Jw4pNZMc79q6yH3BYG77vbQwGbgfn6o= ARC-Message-Signature: i=1; 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Tue, 19 Nov 2024 09:56:56 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:44 +0100 Subject: [PATCH v2 09/11] drm/msm: adreno: enable GMU bandwidth for A740 and A750 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-9-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2528; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=L856afxfFYTrzTjleMcDff0M5LSJvcUyglLdt4As0hg=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFaONQvWVA4bP4yQAg2u1VE2uFOJH4JqIlyKjuL E+b5cDeJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWgAKCRB33NvayMhJ0QTMD/ 9Ym4y6wn5ANBhacJSlVGVq+pieT1LNiuwmZiuqSYT3/FAUZxjXIcuGnBVPWROkU8WG/7Ea0BV6zx7G GaAg7kVOc6fwaAXUEgidaO+BO0d/C6XjOF75YoaVwNzEQ632acKIeBWDCPnPKv58KD+Nqw/LQTpl+2 Pl+4ZitIKwP5OlbelgcghCk+KiNxKPRxpiOi4OXJeJPLGh2eAKQCWQae7uSKmHofFvSefqK3+3DIlJ HBQpyNslSFCzh5BZ/CPPCBfyc+rNP7TYAxZHT3EbolVv2Ti8Q2PuAcFJcKHVjZKAsQU5TB/y1Hikhx 3900PeUp1zuXz+LiCiACvsOKvnDAQAEsHUtMwEj6rSyUdixVbGCZHOsCpCMxtfeVyxm/A7b7R96CNN xCIkhzd//K64UKDkLx/oARBg/KC5TWNblhqNWee2XVrc2civdB1OWbFWSk2mt6J8S2/TL6h17/Vb9v vJl1D4wrMkfcsQ+48D6qY8vzG4BYACQGe3qw7xXqmgaj24pHeBPGfRMTI5/3obZsMIzHSAWzenpqDT EccOZwyzZtuPN2FJzDiPPdkiqoQV82UdKrsyKgNjS6l9NYraZ+Pwc/G9njaCkRkMW8OSHPGulWOj3O 8QmSiYESfdbe44ubCXHV1PNcAlfkTHDA1s/n1O9Q4+qzWx0rV5ujJhUziC8Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Now all the DDR bandwidth voting via the GPU Management Unit (GMU) is in place, declare the Bus Control Modules (BCMs) and the corresponding parameters in the GPU info struct and add the GMU_BW_VOTE feature bit to enable it. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 93f0d4bf50ba773ecde93e6c29a2fcec24ebb7b3..7cb96d524f76df67c6ee4377827a38384c1b343a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1379,7 +1379,8 @@ static const struct adreno_info a7xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | - ADRENO_FEAT_PREEMPTION, + ADRENO_FEAT_PREEMPTION | + ADRENO_FEAT_GMU_BW_VOTE, .init = a6xx_gpu_init, .zapfw = "a740_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1388,6 +1389,16 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202, + .bcm = { + [0] = { .name = "SH0", .buswidth = 16 }, + [1] = { .name = "MC0", .buswidth = 4 }, + [2] = { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 4192 * SZ_1K, @@ -1424,7 +1435,8 @@ static const struct adreno_info a7xx_gpus[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .features = ADRENO_FEAT_HAS_CACHED_COHERENT | ADRENO_FEAT_HAS_HW_APRIV | - ADRENO_FEAT_PREEMPTION, + ADRENO_FEAT_PREEMPTION | + ADRENO_FEAT_GMU_BW_VOTE, .init = a6xx_gpu_init, .zapfw = "gen70900_zap.mbn", .a6xx = &(const struct a6xx_info) { @@ -1432,6 +1444,16 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202, + .bcm = { + [0] = { .name = "SH0", .buswidth = 16 }, + [1] = { .name = "MC0", .buswidth = 4 }, + [2] = { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 3572 * SZ_1K, From patchwork Tue Nov 19 17:56:45 2024 Content-Type: text/plain; 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Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2162; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=xTy0814t50k26n3IdWEnCW6RpXe9FNt3pkGR9JMo8Wo=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFbd07WfUX+D3DO8S9DCJmtm3fmLCUXBbP0PPX5 yQHxYC6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWwAKCRB33NvayMhJ0dxhD/ 0eLXNGnWTLn0HhT5yDPUlg/ODVerSk5fLn5D0uGYbMNd6xHehmhMi7HzPEVFIlHAqzm0mbVZ8aXz3U xV7/qI2EAkv70rCMw9s269YKLo4UBvAc5DL0pflSy+gJaMeEPH3pCpCoRzVahSWTnYnfKEbUDTLaHV sO13U/ZkaHm4B3RCHbdglvwFS9kRz5Snqw/kXBzvsFTWhJfO25VsGiGE3iiWOtN3t8mKq19B59WCK1 aMzFlsensMqpdXOMPihgc3TkDXleatgpi6n+p/shVsUeyrxLvLp0LSxI0fiUCB3k/JDK/MiR4nKNeJ 9d9YgeuCEaPajGFk/H1MsfJ8HjjxPQhfLzrNcd51u+dJxlOOSqLXdWAfNDJFvqJWLd28yUSBeclw3j iGerbFp9eGbfn2PNDJgA73NmDT/e81goHVXesCs00ET40y5TPrcvq+PN1hZ6H4gYId4QVmNioMIu7Q cvFagAEBfgItx/18KTFIxatu6J8x/f4ZSetvCgU3e3tUgrHi5m2Av4bMoZkjn7pVnlycEXq2+bAbVy L8Pc8dHEGHh0+EZPumH9bYKCUiv85Odas2Mg7k0HrYcSRGIULlh7XMhc7j8Bi+o+KQLwc35xsj2+Pn eKCapM6aujBfwjSimn9B4NP0SvuYrtbyAe+AjnBKhhEEu3q6wf0JpwBD0LWA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 9dc0ee3eb98f8711e01934e47331b99e3bb73682..808dce3a624197d38222f53fffa280e63088c1c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2113,6 +2113,9 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + status = "disabled"; zap-shader { @@ -2126,41 +2129,49 @@ gpu_opp_table: opp-table { opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; 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Tue, 19 Nov 2024 09:56:58 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da27fe68sm208302275e9.24.2024.11.19.09.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 09:56:58 -0800 (PST) From: Neil Armstrong Date: Tue, 19 Nov 2024 18:56:46 +0100 Subject: [PATCH v2 11/11] arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241119-topic-sm8x50-gpu-bw-vote-v2-11-4deb87be2498@linaro.org> References: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> In-Reply-To: <20241119-topic-sm8x50-gpu-bw-vote-v2-0-4deb87be2498@linaro.org> To: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2636; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=kMBG33vo/TOc40mVibFxMI9MiLmVj3cBO8HFx/GtxHk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnPNFbEK25BwtwTu1JMvsqoiBYwcvGuuHxuWkwKltH JiltqguJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZzzRWwAKCRB33NvayMhJ0SqJD/ 9i9oT1zcWnuyY+2ojc3JgiG8RZ8/za1lypAPHpIoWVyEqom9FIhYIr5FQhaBl8JzvTyLgD5dWllI46 xxzzMukeW1ktiB/KPRpfA/qz1LbqwExPkNQVl8ruAMbqBYXAUVPHxmlYxEkD0WuUga+D/CX9Xik71k EENR+lA4BtGV7oMNCM1bQ1ov1HNA2p3jmOY7Km2JYzI0lzXkuwskSHjiN1B6wDVtQgdBfU2SJK2gTS mxXzExfxB9VsQDtMgcy9ejIRVoidE9NeFJUYAbTflhXprqiPS08t6S6FoVv6lIA/l6cQPprydHYCGL Jj7gxQv6t1+boECssBZUnNCqepbKsacMzl+b4KJ8RPrOaE9xJMvVMIwvJWlBhyzSqCVCBVEU3dGnzk O/bOXlwFhF4bWgUR+Qu/VTw7QvCQ6JGkY66Mn9mp2Vyx646XSu/L/tCYvP5j70I8k7gg2RlPJKjSWq 4U0AX/V3yGRATzqzGJMvvWraXnglSRW0OVivH9GCNMsGpbdpz5oUWi3KOyHyE+l2p6anawxBOGxx2J ZhkTaJCDFFiNapDGgPEpDSsj+j0KXa3TIR/G5IL3zC7ZFigY3hFKs0q4+cvAg9LCE106xwAem7Qvd1 UsfFkATgF/Hg9N4PH2GzIJYmYirtoOjIshEu/UTgSZhQiBWYSMcV0yqVUm3g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 01ac3769ffa62ffb83c5c51878e2823e1982eb67..331c5140c16bf013190d6da136c0920009d2646b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2636,6 +2636,9 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + status = "disabled"; zap-shader { @@ -2649,56 +2652,67 @@ gpu_opp_table: opp-table { opp-231000000 { opp-hz = /bits/ 64 <231000000>; opp-level = ; + opp-peak-kBps = <2136718>; }; opp-310000000 { opp-hz = /bits/ 64 <310000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-366000000 { opp-hz = /bits/ 64 <366000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-422000000 { opp-hz = /bits/ 64 <422000000>; opp-level = ; + opp-peak-kBps = <8171875>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = ; + opp-peak-kBps = <8171875>; }; opp-578000000 { opp-hz = /bits/ 64 <578000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-629000000 { opp-hz = /bits/ 64 <629000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-770000000 { opp-hz = /bits/ 64 <770000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-834000000 { opp-hz = /bits/ 64 <834000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; }; };