From patchwork Tue Nov 19 20:23:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe JAILLET X-Patchwork-Id: 13880505 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4199D6C294 for ; Tue, 19 Nov 2024 20:23:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5585710E2BD; Tue, 19 Nov 2024 20:23:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=wanadoo.fr header.i=@wanadoo.fr header.b="FsQhm00q"; dkim-atps=neutral Received: from smtp.smtpout.orange.fr (smtp-21.smtpout.orange.fr [80.12.242.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id E4CA810E2BD; Tue, 19 Nov 2024 20:23:31 +0000 (UTC) Received: from localhost.localdomain ([90.11.132.44]) by smtp.orange.fr with ESMTPA id DUkytck50PqyaDUkytUMqx; Tue, 19 Nov 2024 21:23:29 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wanadoo.fr; s=t20230301; t=1732047809; bh=FN6W5Nw0/usd3+xzvpL3gptGh1Ltab0zPDw2vSLmM4U=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=FsQhm00qozxXMgu3E5JGxbABbzt50IvAJAzpPbzgcdWXod5n4B3Ej/vwbAQc42RkN B59AU0DqbFTjU7n5LI1f9X2KWTzOhClBsVAPyaN7AXxYQti0mLhoul3ymr3cvvSVSq XwqmiV5tp71HIShDQy5PPEjTCSmaSnhZrGxXzJmO3JWNxVX0O8N39CYdK9MC3HI9v5 FG24hYfByBMrPFvNAhQ7eoFiv4rZdCvMAsd6fOvJh5eF/YLvLt2qCJ1mEklcZGWmUC S+KcGm0+3q7k7A0XqTOhOAHXBZpTeHW50lMNXqZjkHz5uLfpmWHCzi+9WTGPdq+oiz 3t/JhfMmq3f1g== X-ME-Helo: localhost.localdomain X-ME-Auth: Y2hyaXN0b3BoZS5qYWlsbGV0QHdhbmFkb28uZnI= X-ME-Date: Tue, 19 Nov 2024 21:23:29 +0100 X-ME-IP: 90.11.132.44 From: Christophe JAILLET To: Kenneth Feng , Alex Deucher , =?utf-8?q?Christian_K=C3=B6nig?= , Xinhui Pan , David Airlie , Simona Vetter , Evan Quan Cc: linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org, Christophe JAILLET , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH] drm/amd/pm: Fix an error handling path in vega10_enable_se_edc_force_stall_config() Date: Tue, 19 Nov 2024 21:23:18 +0100 Message-ID: <6584a62da5436ffd726d68e5dbdaf5eadde8af9d.1732047767.git.christophe.jaillet@wanadoo.fr> X-Mailer: git-send-email 2.47.0 MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In case of error after a amdgpu_gfx_rlc_enter_safe_mode() call, it is not balanced by a corresponding amdgpu_gfx_rlc_exit_safe_mode() call. Add the missing call. Fixes: 9b7b8154cdb8 ("drm/amd/powerplay: added didt support for vega10") Signed-off-by: Christophe JAILLET --- *Not* even compile tested only because of missing "hwmgr.h". I've not checked on which arch it is supposed to run in order to cross-compile. This patch is speculative, review with care! --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c index 3007b054c873..776d58ea63ae 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_powertune.c @@ -1120,13 +1120,14 @@ static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT); if (0 != result) - return result; + goto exit_safe_mode; vega10_didt_set_mask(hwmgr, false); +exit_safe_mode: amdgpu_gfx_rlc_exit_safe_mode(adev, 0); - return 0; + return result; } static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)