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Add the compatible in the list of 3 clocks required by the GPU SMMU. Remove the compatible from the "no clocks" list. Signed-off-by: Qingqing Zhou --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index c1e11bc6b7a0..c179ad1b4097 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -88,6 +88,7 @@ properties: items: - enum: - qcom,qcm2290-smmu-500 + - qcom,qcs615-smmu-500 - qcom,sa8255p-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sar2130p-smmu-500 @@ -474,6 +475,7 @@ allOf: items: - enum: - qcom,qcm2290-smmu-500 + - qcom,qcs615-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - const: qcom,adreno-smmu @@ -559,7 +561,6 @@ allOf: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - - qcom,qcs615-smmu-500 - qcom,qcs8300-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8255p-smmu-500 From patchwork Fri Nov 22 07:49:22 2024 Content-Type: text/plain; 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Fri, 22 Nov 2024 07:49:49 GMT Received: from hu-qqzhou-sha.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 23:49:46 -0800 From: Qingqing Zhou To: , , , , , , , , CC: , , , , Qingqing Zhou Subject: [PATCH 2/2] arm64: dts: qcom: qcs615: add the GPU SMMU node Date: Fri, 22 Nov 2024 13:19:22 +0530 Message-ID: <20241122074922.28153-3-quic_qqzhou@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241122074922.28153-1-quic_qqzhou@quicinc.com> References: <20241122074922.28153-1-quic_qqzhou@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TZ3k1Tz6GBDgMYVKgXHGDRokyG8CGYiH X-Proofpoint-ORIG-GUID: TZ3k1Tz6GBDgMYVKgXHGDRokyG8CGYiH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=876 spamscore=0 mlxscore=0 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220064 Add the Adreno GPU SMMU node for QCS615 platform. Signed-off-by: Qingqing Zhou Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 56af38d4f75f..4e0f26563db9 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -528,6 +528,33 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@50a0000 { + compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x50a0000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + dma-coherent; + + power-domains = <&gpucc CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + + interrupts = , + , + , + , + , + , + , + , + ; + }; + dc_noc: interconnect@9160000 { reg = <0x0 0x09160000 0x0 0x3200>; compatible = "qcom,qcs615-dc-noc";