From patchwork Fri Nov 22 11:57:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13883117 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 513BD524F for ; Fri, 22 Nov 2024 11:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732276659; cv=none; b=QGrGjCRWo5JGjBO06d8NG43KuxSqCWwpIXMnJayevVhgIA5H0Rrkk+A0hNTktdCk50WcXFewIlNpT1Y9TvtwauoeK1qZaa2lVQEMO59/cfaIvy2Odo3p/B01UoI9OqXDElmYAv52dXn9Sf5WCO404ugaMny5tiVak+vzvNS8azU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732276659; c=relaxed/simple; bh=cfD5D141doNNZ7xz4A7VC2kjyhmOZXMIKeGOKLLrsY4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=O624RA5yLxoP1//bL9e+xp9LKDCPqVGLb5mwQUdqxJvFoBNvxpTIwQmKgAtIRSwEiX6NzPYEvv4G4YUp/TNXwipWtsMoaHzIOrTHguPZpj0xL30K8g7iKpjnLahu5Cby0bms/DLrvxq0RTLvIK+FiOwbxlgjcl/mbMXbKaCRjRU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U1UgAHKJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U1UgAHKJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 666CAC4CECE; Fri, 22 Nov 2024 11:57:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732276658; bh=cfD5D141doNNZ7xz4A7VC2kjyhmOZXMIKeGOKLLrsY4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U1UgAHKJOyMfCLxaL/tfm7QaKz27jPWJ+SBX0qaSY0iMR4T23r/VLhFmTVBx8Z6Sv G3biLatPI1Be3Gz7O0lYcpZQu/KG7obwWbPeFjeLl8FKV/Jxya32GUxkUVaXcUq8eC Yocu7IqfXARtf9evM21mIbfGaFI59oYhi06CGes+TXaZWYLx5arCSceGulJLWAkx/J 53xr9tben7L9w+fuP2bmkQcir6kqTNT65ep4hJ3skULiG1E8Iha9Ni0i05OweOYhlE 2VqmCGXob8K73adU51Inw3O6t9/dOJ/95q0JwCWW1dnojIh0KPudX1aywzPlCAD+Gl 5JXrW/GavnkcQ== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 1/5] PCI: dwc: ep: iATU registers must be written after the BAR_MASK Date: Fri, 22 Nov 2024 12:57:10 +0100 Message-ID: <20241122115709.2949703-8-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241122115709.2949703-7-cassel@kernel.org> References: <20241122115709.2949703-7-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3556; i=cassel@kernel.org; h=from:subject; bh=cfD5D141doNNZ7xz4A7VC2kjyhmOZXMIKeGOKLLrsY4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIdCmd1XXKaUMl2J/WuqkKLaaGaRsYN3sJwBSZjpgw1i 7Msi3M7SlkYxLgYZMUUWXx/uOwv7nafclzxjg3MHFYmkCEMXJwCMBGHXIb/fi0GfLq1kwq5vNSu OuzQyhctyFpzO1Ch+cvzNK5TctYMDP9zLidysdTr1JVOYeau+VLwTGrOrdqJayYIezBuKqt93ck MAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. If we do not write the BAR_MASK before writing the iATU registers, we are relying the reset value of the BAR_MASK being larger than the requested size of the first set_bar() call. The reset value of the BAR_MASK is SoC dependent. Thus, if the first set_bar() call requests a size that is larger than the reset value of the BAR_MASK, the iATU will try to write to read-only bits, which will cause the iATU to end up redirecting to a physical address that is different from the address that was intended. Thus, we should always write the iATU registers after writing the BAR_MASK. Since set_bar() supports dynamically changing the physical address of a BAR, this change is slightly bigger than a single line change. While at it, add comments which clarifies the support for dynamically changing the physical address of a BAR. (Which was previously missing.) Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 46 ++++++++++++++----- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 507e40bd18c8..34d60142ffb5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -222,19 +222,30 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) return -EINVAL; - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - if (!(flags & PCI_BASE_ADDRESS_SPACE)) - type = PCIE_ATU_TYPE_MEM; - else - type = PCIE_ATU_TYPE_IO; + /* + * Certain EPF drivers dynamically change the physical address of a BAR + * (i.e. they call set_bar() twice, without ever calling clear_bar(), as + * calling clear_bar() would clear the BAR's PCI address assigned by the + * host). + */ + if (ep->epf_bar[bar]) { + /* + * We can only dynamically change a BAR if the new configuration + * doesn't fundamentally differ from the existing configuration. + */ + if (ep->epf_bar[bar]->barno != bar || + ep->epf_bar[bar]->size != size || + ep->epf_bar[bar]->flags != flags) + return -EINVAL; - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); - if (ret) - return ret; + /* + * When dynamically changing a BAR, skip writing the BAR reg, as + * that would clear the BAR's PCI address assigned by the host. + */ + goto config_atu; + } - if (ep->epf_bar[bar]) - return 0; + reg = PCI_BASE_ADDRESS_0 + (4 * bar); dw_pcie_dbi_ro_wr_en(pci); @@ -246,9 +257,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); } - ep->epf_bar[bar] = epf_bar; dw_pcie_dbi_ro_wr_dis(pci); +config_atu: + if (!(flags & PCI_BASE_ADDRESS_SPACE)) + type = PCIE_ATU_TYPE_MEM; + else + type = PCIE_ATU_TYPE_IO; + + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + if (ret) + return ret; + + ep->epf_bar[bar] = epf_bar; + return 0; } From patchwork Fri Nov 22 11:57:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13883118 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65B6D524F for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ixCJsekC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B977DC4CED0; Fri, 22 Nov 2024 11:57:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732276662; bh=upNCPc9D/m4J70XmQNctLDQGOmeQN4f4dphCC/Twwio=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ixCJsekCsQpndEwEjVIHYJ19FrSvpGKOh3IxYL4PQ7aqq74gCKJNG9f+8bPOK+RYV uPaOVsSKW2jB6Wych0NbaY7EXPMnvKyuGyCai+ZYNVHh0clVI1CO2UKkD1a40SiwOG 6sJSzp97efF7vZlTjwrCDTx41C/1Gtm4Ryk6RnfvUU5P9ysY1HjAIs6odTPG1Cz09s zTBPqA+LqcFEokKUsxtRGmbjnXns9Ea/ymwwc/C4wfgyZHPwgUHlUXHVM7HbXL0Fqz VDqOmx2f7tmPx81kyZ635hvRUDFL39/ojxbBVS1V1NzhaVgsSTG+CJw4LEfidgoowq MTzCmyOH+ap3A== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 2/5] PCI: dwc: ep: Add 'address' alignment to 'size' check in dw_pcie_prog_ep_inbound_atu() Date: Fri, 22 Nov 2024 12:57:11 +0100 Message-ID: <20241122115709.2949703-9-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241122115709.2949703-7-cassel@kernel.org> References: <20241122115709.2949703-7-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4252; i=cassel@kernel.org; h=from:subject; bh=upNCPc9D/m4J70XmQNctLDQGOmeQN4f4dphCC/Twwio=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIdCmffPLTtR/CFWGdv5+Tb9o8Xq3fLTeGVmi+3s3pmZ nmU46mTHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZiI6kyGvyK5MfzcHEEGFp6R PY2BEvduHUjOXXzDdOtk5smzc033hTP8U/8fvHRdjAnv9mhfs+0JJa1PrGLnBOSf2/joUfMVjqx iRgA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA dw_pcie_prog_ep_inbound_atu() is used to program an inbound iATU in "BAR Match Mode". A memory address returned by e.g. kmalloc() is guaranteed to have natural alignment (aligned to the size of the allocation). It is however not guaranteed that pci_epc_set_bar() (and thus dw_pcie_prog_ep_inbound_atu()) is supplied an address that has natural alignment. (An EPF driver can send in an arbitrary physical address to pci_epc_set_bar().) The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. Add a check to ensure that the physical address programmed in the iATU is aligned to the size of the BAR (BAR_MASK+1), as without this, we can get hard to debug errors, as we could write to bits that are read-only (without getting a write error), which could cause the iATU to end up redirecting to a physical address that is different from the address that we intended. Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 +++++--- drivers/pci/controller/dwc/pcie-designware.c | 5 +++-- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 34d60142ffb5..ff4350e7adb6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -128,7 +128,8 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, - dma_addr_t cpu_addr, enum pci_barno bar) + dma_addr_t cpu_addr, enum pci_barno bar, + size_t size) { int ret; u32 free_win; @@ -145,7 +146,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, } ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type, - cpu_addr, bar); + cpu_addr, bar, size); if (ret < 0) { dev_err(pci->dev, "Failed to program IB window\n"); return ret; @@ -265,7 +266,8 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, else type = PCIE_ATU_TYPE_IO; - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar, + size); if (ret) return ret; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..3c683b6119c3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -597,11 +597,12 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, } int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar) + int type, u64 cpu_addr, u8 bar, size_t size) { u32 retries, val; - if (!IS_ALIGNED(cpu_addr, pci->region_align)) + if (!IS_ALIGNED(cpu_addr, pci->region_align) || + !IS_ALIGNED(cpu_addr, size)) return -EINVAL; dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..fc0872711672 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -491,7 +491,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u64 size); int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar); + int type, u64 cpu_addr, u8 bar, size_t size); void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci); From patchwork Fri Nov 22 11:57:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13883119 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2826D1DC05D for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PE7Zvj5h" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3994C4CED0; Fri, 22 Nov 2024 11:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732276665; bh=9w4djXq5Jah2Ystn3ezgbNxbPZ4VlU3yHv4SKjG7O9g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PE7Zvj5heSieWpD3s9oUalXBThbliSN8EHs0GLZiS/+1+xgT+Ta3nu1Oj2tZ8Kwbi gjtFQ014dXL/SOgIK/3meDxvy/ZuNjj/+HdpHH9ZKHwh47y+ZVX2P4Oek/feIadINk lJfqMxDOras/TJFPMUV9AIf8oXHTGfsk1B5gyYyB3fTbYqj8l2vCOz9tQ2aRUVckWG TH2ToFTA17IF//VeMcdPbKrYT8h013vueTeEer5e3yMreElFe02w4syyym1MBHC7/S IC70NgTqCxNwYLPKh8jSxfHVYM7odYR0+zPKEQRgiAUYi6aTqLcpUG+NeQoeyQWuE3 AR6//tPNbSTMw== From: Niklas Cassel To: Jesper Nilsson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Niklas Cassel , linux-arm-kernel@axis.com, linux-pci@vger.kernel.org Subject: [PATCH v4 3/5] PCI: artpec6: Implement dw_pcie_ep operation get_features Date: Fri, 22 Nov 2024 12:57:12 +0100 Message-ID: <20241122115709.2949703-10-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241122115709.2949703-7-cassel@kernel.org> References: <20241122115709.2949703-7-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1648; i=cassel@kernel.org; h=from:subject; bh=9w4djXq5Jah2Ystn3ezgbNxbPZ4VlU3yHv4SKjG7O9g=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIdCmczlk9SMehply5kaZSbcu+a+/5Trw5NTFL68FF4w zz7RU7eHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZiIyCVGhoaC64JrLz6M37/3 qo6GGIv4HnPemLX9d3LmXJz+26X3bD/DXwGvI9+6Vt7c5aX8uri25On61rzUY7uaDq7PCj/bEZV 6mg0A X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA All non-DWC EPC drivers implement (struct pci_epc *)->ops->get_features(). All DWC EPC drivers implement (struct dw_pcie_ep *)->ops->get_features(), except for pcie-artpec6.c. epc_features has been required in pci-epf-test.c since commit 6613bc2301ba ("PCI: endpoint: Fix NULL pointer dereference for ->get_features()"). A follow-up commit will make further use of epc_features in EPC core code. Implement epc_features in the only EPC driver where it is currently not implemented. Signed-off-by: Niklas Cassel Reviewed-by: Frank Li Acked-by: Jesper Nilsson --- drivers/pci/controller/dwc/pcie-artpec6.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index f8e7283dacd4..234c8cbcae3a 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -369,9 +369,22 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static const struct pci_epc_features artpec6_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, +}; + +static const struct pci_epc_features * +artpec6_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &artpec6_pcie_epc_features; +} + static const struct dw_pcie_ep_ops pcie_ep_ops = { .init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, + .get_features = artpec6_pcie_get_features, }; static int artpec6_pcie_probe(struct platform_device *pdev) From patchwork Fri Nov 22 11:57:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13883120 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C75F01DE2A4 for ; Fri, 22 Nov 2024 11:57:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732276667; cv=none; b=COoV1Hs7K9XjHLDtlk15v/+B1rF9MxjhvRlZx+iDdosIYz2Qs7fNbar+7x1b6RPupeuU2h4d8K+l8CMVSye2YLabaFWNAwHJoJdC03DzOAqZA5uLrieGbNJNJ3N1Q1L5A83Li53hDKpT6KNezpk3Iv8StQK8e1aMXCCAxnhOK80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732276667; c=relaxed/simple; bh=bp4gTYfxr4o5rF6v3uVH2tPluH/lbIksLfFv6D+dFVw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o78PibI+xN5REE3/ZsDQh/qR5Lm4p53PHvi+TRPJsLCf9wYT94Csn+qrl0KdZGo14xwekzqXUUl78rvKIAFdvDIrp3fPmfomPdi0IJBfMWZl45vslVCTqp7uSKD2ZkgZ2qHbRz337xpTq+PBzDxGTb9jSQ/QjkFeqqhE8HcMzN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tJLdtfhq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tJLdtfhq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFDC0C4CECE; Fri, 22 Nov 2024 11:57:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732276667; bh=bp4gTYfxr4o5rF6v3uVH2tPluH/lbIksLfFv6D+dFVw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tJLdtfhq0OletroR1bgIKeDhRwPilvBc7+lEBBwsAUVFpJH37bCa3ok523gWYzOih IUQ4UJJHOxZWaP5i1kxw0r7oNjTRLpDPbdV0GPT3jVBKUbsh+mH6bKjGi+/Vbo29mk nGwg+km6Gz1OBm3CwpMBq+w50sHIZ6C2hM0iizNifBU6LDtWVRGyUzQ8VO05z1IUeb fhfNW5lJGmK/Bpo0Zq2KXgwJbj82bamqW+CBiFCwOmotzyVt+dXwqwt+MSEFs0e6Tx V32utF2Wf72yHCaQGk/XGkG7Km1bI83J6Kkc5+Y3NwaLOsTE3NnIK+89e94+faZ3yU qL4RvsC3OK7JA== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 4/5] PCI: endpoint: Add size check for fixed size BARs in pci_epc_set_bar() Date: Fri, 22 Nov 2024 12:57:13 +0100 Message-ID: <20241122115709.2949703-11-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241122115709.2949703-7-cassel@kernel.org> References: <20241122115709.2949703-7-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1824; i=cassel@kernel.org; h=from:subject; bh=bp4gTYfxr4o5rF6v3uVH2tPluH/lbIksLfFv6D+dFVw=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIdCmc/ioqJ9zFKnzFFfPvcBxNjD0mbRh9/F7g57OLkT UGsq3J/d5SyMIhxMciKKbL4/nDZX9ztPuW44h0bmDmsTCBDGLg4BWAin84x/NM0nP2Th0F4ZpBR 3NLvzz5fYeyYKOFfHzhpzcymg9UqiioM/3RPeEy3e6y3dGe6AHOKihT/uu0Wa6xl9bapJ1lrNB2 5wwoA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A BAR of type BAR_FIXED has a fixed BAR size (the size cannot be changed). When using pci_epf_alloc_space() to allocate backing memory for a BAR, pci_epf_alloc_space() will always set the size to the fixed BAR size if the BAR type is BAR_FIXED (and will give an error if you the requested size is larger than the fixed BAR size). However, some drivers might not call pci_epf_alloc_space() before calling pci_epc_set_bar(), so add a check in pci_epc_set_bar() to ensure that an EPF driver cannot set a size different from the fixed BAR size, if the BAR type is BAR_FIXED. The pci_epc_function_is_valid() check is removed because this check is now done by pci_epc_get_features(). Signed-off-by: Niklas Cassel Reviewed-by: Frank Li --- drivers/pci/endpoint/pci-epc-core.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index bed7c7d1fe3c..c69c133701c9 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -609,10 +609,17 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { - int ret; + const struct pci_epc_features *epc_features; + enum pci_barno bar = epf_bar->barno; int flags = epf_bar->flags; + int ret; - if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + epc_features = pci_epc_get_features(epc, func_no, vfunc_no); + if (!epc_features) + return -EINVAL; + + if (epc_features->bar[bar].type == BAR_FIXED && + (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || From patchwork Fri Nov 22 11:57:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13883121 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 869821DE891 for ; Fri, 22 Nov 2024 11:57:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732276670; cv=none; b=ExKrtDN1Y2GLYedLbgWhAp1/kcBMd3PAxDkD1ZwJP03EmDJn0ybYrXYkZ4kI7A9LQ1VVvH3a9NmS4pD5Gf4JM0YhA1ajJ66wFrgYVEW9FMO/+J5jgd19qhfOLNrhlWaMYgUfe1H5pptZLMzTjZ8NRBoEZ4RMTCNAzBWZoJNgte4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732276670; c=relaxed/simple; bh=WVDkLSYz6JtRR+SLpXWshGrwSkHerX/M86Ha9lQyt2k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DZJASYEyXHhFvSd+5xm/pd/oN0b1YenilEtY3pWaqMbHtZGi3Zw/sC29cn56ABToPXMzuuuupfnYMpMJaCDh02p7L8jV4RgnttPrR0Qcb6xcpS293gJw20zhcU0QYa2MbfeIhj3b/0BEyDJN27YaPkBCDnG1e1uyOzMTFkwGpNY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iG4AgvbG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iG4AgvbG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F5B6C4AF09; Fri, 22 Nov 2024 11:57:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732276670; bh=WVDkLSYz6JtRR+SLpXWshGrwSkHerX/M86Ha9lQyt2k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iG4AgvbGufvA0u+HZgoZY8zFnZ6ghs595MM+hszo+YYFIKwDp6dsVGSkmPDMVMz24 0eALzfJSmb+f1OYhEGYSfXzEr0H+J0RJ8RsQ/nG7UTdXd9pL/3l4ZUcqqnUYm0zmyC FFyTpNDxbggMXbRTXTBmpfLjCBrmyfB4yr+TzTsKPd54NOLtMj1wGA03Osaz8mfGfL N3d63UWIjAq7FhaiSjQh1YwQNoOLDHMeNCJEBBawpgnNCzYNiAJa5La0HdISILGcfk bbUPaKeRMw9BuYri1/YB8NdNQ3GVZkYPIVN3lT+KP9OeEC7xF+vmATXc9c//pFYLMV ZgVeDEeyDuXuw== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v4 5/5] PCI: endpoint: Verify that requested BAR size is a power of two Date: Fri, 22 Nov 2024 12:57:14 +0100 Message-ID: <20241122115709.2949703-12-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241122115709.2949703-7-cassel@kernel.org> References: <20241122115709.2949703-7-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1134; i=cassel@kernel.org; h=from:subject; bh=WVDkLSYz6JtRR+SLpXWshGrwSkHerX/M86Ha9lQyt2k=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNIdCudMiPtqU2O08rGft0TCHXWr1t5DPyZZRH+uL/v3z O9E2b3ijlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAExEt5uRob87JK20NedlxwKu VwuMZj5JXuD/Ikxon5An43+N2xwFOxgZZmmb7NvL2y19r/7gwVVb4j5Pki31VDkgXPAnR8PUSVG aDwA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA When allocating a BAR using pci_epf_alloc_space(), there are checks that round up the size to a power of two. However, there is no check in pci_epc_set_bar() which verifies that the requested BAR size is a power of two. Add a power of two check in pci_epc_set_bar(), so that we don't need to add such a check in each and every PCI endpoint controller driver. Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epc-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index c69c133701c9..6062677e9ffe 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -622,6 +622,9 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; + if (!is_power_of_2(epf_bar->size)) + return -EINVAL; + if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || (flags & PCI_BASE_ADDRESS_SPACE_IO && flags & PCI_BASE_ADDRESS_IO_MASK) ||