From patchwork Fri Nov 22 19:09:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13883578 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0AEF1DFE02; Fri, 22 Nov 2024 19:10:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732302630; cv=none; b=Pf7CDYs9s1DEFxTGBMiw73vg9SCASzBxMlIJdYMG5PVuVuC2SQGyDQ4tneAQnnv8YR3g6kft43Lv6oq0GemQUI/K13eiEimueb3P9z+g0QmECpeh/XPb1OK5lqi5k1pcKQwNh/TZVlKZzoHoK9atBZ0b8gs/Ma7OdR/Q8MOmab8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732302630; c=relaxed/simple; bh=G7MhZdWm35M1gaIihHtcd9K+V5mSFHhK7xXwjTbLEmE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=BpVrIFe60BRDx0SX3UZcYvlrStkXJ2ENUdA43sX0UXB/37DhZillzRxbMDydct+FiXaq3aFlhISo2uZpxtog8No2ita9tf4sWvqNujGKAnt+3IipCILYmw9watxwDNx6WTuEWKeZwh0ML9EWbHl5FkQ9P628qUihWEP53V8HaiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CBTsFGgn; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CBTsFGgn" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AMDJJdg025224; Fri, 22 Nov 2024 19:10:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Ji+V4XMLO5vGToQIEtXGOYQfcXEWqKl0NnzIeOngEXc=; b=CBTsFGgnUESZDPse Dz5Eu5yByIy79eNvuQB+DK5w/81cPs5v5PkkRaOxeOtqpn4d/cG7PzqDGqDqTd4N qMhpAv4bOP4MeerWvseVKA391V8ihCSmlFi8DgjG9L8zKdknd/j2X6gib++3VX0y hlDf+id6ua6fhxDjv4+HrNB//4hRjXrIq0qvHDtWtGBCxxQwWv8QdPusMabJvCid jrCzcNU55v7sLKLKQQz8fZmllAWe0PiuMumBPimN6XfWntc8k5+cjtEReMptZbHu hLACFiRK5rZAWJ8XqThEuBbyZSjoFgjkWCMvrO3bFInFEVy/7eDR8n1oRgguLMCX 1dOexA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43251nma3f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 19:10:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AMJAFMT007664 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 19:10:15 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 22 Nov 2024 11:10:11 -0800 From: Krishna chaitanya chundru Date: Sat, 23 Nov 2024 00:39:59 +0530 Subject: [PATCH v5 1/3] PCI: dwc: Skip waiting for link up if vendor drivers can detect Link up event Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241123-remove_wait2-v5-1-b5f9e6b794c2@quicinc.com> References: <20241123-remove_wait2-v5-0-b5f9e6b794c2@quicinc.com> In-Reply-To: <20241123-remove_wait2-v5-0-b5f9e6b794c2@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Konrad Dybcio CC: , , , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732302606; l=1886; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=G7MhZdWm35M1gaIihHtcd9K+V5mSFHhK7xXwjTbLEmE=; b=yt0tycpZjY1RTZPpYk0RJeCoCYbx0shAT4QWI6mell82QnoXp/bs/biGbY63LEuasKRiqK22j zSiLZHdlv2AAHZqA7Qe4qnB6B4t3PFiX8R0QMN34i9ZYqeLlaLyvaXP X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: t0K4xC6EZbEzX4CV2y68J1QBfuH7ZV_O X-Proofpoint-GUID: t0K4xC6EZbEzX4CV2y68J1QBfuH7ZV_O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 spamscore=0 impostorscore=0 phishscore=0 mlxlogscore=935 adultscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220161 If the vendor drivers can detect the Link up event using mechanisms such as Link up IRQ and if the driver can enumerate downstream devices instead of waiting here, then waiting for Link up during probe is not needed here, which optimizes the boot time. So skip waiting for link to be up if the driver supports 'use_linkup_irq'. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++-- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d2291c3ceb8b..cc172255d3b6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -530,8 +530,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) goto err_remove_edma; } - /* Ignore errors, the link may come up later */ - dw_pcie_wait_for_link(pci); + /* + * Note: The link up delay is skipped only when a link up IRQ is present. + * This flag should not be used to bypass the link up delay for arbitrary + * reasons. + */ + if (!pp->use_linkup_irq) + /* Ignore errors, the link may come up later */ + dw_pcie_wait_for_link(pci); bridge->sysdata = pp; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..1d0ec47e1986 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -379,6 +379,7 @@ struct dw_pcie_rp { bool use_atu_msg; int msg_atu_index; struct resource *msg_res; + bool use_linkup_irq; }; struct dw_pcie_ep_ops { From patchwork Fri Nov 22 19:10:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13883579 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1093F1DFE35; Fri, 22 Nov 2024 19:10:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732302632; cv=none; b=R6DdTsNyCGYV//B5ZSYbaXhRhBgwK4RL7boMAty1XpgrN5RR8ULNKn+iwXkOGFv3MowXCQ66t3rwwjCHmIZAjqN3c+pUt5NbEekELhtYG8/1B8zbUU3ln02xf8Mfd/GbqN2i8aY3fPsaiLq2c0RXVa/WVEV/2Ta3CJdi5Gp8u1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732302632; c=relaxed/simple; bh=ZFOBw3BMKmVGtHb0UcVh69Xu/bqSKbBzvXx11WmbKHM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=sGc2QkJP73CDyKza3fFuQws15OS6ez5jSSc7APgytUwa4CrsEH+DbCpLYR+9jg5G0CMKkQnhRScrbvrLs7s+9iA7sQU6qdVXzkVqMQ98LlR8rRJIFUz+SIZiy7wuJb2o35ELVpouqHOI9ETOSZ2EJWjjqyL78aGvnIKLQLQqvHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=h63kUd6n; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="h63kUd6n" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AMA6jep027595; Fri, 22 Nov 2024 19:10:21 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Rtxr6wdyL9/5iSlhYv7c+jUJ0eJ4nm8qOAAHZrWd3p0=; b=h63kUd6nyrUY9Fvo 9OKbMLHjNIo2bYUVRfKgepG+ZNA5xFZm4rL7CMWnqHgpXiK8E3Anof1rfSCgUE85 /dvw0TyCEI+N+NwwPmnEUXAJ5pTQntLTvZ1KSXtdInQpQNEHfPuOKBl51NpDeoWz 5qyWzQ9KZUoYxHIChTbql60BPpfSQJs7n7jmFHLTgtzC+dkwAy+ID5Ph1dlJHmzL EYyUMwnPiCSm2v4KnTM86FhP0t8sn4jJTpULFuadcsPAO0Ib0SgUxYkhUtdNLpqf CV4cXue/ukLVXOyKN6v+5upFMAeCyCr0iCnS0FkEOcOSempPoy1/dVoaHrXXVLr8 ouOwDQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 432d5b2vqr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 19:10:20 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AMJAKbm015246 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 19:10:20 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 22 Nov 2024 11:10:15 -0800 From: Krishna chaitanya chundru Date: Sat, 23 Nov 2024 00:40:00 +0530 Subject: [PATCH v5 2/3] PCI: qcom: Set use_linkup_irq if global IRQ handler is present Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241123-remove_wait2-v5-2-b5f9e6b794c2@quicinc.com> References: <20241123-remove_wait2-v5-0-b5f9e6b794c2@quicinc.com> In-Reply-To: <20241123-remove_wait2-v5-0-b5f9e6b794c2@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Konrad Dybcio CC: , , , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732302607; l=1542; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=ZFOBw3BMKmVGtHb0UcVh69Xu/bqSKbBzvXx11WmbKHM=; b=DOXfm8XYstztEIabuC/cLDFkQtaMpv0Sqc+5ujDinZdWjwyqgy4kxNKI9FEKOp0G7OpG8XDwD +Qru1/8xj6JAuGs/4Gqlt5UimkEA6gG22AJmn4YSeytKCcHCfItHHGD X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: woxJ4f__5UlQBKRuKLjkZKvG7ImsIuX7 X-Proofpoint-ORIG-GUID: woxJ4f__5UlQBKRuKLjkZKvG7ImsIuX7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=889 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220161 In cases where a global IRQ handler is present to manage link up interrupts, it may not be necessary to wait for the link to be up during PCI initialization which optimizes the bootup time. So, set use_linkup_irq flag if global IRQ is present and in order to set the use_linkup_irq flag before calling dw_pcie_host_init() call, which waits for link to be up, move platform_get_irq_byname_optional() API above dw_pcie_host_init(). Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index dc102d8bd58c..656d2be9d87f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1703,6 +1703,10 @@ static int qcom_pcie_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pcie); + irq = platform_get_irq_byname_optional(pdev, "global"); + if (irq > 0) + pp->use_linkup_irq = true; + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "cannot initialize host\n"); @@ -1716,7 +1720,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_host_deinit; } - irq = platform_get_irq_byname_optional(pdev, "global"); if (irq > 0) { ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qcom_pcie_global_irq_thread, From patchwork Fri Nov 22 19:10:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13883580 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A06291DF72C; Fri, 22 Nov 2024 19:10:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732302638; cv=none; b=sV+yTDHns82sMoj2+8QlB3J58+BHclzNsQNhhs7hKG6zN/KGtXn64/NrqlCiH/Q3qdkYV842GsjsTRjkq7vEiPRD0cZihywkOgbA97h0WA+h6ZZ83iLH51mW/g0K83rQm8xLabEz/uxWGjtmugfQ+4w3rKm34xOke4FfjEk27Uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732302638; c=relaxed/simple; bh=8NH2yB5xLLOnt00p6vqPplFTBNCd7hf+CR6j9FI9O9w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=SyTm8q3m4I7+/gJ5rDoZBGBYQOy+BxYgMfufxtfk8cwy4XU6Vhyzc2Xf2dvK5N6IxlEEqZh2V45QKSMVuEJq0RTuw3KRG89qnYL7Ls1XeEru81JXEQ4Ll3TyUu3mEVgTt73yCeLaFVNvVgXzx81AihMSOdDX0J20R83wYTLJSs8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ANNIdFq9; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ANNIdFq9" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4AMDZbnZ027713; Fri, 22 Nov 2024 19:10:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Vv7NlU8R41aOG84T042tZhwrHKwcQz1mHKXKct/Et3o=; b=ANNIdFq9Vgs52qW0 sYFvlGHX+wFs1yoK1N3o/gbXzXorIpraFDseX1GrYpBmEBLOHu7jG+9CaC/CrdpK oaz8EraZAEYGAsZ3KyehRMa+6EUJyxm7u4ZG63gRKmV7MEInOSGxvY7u+66gK3w7 9UmiOFI1KW+e8E8kgXQ3MwUFWu4PDld3dOxlBjlg/HTWvGrDtf71uZZfKUBrBb3s 5bMoTMCF98fWBy/9eJohm7WJCErx8DkYID12bsbnwm28X1Rlzfyk7cuSrxF4q3si ocjS5lJqZmvrwberoNJcuYz1S/PgT0B/yqAX+3OoGuOnM/qnq2arg3fIKt7BBg2h GOi8dw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 432h4dtb0t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 19:10:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AMJAOd3025725 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 19:10:24 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 22 Nov 2024 11:10:20 -0800 From: Krishna chaitanya chundru Date: Sat, 23 Nov 2024 00:40:01 +0530 Subject: [PATCH v5 3/3] PCI: qcom: Update ICC and OPP values during link up event Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241123-remove_wait2-v5-3-b5f9e6b794c2@quicinc.com> References: <20241123-remove_wait2-v5-0-b5f9e6b794c2@quicinc.com> In-Reply-To: <20241123-remove_wait2-v5-0-b5f9e6b794c2@quicinc.com> To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Konrad Dybcio CC: , , , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732302607; l=1500; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=8NH2yB5xLLOnt00p6vqPplFTBNCd7hf+CR6j9FI9O9w=; b=jlHUMlK9os0a8uibvg0sVDUzDjiY3qOtLeMErY2m/f7oPN5ohfhFbaH+WVkWyPjT3nl3Os3fw G3zKqogA3PNANNQOGuLoQb5Z5HddzezixH879QKjol/gaxyK3xox2Js X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ZW5XeqCWSW5aqWZuIajKE7S8NrFEYUIm X-Proofpoint-GUID: ZW5XeqCWSW5aqWZuIajKE7S8NrFEYUIm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=897 spamscore=0 adultscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220161 The 'commit 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt")' added the Link up based enumeration support failed to update the ICC/OPP vote once link is up. Earlier, the update happens during probe and the endpoints may or may not be enumerated at that time. So the ICC/OPP vote was not guaranteed to be accurate. Now with the Link up based enumeration support, the driver can request the accurate vote based on the PCIe link. So call qcom_pcie_icc_opp_update() in qcom_pcie_global_irq_thread() after enumerating the endpoints. Fixes: 4581403f6792 ("PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt") Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 656d2be9d87f..e4d3366ead1f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1569,6 +1569,8 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) pci_lock_rescan_remove(); pci_rescan_bus(pp->bridge->bus); pci_unlock_rescan_remove(); + + qcom_pcie_icc_opp_update(pcie); } else { dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", status);