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Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 1/8] hw/pci/pci_bus: Introduce PCIBusFlags::PCI_BUS_IO_ADDR0_ALLOWED Date: Mon, 25 Nov 2024 15:05:28 +0100 Message-ID: <20241125140535.4526-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Some machines need PCI buses to allow access at BAR0. Introduce the PCI_BUS_IO_ADDR0_ALLOWED flag and the pci_bus_allows_io_addr0_access() helper, so machines can set this flag during creation, similarly to how they do with the PCI_BUS_EXTENDED_CONFIG_SPACE flag. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci_bus.h | 6 ++++++ hw/pci/pci.c | 1 + 2 files changed, 7 insertions(+) diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 2261312546..5c8b0d2887 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -26,6 +26,7 @@ enum PCIBusFlags { PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002, /* This is a CXL Type BUS */ PCI_BUS_CXL = 0x0004, + PCI_BUS_IO_ADDR0_ALLOWED = 0x0008, }; #define PCI_NO_PASID UINT32_MAX @@ -72,4 +73,9 @@ static inline bool pci_bus_allows_extended_config_space(PCIBus *bus) return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE); } +static inline bool pci_bus_allows_io_addr0_access(PCIBus *bus) +{ + return !!(bus->flags & PCI_BUS_IO_ADDR0_ALLOWED); +} + #endif /* QEMU_PCI_BUS_H */ diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 1416ae202c..de3f93646f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1475,6 +1475,7 @@ pcibus_t pci_bar_address(PCIDevice *d, MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); bool allow_0_address = mc->pci_allow_0_address; + allow_0_address |= pci_bus_allows_io_addr0_access(pci_get_bus(d)); if (type & PCI_BASE_ADDRESS_SPACE_IO) { if (!(cmd & PCI_COMMAND_IO)) { return PCI_BAR_UNMAPPED; From patchwork Mon Nov 25 14:05:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13884935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8B7AD58D4B for ; Mon, 25 Nov 2024 14:08:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tFZjX-0002Ec-H8; Mon, 25 Nov 2024 09:06:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tFZjU-00027K-QR for qemu-devel@nongnu.org; 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Mon, 25 Nov 2024 06:06:25 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433cde8fcdfsm128353385e9.32.2024.11.25.06.06.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:06:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 2/8] hw/ppc/spapr_pci: Set PCI_BUS_IO_ADDR0_ALLOWED flag in host bridge Date: Mon, 25 Nov 2024 15:05:29 +0100 Message-ID: <20241125140535.4526-3-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=philmd@linaro.org; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org See commit e402463073 ("pci: allow 0 address for PCI IO/MEM regions"), all sPAPR machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/spapr.c | 1 - hw/ppc/spapr_pci.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 5c02037c56..8af56bd68a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4600,7 +4600,6 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) mc->default_display = "std"; mc->kvm_type = spapr_kvm_type; machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); - mc->pci_allow_0_address = true; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler = spapr_get_hotplug_handler; hc->pre_plug = spapr_machine_device_pre_plug; diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7e24084673..16f3a18d2e 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1888,6 +1888,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); + bus->flags |= PCI_BUS_IO_ADDR0_ALLOWED; /* * Despite resembling a vanilla PCI bus in most ways, the PAPR * para-virtualized PCI bus *does* permit PCI-E extended config From patchwork Mon Nov 25 14:05:30 2024 Content-Type: text/plain; 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Mon, 25 Nov 2024 06:06:39 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-433b45d40basm199474065e9.21.2024.11.25.06.06.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:06:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 3/8] hw/pci-host/gpex: Allow machines to set PCI_BUS_IO_ADDR0_ALLOWED flag Date: Mon, 25 Nov 2024 15:05:30 +0100 Message-ID: <20241125140535.4526-4-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expose the "allow-io-addr0-accesses" property so machines using a GPEX host bridge can set this flag on the bus. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/gpex.h | 1 + hw/pci-host/gpex.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index dce883573b..8c990bff5f 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -64,6 +64,7 @@ struct GPEXHost { int irq_num[GPEX_NUM_IRQS]; bool allow_unmapped_accesses; + bool allow_io_addr0_accesses; struct GPEXConfig gpex_cfg; }; diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index e9cf455bf5..635467016f 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -32,6 +32,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/irq.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -136,6 +137,9 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq, pci_swizzle_map_irq_fn, s, &s->io_mmio, &s->io_ioport, 0, 4, TYPE_PCIE_BUS); + if (s->allow_io_addr0_accesses) { + pci->bus->flags |= PCI_BUS_IO_ADDR0_ALLOWED; + } pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal); @@ -154,6 +158,8 @@ static Property gpex_host_properties[] = { */ DEFINE_PROP_BOOL("allow-unmapped-accesses", GPEXHost, allow_unmapped_accesses, true), + DEFINE_PROP_BOOL("allow-io-addr0-accesses", GPEXHost, + allow_io_addr0_accesses, false), DEFINE_PROP_UINT64(PCI_HOST_ECAM_BASE, GPEXHost, gpex_cfg.ecam.base, 0), DEFINE_PROP_SIZE(PCI_HOST_ECAM_SIZE, GPEXHost, gpex_cfg.ecam.size, 0), DEFINE_PROP_UINT64(PCI_HOST_PIO_BASE, GPEXHost, gpex_cfg.pio.base, 0), From patchwork Mon Nov 25 14:05:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13884934 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAF0DD58D4B for ; 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Mon, 25 Nov 2024 06:06:55 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fad62fasm10436999f8f.15.2024.11.25.06.06.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:06:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 4/8] hw/arm/virt: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:31 +0100 Message-ID: <20241125140535.4526-5-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org See commit 74de8c3568 ("hw/arm/virt: Allow zero address for PCI IO space"), all ARM Virt machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1a381e9a2b..773df5f04b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1510,6 +1510,8 @@ static void create_pcie(VirtMachineState *vms) MachineClass *mc = MACHINE_GET_CLASS(ms); dev = qdev_new(TYPE_GPEX_HOST); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); ecam_id = VIRT_ECAM_ID(vms->highmem_ecam); @@ -3124,7 +3126,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) #endif mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; - mc->pci_allow_0_address = true; /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ mc->minimum_page_bits = 12; mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; From patchwork Mon Nov 25 14:05:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13884936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75B73D58D4C for ; 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Mon, 25 Nov 2024 06:07:04 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4348e272094sm84910365e9.7.2024.11.25.06.07.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:07:03 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 5/8] hw/arm/sbsa-ref: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:32 +0100 Message-ID: <20241125140535.4526-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=philmd@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All SBSA-Ref machines set this flag in MachineClass. Directly set it to the GPEX bridge. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/sbsa-ref.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index e3195d5449..988a0a236e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -647,6 +647,8 @@ static void create_pcie(SBSAMachineState *sms) int i; dev = qdev_new(TYPE_GPEX_HOST); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); /* Map ECAM space */ @@ -896,7 +898,6 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = ARM_CPU_TYPE_NAME("neoverse-n2"); mc->valid_cpu_types = valid_cpu_types; mc->max_cpus = 512; - mc->pci_allow_0_address = true; mc->minimum_page_bits = 12; mc->block_default_type = IF_IDE; mc->no_cdrom = 1; From patchwork Mon Nov 25 14:05:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13884994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76390D58D4B for ; Mon, 25 Nov 2024 14:09:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tFZkP-0003Vg-06; Mon, 25 Nov 2024 09:07:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tFZkD-0002sv-NR for qemu-devel@nongnu.org; Mon, 25 Nov 2024 09:07:18 -0500 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tFZkB-0006kt-9J for qemu-devel@nongnu.org; Mon, 25 Nov 2024 09:07:16 -0500 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-53de27f1478so1502284e87.2 for ; Mon, 25 Nov 2024 06:07:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732543631; x=1733148431; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CidC1DzNGex4xdl38okZ6dg7MoluQ+zRZMKK1keD2+U=; b=LSk6hKmeFAbz8lC7fHUMSEV0llmA1Cp8ZY4J6nZmBlLMWvk3xCgCWJPEHyJqf8U9+3 l5mU0SMCmTjZPfTTrP7jkkmLGQcxLgv4VJl60KNldTy1Nwfov4U3fkEtZ0P5y+VDPVMT WcS+z4Wmb//yCtynd0PqqFNPAMmSc0QS3xRJCClxeACqgIBoOEySOXnzaFaq6Uz1MyOT IC9Id3mw8rJyy67zgqQOcfVvxb+e/dQP83k8z+UJ3s2GG9BKkWW4nUIWIbQpEVN5Gcwx YPhKmHR8U3S0VBRPNDtvt69pfwHL8+UO68dzSz245AXpqJPVI63Th+IywmkMO+ld/6t+ 6JhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732543631; x=1733148431; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CidC1DzNGex4xdl38okZ6dg7MoluQ+zRZMKK1keD2+U=; b=irm3qcXX2NkGaF7BB3YzCKDnS/+mWeWpQXv2gOuJURV3P2l89kmOrFoyURbyn5Ubdu x0RVEsXzDtCsWpP74Xk97E4IEpAKSLMIru33DZSuIWBWZwKBp1cHw27yzdBS+TsXDtt1 xEQ/pHRyNk033NT1vRQzXip7GjuS8/UybvwgWU7hyh7G9zCwn4eltQOulHDt4dzPTacD Vr3QGNw9PpFdwHHelmsVPRoBsE4ZVb1BCfIK4EYiZK6yGI3NGybiOTJ16URShs1RfEzR Z5mbUHlUtpRz8rz32BFmj79feVdwsZqkApSiFe12k7+98oiP4ELXpwdohRNTsfhH82Lr Ju/g== X-Gm-Message-State: AOJu0YxvHwR0ee+8teFWbj060VjgIKxgiepQmrdHt+NOE2j/lN8qLk04 9UgvcFdR01wR/1Y68lMXOKjctByJ19xbNOby0nyOWKmm9OTi13YBxIfdt/C7ug9MxIV7eFc2Kqy P X-Gm-Gg: ASbGncss5mOxunGQLM2rSJDelKEBdtcU/1XkvqajByTbw0zbh8jmouQyaN0P/O+hiKx kCY2YEcFVY6sXwsF+6QzZmUAVQPFgblCfKQ3KWJq7O3BrdCnCY8lccXf8JvrfGNps+TfRdrG3fx tPvbVyha99roS2Ec/h7pUNbPa4TiLblDzLwvuUXzOjVY2yve6+WiiiOvNCx7dV+bo3l2rPv0hVf A2BeCAFad1MQyLz8cJBLhH+IR9i1HSHKWxCxa/LHyuTaJvxRkskqvdfSxVIJpXfyM7Dhph9 X-Google-Smtp-Source: AGHT+IHTjZk1o1vCUns5HUX/W+2Z1zlVuyiGOcQiiDOXLsF9OPmO54VKYQyfoTkRsHRl+oycxqVYHQ== X-Received: by 2002:a05:6512:b12:b0:53d:cfdb:c65c with SMTP id 2adb3069b0e04-53dd39b62d8mr5978210e87.52.1732543631212; Mon, 25 Nov 2024 06:07:11 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4349ca82957sm63707025e9.33.2024.11.25.06.07.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:07:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 6/8] hw/riscv/virt: Remove pointless GPEX_HOST() cast Date: Mon, 25 Nov 2024 15:05:33 +0100 Message-ID: <20241125140535.4526-7-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=philmd@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org No need to QOM-cast twice, since the intermediate value is not used. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth --- hw/riscv/virt.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 45a8c4f819..2feb851f15 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1140,23 +1140,21 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, dev = qdev_new(TYPE_GPEX_HOST); /* Set GPEX object properties for the virt machine */ - object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_ECAM_BASE, ecam_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_ECAM_SIZE, ecam_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), - PCI_HOST_BELOW_4G_MMIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_BASE, mmio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_BELOW_4G_MMIO_SIZE, mmio_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), - PCI_HOST_ABOVE_4G_MMIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_BASE, high_mmio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_ABOVE_4G_MMIO_SIZE, high_mmio_size, NULL); - object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE, + object_property_set_uint(OBJECT(dev), PCI_HOST_PIO_BASE, pio_base, NULL); - object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE, + object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, pio_size, NULL); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -1189,7 +1187,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); } - GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus; + GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(dev)->bus; return dev; } From patchwork Mon Nov 25 14:05:34 2024 Content-Type: text/plain; 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Mon, 25 Nov 2024 06:07:18 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbee043sm10499689f8f.104.2024.11.25.06.07.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:07:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 7/8] hw/riscv/virt: Set PCI_BUS_IO_ADDR0_ALLOWED flag on GPEX host bridge Date: Mon, 25 Nov 2024 15:05:34 +0100 Message-ID: <20241125140535.4526-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=philmd@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org See commit acead54c78 ("riscv: virt: Allow PCI address 0") all RISCV Virt machines set this flag. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2feb851f15..4e1ce3a423 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1156,6 +1156,8 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, pio_base, NULL); object_property_set_int(OBJECT(dev), PCI_HOST_PIO_SIZE, pio_size, NULL); + object_property_set_bool(OBJECT(dev), "allow-io-addr0-accesses", + true, &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -1803,7 +1805,6 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = TYPE_RISCV_CPU_BASE; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; - mc->pci_allow_0_address = true; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; From patchwork Mon Nov 25 14:05:35 2024 Content-Type: text/plain; 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Mon, 25 Nov 2024 06:07:24 -0800 (PST) Received: from localhost.localdomain ([176.176.170.239]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432f642f15esm210421055e9.0.2024.11.25.06.07.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 25 Nov 2024 06:07:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Daniel Henrique Barboza , Marcin Juszkiewicz , Bin Meng , Alistair Francis , Harsh Prateek Bora , Zhao Liu , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Liu Zhiwei , Palmer Dabbelt , Marcel Apfelbaum , qemu-arm@nongnu.org, "Michael S. Tsirkin" , Nicholas Piggin , Leif Lindholm , Peter Maydell , qemu-riscv@nongnu.org, Weiwei Li , Radoslaw Biernacki , Thomas Huth , Yanan Wang , Eduardo Habkost , qemu-ppc@nongnu.org Subject: [PATCH-for-10.0 8/8] hw/pci/pci: Remove legacy MachineClass::pci_allow_0_address flag Date: Mon, 25 Nov 2024 15:05:35 +0100 Message-ID: <20241125140535.4526-9-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241125140535.4526-1-philmd@linaro.org> References: <20241125140535.4526-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All users of this flag now set the PCI_BUS_IO_ADDR0_ALLOWED PCIBusFlags. Since there are no more users, remove the field in MachineClass. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/boards.h | 1 - hw/pci/pci.c | 5 +---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 36fbb9b59d..66fb2eddd3 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -284,7 +284,6 @@ struct MachineClass { no_floppy:1, no_cdrom:1, no_sdcard:1, - pci_allow_0_address:1, legacy_fw_cfg_order:1; bool is_default; const char *default_machine_opts; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index de3f93646f..d27166dd75 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -45,7 +45,6 @@ #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "hw/hotplug.h" -#include "hw/boards.h" #include "qapi/error.h" #include "qemu/cutils.h" #include "pci-internal.h" @@ -1472,10 +1471,8 @@ pcibus_t pci_bar_address(PCIDevice *d, { pcibus_t new_addr, last_addr; uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); - MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); - bool allow_0_address = mc->pci_allow_0_address; + bool allow_0_address = pci_bus_allows_io_addr0_access(pci_get_bus(d)); - allow_0_address |= pci_bus_allows_io_addr0_access(pci_get_bus(d)); if (type & PCI_BASE_ADDRESS_SPACE_IO) { if (!(cmd & PCI_COMMAND_IO)) { return PCI_BAR_UNMAPPED;