From patchwork Mon Nov 25 16:33:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13885145 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 219EA1B395F; Mon, 25 Nov 2024 16:33:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732552424; cv=none; b=BmQcW+QyFocY5eGlQCRBAtAumNGxfhscDNokaUhcYg4L9UjOPwDnZ1bco0sXYrXh1uPkRAHpEHSu/NKw6H32quS4BSYSvQ3wHqVUeLsryZV9jom8DRY8NW3op5jDlDKz50dArwN0ahHs4+a7d2yMhqCyXEY9SPcyWFg9DWxSqbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732552424; c=relaxed/simple; bh=0b9nQ9EfEGB7VdwrbTXtga4eH63LhXyAMy4kiO4tCFM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=OPONgWxWJAOEiXke/kdALICFSzxCdpwD1aUx5TESP7TV9rRa+akB62MMI/hhMUfAKvkpWykOOk6/VizV4VFXZgoFKPnkd6O5wANZNBCTOaYMZxW9NGeuYkdoF2UHVl8F+BKPvIVXuVrYh81JdUvR31mXw7bJJ8XhiQysgbrfamo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Cnuf99e9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Cnuf99e9" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4APAThuE030525; Mon, 25 Nov 2024 16:33:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= NXwZ4NQeg2R83ST+/G9mV5EeOQPsGKzHl8DwiBSaPf0=; b=Cnuf99e9dIiuKCMx ByPZG/MFdvpLc0f1xFzZXNZfgNCzYXgZAQtz/nVVhE+ZxqYY5nvS7KY9zWxgM9We FaA2fCzLZrDtk9+p6Mf5rbBMTM3+a8naxhrBOPFC2kcJCUYkRhTVP+GgXQ+O20rN VphgkWc7tZ+RVISW2f15sELf6AJkqG0dZIc92wDBkchrdSTgBAWSd/rNTbHgfezX 9yQQjzbuRJOcIreTNx8oRk7CY8d1eX8xznNPflsIG8DyvxmplMfv9shFephqONJY XkTAscM6iiwf+HSFz/aP4NJpWb2MkkYMmNNBjpfMJCA3PwL86l7wHQ7SZYV4h0F9 svOKRQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4334rd5pu2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 16:33:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4APGXXjT012170 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 16:33:33 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 08:33:29 -0800 From: Akhil P Oommen Date: Mon, 25 Nov 2024 22:03:00 +0530 Subject: [PATCH v2 1/2] drm/msm/adreno: Introduce ADRENO_QUIRK_NO_SYSCACHE Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241125-a612-gpu-support-v2-1-b7cc38e60191@quicinc.com> References: <20241125-a612-gpu-support-v2-0-b7cc38e60191@quicinc.com> In-Reply-To: <20241125-a612-gpu-support-v2-0-b7cc38e60191@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , , "Akhil P Oommen" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732552405; l=3061; i=quic_akhilpo@quicinc.com; s=20240726; h=from:subject:message-id; bh=0b9nQ9EfEGB7VdwrbTXtga4eH63LhXyAMy4kiO4tCFM=; b=+SJGYWgq9yxKiYn3ZSxrnMbKX777dwuVlseoMW1ZaZkAjZldfdlIFzAGeJTVAkDl1JU4RKR83 6gYmD9886rPBbAaSRxJhHcnK64UHEe3NrbOszN6vIKa789eyuabTTII X-Developer-Key: i=quic_akhilpo@quicinc.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Gdpj4VDYfPMOG0uBDiVDZ3KD8-5yWVkY X-Proofpoint-GUID: Gdpj4VDYfPMOG0uBDiVDZ3KD8-5yWVkY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 mlxlogscore=924 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250138 There are a few chipsets which don't have system cache a.k.a LLC. Currently, the assumption in the driver is that the system cache availability correlates with the presence of GMU or RPMH, which is not true. For instance, Snapdragon 6 Gen 1 has RPMH and a GPU with a full blown GMU, but doesnot have a system cache. So, introduce an Adreno Quirk flag to check support for system cache instead of using gmu_wrapper flag. Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 3 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +------ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a..5e389f6b8b8a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -682,6 +682,7 @@ static const struct adreno_info a6xx_gpus[] = { }, .gmem = (SZ_128K + SZ_4K), .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_NO_SYSCACHE, .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", .a6xx = &(const struct a6xx_info) { @@ -1331,7 +1332,7 @@ static const struct adreno_info a7xx_gpus[] = { }, .gmem = SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV | ADRENO_QUIRK_NO_SYSCACHE, .init = a6xx_gpu_init, .zapfw = "a702_zap.mbn", .a6xx = &(const struct a6xx_info) { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 019610341df1..a8b928d0f320 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1863,10 +1863,6 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) { - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ - if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) - return; - llcc_slice_putd(a6xx_gpu->llc_slice); llcc_slice_putd(a6xx_gpu->htw_llc_slice); } @@ -1876,8 +1872,7 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, { struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ - if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) + if (a6xx_gpu->base.info->quirks & ADRENO_QUIRK_NO_SYSCACHE) return; /* diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e71f420f8b3a..398be2218110 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -57,6 +57,7 @@ enum adreno_family { #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) #define ADRENO_QUIRK_PREEMPTION BIT(5) +#define ADRENO_QUIRK_NO_SYSCACHE BIT(6) /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. From patchwork Mon Nov 25 16:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 13885146 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA4CA1B4F14; Mon, 25 Nov 2024 16:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732552441; cv=none; b=jjViQSGH2w8pxwkV27tYm1GnBM+H1VlK7zF6TpIisdzdE8K94x58ziCWYAtkKv2lTVb6i/7PTzR5iVvEhCaCBCEbTV6lCR+sv47qBILheo+l82TByIWgYfBx1Zi9tvpUk/Gxul8gpr55tuq7vT1kOLYUhRCuH8SR56EzPJQr8PU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732552441; c=relaxed/simple; bh=96PuKBE5JdD/eHc81yMjwJcQQ3cQw2hp2B/5v603J3Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Awnd8vjxAZYrcWKjoKHTa33tTAR2JlLCCFpyNGYkYJuB331Krr9a4fNYUlB9cBpCKVKdc/DiAodv/6AcZsOWI9J2xj4y3uJo5PSYNwYNX1RW+bNjDH+HkKpp4SlFlCxVHRY46P93xG7yAo9ijsToCoLRWGZX216IqjboiMKuqWY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=W5tdSjzS; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="W5tdSjzS" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4APB1067008874; Mon, 25 Nov 2024 16:33:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pR35uQh0Vz3rmWy5iymN95hYXiXemTleILwxkaib3ac=; b=W5tdSjzSh67jGWDA 7bRbeXbiyl/TuBhIkQEdnKDbVazfAXrwsDmZahah0gyWHX/pERxDAJC67LOK1WvN Gisi/pFCcaAPi24xfuQv0cBZZEpTMe8VMb4fkqS/qBRGwgjTU+ygPLh6jT6d9XE5 Q0AAyamiZhxVfI6CQqODXDOOgvdqYDp9b4dHksBUTknp4kAap99QCjFb3znshzrd KLOOUXkr9L2LeJTTdZfset1KGAoH9xNyqZRZ1cVeu4G5u+QxgMbr0gE3drZ8gAPt +UQJU8MJBaVrTI06tNz5qYfSRjyR/CrTgDj/E1piHK89do6+WPId5txN1xgiGIWL sFPT5w== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 433626df41-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 16:33:39 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4APGXcAi017720 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 16:33:38 GMT Received: from [10.213.111.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 08:33:33 -0800 From: Akhil P Oommen Date: Mon, 25 Nov 2024 22:03:01 +0530 Subject: [PATCH v2 2/2] drm/msm/a6xx: Add support for Adreno 612 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241125-a612-gpu-support-v2-2-b7cc38e60191@quicinc.com> References: <20241125-a612-gpu-support-v2-0-b7cc38e60191@quicinc.com> In-Reply-To: <20241125-a612-gpu-support-v2-0-b7cc38e60191@quicinc.com> To: Rob Clark , Sean Paul , "Konrad Dybcio" , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" CC: , , , , Jie Zhang , Akhil P Oommen , "Konrad Dybcio" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732552405; l=6457; i=quic_akhilpo@quicinc.com; s=20240726; h=from:subject:message-id; bh=UujJJJ2qBaLMZpgFIWVNQifU/7BDaePIDcmsc4etJ1A=; b=W1fGmzxPtB18c8izwU/kDQMHA6OPNZL5EzfeM71zIUbTFB0RLwVZttxCALA+8ajfCsKlGVBzz vmn3Fx2DoZEBDhSG5bMCLkv1Rloyl9/6k5NG3IFKE3lQ5aoEtS1xtFW X-Developer-Key: i=quic_akhilpo@quicinc.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: F_tJt68fNsCtpwMgIX4SILIyNMav6pG2 X-Proofpoint-ORIG-GUID: F_tJt68fNsCtpwMgIX4SILIyNMav6pG2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250138 From: Jie Zhang Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. A612 falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU which is a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement IFPC feature. It doesn't support any other features of a full fledged GMU like clock control, resource voting to rpmh etc. So we need linux clock driver support like other gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. Since there is no benefit with enabling RGMU at the moment, RGMU is entirely skipped in this patch. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 15 +++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 35 ++++++++++++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 11 +++++++--- 3 files changed, 50 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 5e389f6b8b8a..633a966a0c39 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -705,6 +705,21 @@ static const struct adreno_info a6xx_gpus[] = { { 157, 3 }, { 127, 4 }, ), + }, { + .chip_ids = ADRENO_CHIP_IDS(0x06010200), + .family = ADRENO_6XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + }, + .gmem = (SZ_128K + SZ_4K), + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .a6xx = &(const struct a6xx_info) { + .hwcg = a612_hwcg, + .protect = &a630_protect, + .gmu_cgc_mode = 0x00000022, + .prim_fifo_threshold = 0x00080000, + }, }, { .chip_ids = ADRENO_CHIP_IDS(0x06010500), .family = ADRENO_6XX_GEN1, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a8b928d0f320..1af7bbed457a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -504,15 +504,26 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) if (adreno_is_a630(adreno_gpu)) clock_cntl_on = 0x8aa8aa02; - else if (adreno_is_a610(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) clock_cntl_on = 0xaaa8aa82; else if (adreno_is_a702(adreno_gpu)) clock_cntl_on = 0xaaaaaa82; else clock_cntl_on = 0x8aa8aa82; - cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111; - cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555; + if (adreno_is_a612(adreno_gpu)) + cgc_delay = 0x11; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay = 0x111; + else + cgc_delay = 0x10111; + + if (adreno_is_a612(adreno_gpu)) + cgc_hyst = 0x55; + else if (adreno_is_a615_family(adreno_gpu)) + cgc_delay = 0x555; + else + cgc_delay = 0x5555; gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0); @@ -600,6 +611,9 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.ubwc_swizzle = 0x7; } + if (adreno_is_a612(gpu)) + gpu->ubwc_config.highest_bank_bit = 13; + if (adreno_is_a618(gpu)) gpu->ubwc_config.highest_bank_bit = 14; @@ -1165,7 +1179,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ - if (adreno_is_a610(adreno_gpu)) { + if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); } else if (adreno_is_a702(adreno_gpu)) { @@ -1199,7 +1213,7 @@ static int hw_init(struct msm_gpu *gpu) /* Enable fault detection */ if (adreno_is_a730(adreno_gpu) || - adreno_is_a740_family(adreno_gpu)) + adreno_is_a740_family(adreno_gpu) || adreno_is_a612(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff); else if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); @@ -2076,6 +2090,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) if (!ret) msm_devfreq_resume(gpu); + if (!(a6xx_gpu->base.info->quirks & ADRENO_QUIRK_NO_SYSCACHE)) + a6xx_llc_activate(a6xx_gpu); + return ret; } @@ -2115,6 +2132,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) trace_msm_gpu_suspend(0); + if (!(a6xx_gpu->base.info->quirks & ADRENO_QUIRK_NO_SYSCACHE)) + a6xx_llc_deactivate(a6xx_gpu); + msm_devfreq_suspend(gpu); mutex_lock(&a6xx_gpu->gmu.lock); @@ -2480,11 +2500,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) config->info->family == ADRENO_7XX_GEN2 || config->info->family == ADRENO_7XX_GEN3; - a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); if (ret) { - a6xx_llc_slices_destroy(a6xx_gpu); kfree(a6xx_gpu); return ERR_PTR(ret); } @@ -2503,6 +2520,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(ret); } + a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); + /* * For now only clamp to idle freq for devices where this is known not * to cause power supply issues: diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 398be2218110..a6462a255611 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -421,6 +421,11 @@ static inline int adreno_is_a610(const struct adreno_gpu *gpu) return adreno_is_revn(gpu, 610); } +static inline int adreno_is_a612(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x06010200; +} + static inline int adreno_is_a618(const struct adreno_gpu *gpu) { return adreno_is_revn(gpu, 618); @@ -490,9 +495,9 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - - /* TODO: A612 */ - return adreno_is_a610(gpu) || adreno_is_a702(gpu); + return adreno_is_a610(gpu) || + adreno_is_a612(gpu) || + adreno_is_a702(gpu); } /* TODO: 615/616 */