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But boot firmware change the behavor, it is off when boot. So it needs be turn on when it is used. Also it needs be turn off/on when suspend and resume. Add one ref clock for i.MX95 PCIe RC. Increase clocks' maxItems to 5 and keep the same restriction with other compatible string. Signed-off-by: Richard Zhu Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/fsl,imx6q-pcie-common.yaml | 4 +-- .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 1 + .../bindings/pci/fsl,imx6q-pcie.yaml | 25 ++++++++++++++++--- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml index a8b34f58f8f4..cddbe21f99f2 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml @@ -17,11 +17,11 @@ description: properties: clocks: minItems: 3 - maxItems: 4 + maxItems: 5 clock-names: minItems: 3 - maxItems: 4 + maxItems: 5 num-lanes: const: 1 diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index 7bd00faa1f2c..0b3526de1d62 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -118,6 +118,7 @@ allOf: properties: clocks: minItems: 4 + maxItems: 4 clock-names: items: - const: pcie diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 1e05c560d797..4c76cd3f98a9 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -40,10 +40,11 @@ properties: - description: PCIe PHY clock. - description: Additional required clock entry for imx6sx-pcie, imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep. + - description: PCIe reference clock. clock-names: minItems: 3 - maxItems: 4 + maxItems: 5 interrupts: items: @@ -127,7 +128,7 @@ allOf: then: properties: clocks: - minItems: 4 + maxItems: 4 clock-names: items: - const: pcie @@ -140,11 +141,10 @@ allOf: compatible: enum: - fsl,imx8mq-pcie - - fsl,imx95-pcie then: properties: clocks: - minItems: 4 + maxItems: 4 clock-names: items: - const: pcie @@ -200,6 +200,23 @@ allOf: - const: mstr - const: slv + - if: + properties: + compatible: + enum: + - fsl,imx95-pcie + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: pcie + - const: pcie_bus + - const: pcie_phy + - const: pcie_aux + - const: ref + unevaluatedProperties: false examples: From patchwork Tue Nov 26 07:56:54 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3nybBDwzCO7JhkoDtOYNDVVH4m2FQ+yrzdOFaWdik/Z6VXV/lQCT5slB5nEs3jrzFnfcrakzrsepx4+gzexPAdJMtnI204ivKNFnx7U3c/Sa2L6k5SbXuQSazoNTtVEAQl246xp03/lfyVjvCChVZrzSoA0FfPm7zhaHjz1S7Dr4eoo7GFXw4BVzIRE3ha+TNqztSpXudf58A0qd+5fuu2AJLa6EeoWnJ4XlefH8KSVATtoGl3Tv+9gcJh6TVvl9LVFFLpvP8DHPQg73DWMZXW08FttIljcvVj/uE1RQzXaWOplGAZrcElZ+QVDHj/STUd5pwkVOHu1DXhx/k/KheuFn7R1qQpuJplN4ZI/fPQFgvxeCxBwn9e29xq+YxwOrMfgTp796AQexEzz4cPLV9OE4RSP3zPnP6qiwGspVq6j6QoWTteai/6pcGo5X5qXwJXWY/ljBXEFutt+SBz09XSCbMTxAd7ayR7WNRf+GB3bfmNywDRCykwURyaIyN9k0pk5P1PXtwJ2T5THWUgOQjQK++Q6BPELztFW27hvLBDa13OtERgqyij9Kvf72Lrx9HFYIxMLTAlc0dWYYmg/G0/P635Em5RPDvu+e4BRh3ucrDTQO+upV7Q/mwQws6clOHIuhvRHOB92dXO2x+hdu62oGmIjuKD3hc1i8S3x2ze0Ee1IxB2cMH+38t0Tgu5shhNZidbJxkAgri6bmiJ4WUiy4cKY08SKh/16kaMEXymI+6cknHGsglVQIGVFSuuB0iSVJiE2xoKL10EDy0WLJhp1VyhSkTlMWP9qwWSGDWO78+NrhVWAcZV7jeN+Rwlkmx2/Sgt7DeyEGSzYeYuUNCBfpQnRxb7jRVX+DORp0X7XQu64W4HKrocH/5+/lJeE4OPkgX4EUKvXf3sN7HuPRX2ELvrtnq3wzLQP99Q83FmWS7w73GNUhwqFwZUr8vgpoHMEYLvPTj6FVNv/I6JwzOgHCBO1XOS6faxhEI62TcV/Dktfits/cFY16NwjCriCm/OTKes1NlDmD9iTjh04ARHim7bJcXHq92V29cgCwB8hh0FeN+FGXiljzekQO9ePbZ6+R/zUnjb60MIj860Ne+bwaH32nNNjg7QEoO/THD7rqHiiATlCfFveNJ8RO/Ss4Mo7TF6ISL4a3sd5zXEMbWoenNKEILsAtAyUHUhAnmI/BapE0rwihtGAmLRa/d05PmhVyLxIe6cDA4AZ5ovsl98vwYbV4ylvOUyW6iHlPZOtaj3CoUnKpS45Y7ln0R17DvUBoLWzD1i3EcfLOnvx9H3g/K/9OtD1eT+FAWO7DSEjuvyUlGIBVFWSbiR5Ro8q4IMol1dKsFazHp7VIUQCNPl7no8yPU2RoXD3jwrgdG0QQnzVCCY+ce1RAnfCiAirGZkzqBk5dAfLo+x2bpEp0ff+yMvXBCJOdvHU2afqElkEir8XuxMzoEwKPIpzthz5dzOwc3Q+di0rJPO2BdpbLVXoqDUlKkmhhQyp7dts1s2Ub4g4pIMQsigTtXDHZdSnighc/MY9QfOwv2CHlqE+q564do0bPA1M3eZHQ+/e4N11sUw9WvkPtP7k0X0WRRoVb X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b5f351c-bd11-4320-e658-08dd0df003e2 X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 07:57:46.6986 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 4qfTOnJpxBnoxku4IrSgdK4nFJwbo9XWeLBha4Hv++bgQx128MxBBkRK8Lg6EDobYzAHhOmFUBFjK9YZGiAY9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR04MB9401 Add "ref" clock to enable reference clock. To avoid breaking DT backwards compatibility, i.MX95 REF clock might be optional. Use devm_clk_get_optional() to fetch i.MX95 PCIe optional clocks in driver. If use external clock, ref clock should point to external reference. If use internal clock, CREF_EN in LAST_TO_REG controls reference output, which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 385f6323e3ca..f7e928e0a018 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const char *gpr; const char * const *clk_names; const u32 clks_cnt; + const u32 clks_optional_cnt; const u32 ltssm_off; const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; @@ -1306,9 +1307,8 @@ static int imx_pcie_probe(struct platform_device *pdev) struct device_node *np; struct resource *dbi_base; struct device_node *node = dev->of_node; - int ret; + int i, ret, req_cnt; u16 val; - int i; imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); if (!imx_pcie) @@ -1358,9 +1358,13 @@ static int imx_pcie_probe(struct platform_device *pdev) imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; /* Fetch clocks */ - ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks); + req_cnt = imx_pcie->drvdata->clks_cnt - imx_pcie->drvdata->clks_optional_cnt; + ret = devm_clk_bulk_get(dev, req_cnt, imx_pcie->clks); if (ret) return ret; + imx_pcie->clks[req_cnt].clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(imx_pcie->clks[req_cnt].clk)) + return PTR_ERR(imx_pcie->clks[req_cnt].clk); if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); @@ -1509,6 +1513,7 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; +static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"}; static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { @@ -1623,8 +1628,9 @@ static const struct imx_pcie_drvdata drvdata[] = { [IMX95] = { .variant = IMX95, .flags = IMX_PCIE_FLAG_HAS_SERDES, - .clk_names = imx8mq_clks, - .clks_cnt = ARRAY_SIZE(imx8mq_clks), + .clk_names = imx95_clks, + .clks_cnt = ARRAY_SIZE(imx95_clks), + .clks_optional_cnt = 1, .ltssm_off = IMX95_PE0_GEN_CTRL_3, .ltssm_mask = IMX95_PCIE_LTSSM_EN, .mode_off[0] = IMX95_PE0_GEN_CTRL_1, From patchwork Tue Nov 26 07:56:55 2024 Content-Type: text/plain; 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Upsteam dts's have not enabled EP function. So no function broken for old upsteam's dtb. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index f7e928e0a018..81f1f68ccc14 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1114,7 +1114,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct platform_device *pdev) { int ret; - unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; struct dw_pcie *pci = imx_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; @@ -1124,28 +1123,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, ep = &pci->ep; ep->ops = &pcie_ep_ops; - switch (imx_pcie->drvdata->variant) { - case IMX8MQ_EP: - case IMX8MM_EP: - case IMX8MP_EP: - pcie_dbi2_offset = SZ_1M; - break; - default: - pcie_dbi2_offset = SZ_4K; - break; - } - - pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; - - /* - * FIXME: Ideally, dbi2 base address should come from DT. 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The previous code is incorrect although yielding the correct result. Fix by removing IMX7D from the switch case branch. Fixes: 2d8ed461dbc9 ("PCI: imx6: Add support for i.MX8MQ") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 81f1f68ccc14..3538440601a7 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1367,7 +1367,6 @@ static int imx_pcie_probe(struct platform_device *pdev) switch (imx_pcie->drvdata->variant) { case IMX8MQ: case IMX8MQ_EP: - case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) imx_pcie->controller_id = 1; break; From patchwork Tue Nov 26 07:56:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 13885543 Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazon11013041.outbound.protection.outlook.com [40.107.162.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAF131AF4EE; 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Fixes: 9b3fe6796d7c ("PCI: imx6: Add code to support i.MX7D") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 3538440601a7..413db182ce9f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -776,6 +776,7 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { reset_control_deassert(imx_pcie->pciephy_reset); + reset_control_deassert(imx_pcie->apps_reset); if (imx_pcie->drvdata->core_reset) imx_pcie->drvdata->core_reset(imx_pcie, false); From patchwork Tue Nov 26 07:56:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 13885544 Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011060.outbound.protection.outlook.com [52.101.70.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 989441B2192; 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Received: from AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) by PAXPR04MB8489.eurprd04.prod.outlook.com (2603:10a6:102:1dd::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8182.20; Tue, 26 Nov 2024 07:58:20 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%4]) with mapi id 15.20.8182.019; Tue, 26 Nov 2024 07:58:20 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu , Frank Li Subject: [PATCH v7 06/10] PCI: imx6: Fix the missing reference clock disable logic Date: Tue, 26 Nov 2024 15:56:58 +0800 Message-Id: <20241126075702.4099164-7-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241126075702.4099164-1-hongxing.zhu@nxp.com> References: <20241126075702.4099164-1-hongxing.zhu@nxp.com> X-ClientProxiedBy: SI1PR02CA0060.apcprd02.prod.outlook.com (2603:1096:4:1f5::17) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|PAXPR04MB8489:EE_ X-MS-Office365-Filtering-Correlation-Id: 2aa0831c-1c1b-4226-ac01-08dd0df0181e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|7416014|376014|1800799024|366016|38350700014|921020; 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Fixes: d0a75c791f98 ("PCI: imx6: Factor out ref clock disable to match enable") Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 413db182ce9f..ab2c97a8c327 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -599,10 +599,9 @@ static int imx_pcie_attach_pd(struct device *dev) static int imx6sx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - if (enable) - regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); return 0; } @@ -631,19 +630,20 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) { int offset = imx_pcie_grp_offset(imx_pcie); - if (enable) { - regmap_clear_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); - regmap_set_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); - } - + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, + IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); return 0; } static int imx7d_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - if (!enable) - regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); return 0; } From patchwork Tue Nov 26 07:56:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhu X-Patchwork-Id: 13885545 Received: from OSPPR02CU001.outbound.protection.outlook.com (mail-norwayeastazon11013069.outbound.protection.outlook.com [40.107.159.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E47CF1B2192; Tue, 26 Nov 2024 07:58:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.159.69 ARC-Seal: i=2; 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Tue, 26 Nov 2024 07:58:29 +0000 Received: from AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93]) by AS8PR04MB8676.eurprd04.prod.outlook.com ([fe80::28b2:de72:ad25:5d93%4]) with mapi id 15.20.8182.019; Tue, 26 Nov 2024 07:58:29 +0000 From: Richard Zhu To: l.stach@pengutronix.de, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, frank.li@nxp.com, s.hauer@pengutronix.de, festevam@gmail.com Cc: imx@lists.linux.dev, kernel@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Zhu , Frank Li Subject: [PATCH v7 07/10] PCI: imx6: Remove imx7d_pcie_init_phy() function Date: Tue, 26 Nov 2024 15:56:59 +0800 Message-Id: <20241126075702.4099164-8-hongxing.zhu@nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20241126075702.4099164-1-hongxing.zhu@nxp.com> References: <20241126075702.4099164-1-hongxing.zhu@nxp.com> X-ClientProxiedBy: SI1PR02CA0060.apcprd02.prod.outlook.com (2603:1096:4:1f5::17) To AS8PR04MB8676.eurprd04.prod.outlook.com (2603:10a6:20b:42b::10) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS8PR04MB8676:EE_|PAXPR04MB8489:EE_ X-MS-Office365-Filtering-Correlation-Id: 9660762d-6c8d-4228-a002-08dd0df01d2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|52116014|7416014|376014|1800799024|366016|38350700014|921020; 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So remove it. Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index ab2c97a8c327..743a71789d17 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -394,13 +394,6 @@ static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) return 0; } -static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) -{ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); - - return 0; -} - static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -1554,7 +1547,6 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx6q_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx7d_pcie_init_phy, .enable_ref_clk = imx7d_pcie_enable_ref_clk, .core_reset = imx7d_pcie_core_reset, }, From patchwork Tue Nov 26 07:57:00 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WuEhwjlj1xnlJOWD7f97WU8QFJNzoNQp7AF9Z6K8FZqIZVx3chURSzK6qc+KioydpZyXgUg2MFW3Sm9xLgEGH2xeQq/+wLgcess5n8SJ3SN0zqLR31En7XO1LFqq2HFfwJV75Ghj3u6JMLqvL01GAS7c807Jc9srRyfPWuUnvGEhAlTDrGxNc6/FuEM0VXhWwcACwYHhjiyOA4oCddGgEadhkDWhBupFxVuiZlFAH4CmqaoyDGYxAiVEgZQFfkidtnwFzf63d/99u4L9Wda0kIjaRm08gPqRkNKmNbX/7GKSLoNqKMCNC2QsA6WIPFsW9DXHvvNYjVwVR+lQdWYBbK7Of2okAuf2uzEDxc+WkgTGk38tVS36DyfPFS5U/A+LzggQwz7Faz3RBMi8b4iNljPvKUiTAqzwVLu65Ua0aaZMAzNBohhQh1/LUIKV99FFqpDVADuDJnowfXZB9hmv0k1akVQQBGhhPHzP7+jGPRzOYoxyJypbD3JmL3aH5JCad4CK/6yDPsln+zdc1MNFphTtAxnNFo6swlGs4amIcLPJRr3GynDDS+J3PYUndnjYrj17P4sa6/KPIpRnHn8RSzQ051MtnhgkGT6GM6YwW5rX7breKH6XKUrJJlP+w3H6AaMFqq0jX2ZnkVJUHtZNxgUxfNJICA6rT9E/8aq2POFyzVnKUsYXh4hTimepBiq5loqQDzc6f3S0Ql1RV93YY0To5Rw9uCd/ap1eelY5EH9XixPyu19cnxj57mVCUif8ZVU6Hi+S56AAwqB+u7KU8Woh/TPRpBZXPsvbYtalTzcq9wthMRQqD306MT9Ehvmn5sHcqdujwti9Ht3pL/5+0+L3jlBZO2uFt761WQUlvvDmPXKz5dLjfINHyLBg1OuG2GojdU2smMDfLrojMPjOApdv4v7Mb1YAbcO/pGzi9BvVzBESPwhgzYmlBZJlQpo/Zpo2/1k/iK9ksbyw4LHMasTIivZfFgMkW39ngmdkkV7kTq7NiUJtqZi05X+j/tmuSGvvvVMi7s0KB2D06rUJvuU+xlMv3JgkApV5Sy3cpf7UTubhYWHrwHUjz4W/cmrY5JeSfhFk1pVOXeJoZdtbLQAlikWEDnGs0cibTK501ZUyKTg9MxFAowIgQ5gdVJecp5xIRqUPdhWS6SG0gFeNQRbvYOJGtfCBCFMvQ9Rid23gKs/J514NSdO6+PYv2E5nQMatJvmKHLHKpo1u7A65BoUg12gZ1QKHm/rWS8J3MSrEFYAwe4JvW+1FMF/sXu99sfh4jZP3cvaKb4zVuuqvz6ba0zGy4d8WhDQblPjNDkmwH3ljHSH9/3d1UMcWMm78bAQHQccghu18PGShqpqO+x1Cv8ivVAcM7IZ7/s//b4VQxZQoLIJS+53HAGSVtTXrGh1MfseuFeAHndB4jwKdjSuvfQnRA2ZYBC+2xi4SGx+uz2GocH4ijvtXgQ0oSSONKajY/gNNasefL6RKGRFnhm/MGknR0oVfqyE61zzPq2U6+rGMXmzFtK2ppCPNyRAbW8f1kliD4I8/t/I7hzv8knLwxC2yyQ8aYyElfM7+qoAvPS4t116rXrf6MMTma5lk X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9600350a-d2ba-45b9-2f49-08dd0df02219 X-MS-Exchange-CrossTenant-AuthSource: AS8PR04MB8676.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2024 07:58:37.4304 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q8Wx+AYziR1x9uLuEKsv/bvWp0Fj3P9weS5nQA97eZmAIEB4kGfZIZHbJe1CH+6BXIhIUYFNG19GFlDmCwuwnA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR04MB8489 From: Frank Li Call common dwc suspend/resume function. Use dwc common iATU method to send out PME_TURN_OFF message. In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 register is reserved. So the generic DWC implementation of sending the PME_Turn_Off message using a dummy MMIO write cannot be used. Use previouse method to kick off PME_TURN_OFF MSG for these platforms. SRC(System Reset Control) interface is used to toggle 'turnoff_reset' to send PME_TURN_OFF and since the DWC implementation is used, it is not needed now. Replace the imx_pcie_stop_link() and imx_pcie_host_exit() by dw_pcie_suspend_noirq() in imx_pcie_suspend_noirq(). Since dw_pcie_suspend_noirq() already does these, see below call stack: dw_pcie_suspend_noirq() dw_pcie_stop_link(); imx_pcie_stop_link(); pci->pp.ops->deinit(); imx_pcie_host_exit(); Replace the imx_pcie_host_init(), dw_pcie_setup_rc() and imx_pcie_start_link() by dw_pcie_resume_noirq() in imx_pcie_resume_noirq(). Since dw_pcie_resume_noirq() already does these, see below call stack: dw_pcie_resume_noirq() pci->pp.ops->init(); imx_pcie_host_init(); dw_pcie_setup_rc(); dw_pcie_start_link(); imx_pcie_start_link(); Signed-off-by: Frank Li Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 96 ++++++++++----------------- 1 file changed, 35 insertions(+), 61 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 743a71789d17..87dac4ac9d10 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -33,6 +33,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) @@ -112,19 +113,18 @@ struct imx_pcie_drvdata { int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); int (*core_reset)(struct imx_pcie *pcie, bool assert); + const struct dw_pcie_host_ops *ops; }; struct imx_pcie { struct dw_pcie *pci; struct gpio_desc *reset_gpiod; - bool link_is_up; struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; struct reset_control *pciephy_reset; struct reset_control *apps_reset; - struct reset_control *turnoff_reset; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; u32 tx_deemph_gen2_6db; @@ -903,13 +903,11 @@ static int imx_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } - imx_pcie->link_is_up = true; tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; err_reset_phy: - imx_pcie->link_is_up = false; dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); @@ -1014,9 +1012,31 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } +/* + * In Old DWC implementations, PCIE_ATU_INHIBIT_PAYLOAD bit in iATU Ctrl2 + * register is reserved. So the generic DWC implementation of sending the + * PME_Turn_Off message using a dummy MMIO write cannot be used. + */ +static void imx_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); + regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); + + usleep_range(PCIE_PME_TO_L2_TIMEOUT_US/10, PCIE_PME_TO_L2_TIMEOUT_US); +} + static const struct dw_pcie_host_ops imx_pcie_host_ops = { .init = imx_pcie_host_init, .deinit = imx_pcie_host_exit, + .pme_turn_off = imx_pcie_pme_turn_off, +}; + +static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops = { + .init = imx_pcie_host_init, + .deinit = imx_pcie_host_exit, }; static const struct dw_pcie_ops dw_pcie_ops = { @@ -1143,43 +1163,6 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, return 0; } -static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) -{ - struct device *dev = imx_pcie->pci->dev; - - /* Some variants have a turnoff reset in DT */ - if (imx_pcie->turnoff_reset) { - reset_control_assert(imx_pcie->turnoff_reset); - reset_control_deassert(imx_pcie->turnoff_reset); - goto pm_turnoff_sleep; - } - - /* Others poke directly at IOMUXC registers */ - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, - IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); - break; - default: - dev_err(dev, "PME_Turn_Off not implemented\n"); - return; - } - - /* - * Components with an upstream port must respond to - * PME_Turn_Off with PME_TO_Ack but we can't check. - * - * The standard recommends a 1-10ms timeout after which to - * proceed anyway as if acks were received. - */ -pm_turnoff_sleep: - usleep_range(1000, 10000); -} - static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; @@ -1203,7 +1186,6 @@ static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) static int imx_pcie_suspend_noirq(struct device *dev) { struct imx_pcie *imx_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx_pcie->pci->pp; if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; @@ -1218,9 +1200,7 @@ static int imx_pcie_suspend_noirq(struct device *dev) imx_pcie_assert_core_reset(imx_pcie); imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); } else { - imx_pcie_pm_turnoff(imx_pcie); - imx_pcie_stop_link(imx_pcie->pci); - imx_pcie_host_exit(pp); + return dw_pcie_suspend_noirq(imx_pcie->pci); } return 0; @@ -1230,7 +1210,6 @@ static int imx_pcie_resume_noirq(struct device *dev) { int ret; struct imx_pcie *imx_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx_pcie->pci->pp; if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; @@ -1250,17 +1229,12 @@ static int imx_pcie_resume_noirq(struct device *dev) ret = dw_pcie_setup_rc(&imx_pcie->pci->pp); if (ret) return ret; - imx_pcie_msi_save_restore(imx_pcie, false); } else { - ret = imx_pcie_host_init(pp); + ret = dw_pcie_resume_noirq(imx_pcie->pci); if (ret) return ret; - imx_pcie_msi_save_restore(imx_pcie, false); - dw_pcie_setup_rc(pp); - - if (imx_pcie->link_is_up) - imx_pcie_start_link(imx_pcie->pci); } + imx_pcie_msi_save_restore(imx_pcie, false); return 0; } @@ -1291,11 +1265,15 @@ static int imx_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; - pci->pp.ops = &imx_pcie_host_ops; imx_pcie->pci = pci; imx_pcie->drvdata = of_device_get_match_data(dev); + if (imx_pcie->drvdata->ops) + pci->pp.ops = imx_pcie->drvdata->ops; + else + pci->pp.ops = &imx_pcie_host_dw_pme_ops; + /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1368,13 +1346,6 @@ static int imx_pcie_probe(struct platform_device *pdev) break; } - /* Grab turnoff reset */ - imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); - if (IS_ERR(imx_pcie->turnoff_reset)) { - dev_err(dev, "Failed to get TURNOFF reset control\n"); - return PTR_ERR(imx_pcie->turnoff_reset); - } - if (imx_pcie->drvdata->gpr) { /* Grab GPR config register range */ imx_pcie->iomuxc_gpr = @@ -1454,6 +1425,7 @@ static int imx_pcie_probe(struct platform_device *pdev) if (ret < 0) return ret; } else { + pci->pp.use_atu_msg = true; ret = dw_pcie_host_init(&pci->pp); if (ret < 0) return ret; @@ -1519,6 +1491,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .init_phy = imx6sx_pcie_init_phy, .enable_ref_clk = imx6sx_pcie_enable_ref_clk, .core_reset = imx6sx_pcie_core_reset, + .ops = &imx_pcie_host_ops, }, [IMX6QP] = { .variant = IMX6QP, @@ -1536,6 +1509,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .init_phy = imx_pcie_init_phy, .enable_ref_clk = imx6q_pcie_enable_ref_clk, .core_reset = imx6qp_pcie_core_reset, + .ops = &imx_pcie_host_ops, }, [IMX7D] = { .variant = IMX7D, From patchwork Tue Nov 26 07:57:01 2024 Content-Type: text/plain; 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Signed-off-by: Richard Zhu Reviewed-by: Manivannan Sadhasivam Reviewed-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 87dac4ac9d10..852b34572bb8 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1527,7 +1527,8 @@ static const struct imx_pcie_drvdata drvdata[] = { [IMX8MQ] = { .variant = IMX8MQ, .flags = IMX_PCIE_FLAG_HAS_APP_RESET | - IMX_PCIE_FLAG_HAS_PHY_RESET, + IMX_PCIE_FLAG_HAS_PHY_RESET | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), @@ -1564,13 +1565,15 @@ static const struct imx_pcie_drvdata drvdata[] = { }, [IMX8Q] = { .variant = IMX8Q, - .flags = IMX_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .clk_names = imx8q_clks, .clks_cnt = ARRAY_SIZE(imx8q_clks), }, [IMX95] = { .variant = IMX95, - .flags = IMX_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .clk_names = imx95_clks, .clks_cnt = ARRAY_SIZE(imx95_clks), .clks_optional_cnt = 1, From patchwork Tue Nov 26 07:57:02 2024 Content-Type: text/plain; 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Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 25 ++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 03661e76550f..9951d2c84799 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -236,6 +236,13 @@ clk_ext1: clock-ext1 { clock-output-names = "clk_ext1"; }; + clk_sys100m: clock-sys100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "clk_sys100m"; + }; + sai1_mclk: clock-sai-mclk1 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -1473,6 +1480,14 @@ smmu: iommu@490d0000 { }; }; + hsio_blk_ctl: syscon@4c0100c0 { + compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; + reg = <0x0 0x4c0100c0 0x0 0x4>; + #clock-cells = <1>; + clocks = <&clk_sys100m>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + pcie0: pcie@4c300000 { compatible = "fsl,imx95-pcie"; reg = <0 0x4c300000 0 0x10000>, @@ -1500,8 +1515,9 @@ pcie0: pcie@4c300000 { clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1567,8 +1583,9 @@ pcie1: pcie@4c380000 { clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;