From patchwork Tue Nov 26 09:20:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885620 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA1FF19A2B0 for ; Tue, 26 Nov 2024 09:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612871; cv=none; b=VgdJ7PErg02VHgF4lFQy5q65Hzvep5KVlFBprIB7e7bRRYLKn6HHqlNTsK9QfrBXekjFHUaUoqJanFhjvXRylB7A+q7Gr6+qH+Q10P8JS82jfLuOaCDJlcQhmZjnyiysRsHj1gmwz+ayGunFZjRe6X0tJOcziI5X9sDXDYZ/e0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612871; c=relaxed/simple; bh=V/DGxPq334std3OZDw1Q13cvXzTcQ8HKIYrcq1YIJz8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LhDmwVbMuuOnMeocmlb5eSItRbURV2obq0hbMJkZ9/H5pHElbQjPIG8mUzNu4Qb2vxYMMcKjPHJ/WFevE5xf6YTk/qnMwGHWecx+gWzer68umaSWCHpBqnyBJBDIUelV8/W+PUA0gfW5ys129p5fVpxgH2o0IPeVXaZccgmxqjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=ecJ7nixf; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="ecJ7nixf" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-382588b7a5cso3426332f8f.3 for ; Tue, 26 Nov 2024 01:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612867; x=1733217667; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oQlGMIlStcYoMIShuvfUaEr5YyWxZQ2PUL1/5BTbV6c=; b=ecJ7nixfA9OMlsZb5dKVxfMvfwF7PKkDh5DkWFugpB4EsQvjgWSgc3jhd1U+x21D87 QwdsGbBIMykVGFzXhVasqjUgxA3ZosL+0hTJjJcN58OA/T8vPzjfqlnAmk53/VzAwv/5 Pf3tR29uewY1nGXArtHy2jql+0OdIqRm0G3GtViX/9uBqUvHXnBBPxQ+XCgeZgAkSGoz R47QCkotM647N1hHa4kbpDKmOIxWIS1PuzOx1jio5T5scBDHvo0r905IYD0ITSD6kNo9 gMDWbPA7TePcSu4I1jCra3+zkzq2J/8ugnuQJAOxY1Nc69ZpwQkNcMIosU4NjstiMYlK tc0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612867; x=1733217667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oQlGMIlStcYoMIShuvfUaEr5YyWxZQ2PUL1/5BTbV6c=; b=J8ZnwfXX+M8SaX8ZYZReSOX+EfWpbpDtoarP3A0rYHM1CBFIIqtxDfH3C3sXR7sZwa aB9ne97lCxUl1zRDJKaLNK529baGYNWk4ecjAgw3gwnSSJLjWZLY1DpeqvnbGxcfTkS6 iRTDipqgGZrt/lYIf5jiCAebMNaWmSM4HPKw3AOlip3/jOpsDs//Qc46e/bD9/zlOcSz poAa+5MOKNPFKkRhcFRuLP54rbrRAPgU4z30myRs6Wdzo/89Esgu9bi0X2cWe58cetim oypI9ACauxK/koZtlcEuSnnxtrwR9EthFBpFoTmIacmYp2RHMe08h082mG8FZpG6RLRU toAw== X-Forwarded-Encrypted: i=1; AJvYcCUC7cXnasv2aXULnKK61jH+iHkunzNmyaqUJmHtiMm1CPZKkcIwF10RiWxglQUzXwXGVBvJrlJLlLd14t+GQIUflw==@vger.kernel.org X-Gm-Message-State: AOJu0Yy2qIVi9dS+/7glsBOzpv42JmCB7S5ZkoBDEM6wE0xsHg1aPSR5 UiaYeeiX4oI7naIp65fIW9/zM44mPqKZLKqIP+inSCUdZPHdgtIc2/I9YH1fDhg= X-Gm-Gg: ASbGnct24ZHOrcGbzM42RrqqW90jZe6KykiilEECVMvUEBVRDRqCBBW1xA9//r7yaFs j8Cj388f9/EmmAedzQ4kmTskASqDaQF57YGkw83eZIsyNiylthgYMeZNcVtKSVSNd3C7PwKWMNk ZD3llihB48v0s3BmD4LHQclinsXWUoVDytrCw/D7IEMCevIH4VpTSFQngZ8wJGxEReT4F9xwgIy VthwvTjlspYVgNBgwIU5VFN7LQd74kQjwo3vdAP2Xj18ylFbafAoqgJs4DE1uKZmNYKxkMGL9Xv 1fo= X-Google-Smtp-Source: AGHT+IGG2IQ+U6IJTaeTyTNQI6LGmc4AjJAHShu01o6855LNNPFEdIbHv35w4G1l6XXNHmNrrqLTjw== X-Received: by 2002:a5d:5984:0:b0:382:415e:a144 with SMTP id ffacd0b85a97d-382608a4b7bmr12377286f8f.0.1732612867211; Tue, 26 Nov 2024 01:21:07 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:06 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 01/15] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Add #renesas,sysc-signal-cells Date: Tue, 26 Nov 2024 11:20:36 +0200 Message-Id: <20241126092050.1825607-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S system controller (SYSC) has registers to control signals that are routed to various IPs. These signals must be controlled during configuration of the respective IPs. One such signal is the USB PWRRDY, which connects the SYSC and the USB PHY. This signal must to be controlled before and after the power to the USB PHY is turned off/on. Other similar signals include the following (according to the RZ/G3S hardware manual): * PCIe: - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B register - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register * SPI: - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA register * I2C/I3C: - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers (x=0..3) - af_bypass I3C signal controlled through SYS_I3C_CFG register * Ethernet: - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG registers (x=0..1) Add #renesas,sysc-signal-cells DT property to allow different SYSC signals consumers to manage these signals. The goal is to enable consumers to specify the required access data for these signals (through device tree) and let their respective drivers control these signals via the syscon regmap provided by the system controller driver. For example, the USB PHY will describe this relation using the following DT property: usb2_phy1: usb-phy@11e30200 { // ... renesas,sysc-signal = <&sysc 0xd70 0x1>; // ... }; Along with it, add the syscon to the compatible list as it will be requested by the consumer drivers. The syscon was added to the rest of system controller variants as these are similar with RZ/G3S and can benefit from the implementation proposed in this series. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new .../soc/renesas/renesas,rzg2l-sysc.yaml | 23 ++++++++++++++----- 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml index 4386b2c3fa4d..90f827e8de3e 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml @@ -19,11 +19,13 @@ description: properties: compatible: - enum: - - renesas,r9a07g043-sysc # RZ/G2UL and RZ/Five - - renesas,r9a07g044-sysc # RZ/G2{L,LC} - - renesas,r9a07g054-sysc # RZ/V2L - - renesas,r9a08g045-sysc # RZ/G3S + items: + - enum: + - renesas,r9a07g043-sysc # RZ/G2UL and RZ/Five + - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L + - renesas,r9a08g045-sysc # RZ/G3S + - const: syscon reg: maxItems: 1 @@ -42,9 +44,17 @@ properties: - const: cm33stbyr_int - const: ca55_deny + "#renesas,sysc-signal-cells": + description: + The number of cells needed to configure a SYSC controlled signal. First + cell specifies the SYSC offset of the configuration register, second cell + specifies the bitmask in register. + const: 2 + required: - compatible - reg + - "#renesas,sysc-signal-cells" additionalProperties: false @@ -53,7 +63,7 @@ examples: #include sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; + compatible = "renesas,r9a07g044-sysc", "syscon"; reg = <0x11020000 0x10000>; interrupts = , , @@ -61,4 +71,5 @@ examples: ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; }; From patchwork Tue Nov 26 09:20:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885621 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCAC31B85C2 for ; Tue, 26 Nov 2024 09:21:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; cv=none; b=E2ppTkCQHOLWO7v14dK3YgS4whWRgUkN+mR8hBChiOjRZ2kTyDFgYdC+MbUzo+0lwjyhjD+yGpT9j6mblzTSd2B973ruHu63cRhLH/a7LRbN/2Qr5QtWIIv1n2kjdq2pq+gVD32BTxc6I3WCH8G9D+7ShWmo5KFD7E4urjK5bb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612873; c=relaxed/simple; bh=EqyCCrGqEJwg3+iLhcuJrpOwueTe8BY2KShqIIlG8ZY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F8HmXr6mAT1vYhop+IQibB/vgjZK45fzwTB9iAsUxovKzbgjaAfgTdiFEkfwzttBuiH/IwnVq18VYNIIVnC7LJjZJUWO16lpoDYKw9OFiCAWHMEm6daCbP245e8X2QWD2D2dvl8jbN+5xNxIGr9iaWHE8UlO2y/056aBFkXtNzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=WpmWgXyr; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="WpmWgXyr" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43155abaf0bso49707365e9.0 for ; Tue, 26 Nov 2024 01:21:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612869; x=1733217669; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5vCamtieJ1Any0nEDdOYudZWF6ph91xcO8/i+h+/3r0=; b=WpmWgXyrfuIkNdGBirDiL0o9+2F5c/OS9QxGPfWXRN14eKKiLmwatebdp8nz/Nq1hk OyohD5xO9pkHRT7odfi4tx+HukktcrVdtHGQQAdH3HQP3SaeSy2B3ynG/nH/1CXe6IG7 WNgEHOhQzJn/cDHa7kS8zUo+PHqz05tblKrdgTJFguG/Xn4Bf4PfUo7KzLHmDhdQ87Yg 1ckjGVQmD+DniYnpUUUeBd8Rj6DmQaXRmc+MteZ4bKIuM0KWYgCfaPoDikTp75gZIF0/ 6bgHXEZ8WK/3KNo5mVKDpQLD2r8/9UYw1GE6grw07hpOb8pq1cqFIjC0OAAXnWTStyeC HxZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612869; x=1733217669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5vCamtieJ1Any0nEDdOYudZWF6ph91xcO8/i+h+/3r0=; b=V6shCiLEst0j5ma5mjgvVmvPKprenNeQ2KAHAgxtxm+ozSzncbMHTF097Npkc8zHBD E2oMBCpsJ6yJF8UhJgCeBOysa7zogIIj0PQZzE4ImcGle5ieltaJ0OyJe3+oAO/ABmRI ElsEONvT94g+5pTNJvPUbE66IggwxZjhNwrJE21EJiRVoeS94OMWKlbmGY59q/CHvark XakEOg8MgfV02bZ/qYH/czyx60jO50EW0Dh/YWplnMgBjzXNOIHJgk1W4VYE4c8Rvjk4 VTG4ib3JFaB8S10+eymEUuvdfNnjEy2qXwK2fchUE8xWZubJEb0qLV5J8IijPzZTQYdH HgUQ== X-Forwarded-Encrypted: i=1; AJvYcCUHL3VYYH1jhP98xuXjw3FJHlF6cA2EtdYrg8xUbROKxK6+63ZQ877xliuZ+KrK5CdQmKCcazTI8tdIymIB1yJwQw==@vger.kernel.org X-Gm-Message-State: AOJu0YxCqz1egxUiGkaosQ44qx7EKrj+ngV7nwk9JfT6rKReRrSQgr/+ 8hImQmC0hOBea++JduW97oJ6mf5d+57LJddjfGDlihInBQh/MJFJ1sgaI37r5ms= X-Gm-Gg: ASbGncvooApazvFFNtJVprvNsN9WAWPjPO+Hq6vRr0D76ZrTKxbMIZF/JLcA0/+4NRw N/a2Twa7afsQHh1rqNf7aSqzOkWXXonukWhL6XbsYy7QVytRacM6pyaflTiqzzDD9d/PVWzqa5M +f0rNuF6lrjeNpQ89yo3NOD0wpJ30mtVRqp7Fo3MXJNaJM957pEaU15UG1iFo6/PSY0FUzsbAfv VAIJ4xVcopsaGVwMNYxqkHVW7nRt2Yc0ySxiBbN/myE3qGSNPhjObYxizzlwjzy616yv6buNRDs dZ0= X-Google-Smtp-Source: AGHT+IHaYOnIDbCpLmYeLO1a6tWYrQIEozAksJelkAeI7VXpQtyjiqqF3I9/uKkLk0h0PGHL3GFAQQ== X-Received: by 2002:a05:6000:2ad:b0:382:4a4e:25bb with SMTP id ffacd0b85a97d-38260bcc4fdmr15091977f8f.46.1732612868973; Tue, 26 Nov 2024 01:21:08 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:08 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 02/15] soc: renesas: Add SYSC driver for Renesas RZ family Date: Tue, 26 Nov 2024 11:20:37 +0200 Message-Id: <20241126092050.1825607-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ/G3S system controller (SYSC) has various registers that control signals specific to individual IPs. IP drivers must control these signals at different configuration phases. Add SYSC driver that allows individual SYSC consumers to control these signals. The SYSC driver exports a syscon regmap enabling IP drivers to use a specific SYSC offset and mask from the device tree, which can then be accessed through regmap_update_bits(). Currently, the SYSC driver provides control to the USB PWRRDY signal, which is routed to the USB PHY. This signal needs to be managed before or after powering the USB PHY off or on. Other SYSC signals candidates (as exposed in the the hardware manual of the RZ/G3S SoC) include: * PCIe: - ALLOW_ENTER_L1 signal controlled through the SYS_PCIE_CFG register - PCIE_RST_RSM_B signal controlled through the SYS_PCIE_RST_RSM_B register - MODE_RXTERMINATION signal controlled through SYS_PCIE_PHY register * SPI: - SEL_SPI_OCTA signal controlled through SYS_IPCONT_SEL_SPI_OCTA register * I2C/I3C: - af_bypass I2C signals controlled through SYS_I2Cx_CFG registers (x=0..3) - af_bypass I3C signal controlled through SYS_I3C_CFG register * Ethernet: - FEC_GIGA_ENABLE Ethernet signals controlled through SYS_GETHx_CFG registers (x=0..1) As different Renesas RZ SoC shares most of the SYSC functionalities available on the RZ/G3S SoC, the driver if formed of a SYSC core part and a SoC specific part allowing individual SYSC SoC to provide functionalities to the SYSC core. Signed-off-by: Claudiu Beznea Reviewed-by: Biju Das --- Change in v2: - this was patch 04/16 in v1 - dropped the initial approach proposed in v1 where a with a reset controller driver was proposed to handle the USB PWRRDY signal - implemented it with syscon regmap and the SYSC signal concept (introduced in this patch) drivers/soc/renesas/Kconfig | 7 + drivers/soc/renesas/Makefile | 2 + drivers/soc/renesas/r9a08g045-sysc.c | 31 +++ drivers/soc/renesas/rz-sysc.c | 286 +++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.h | 52 +++++ 5 files changed, 378 insertions(+) create mode 100644 drivers/soc/renesas/r9a08g045-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.c create mode 100644 drivers/soc/renesas/rz-sysc.h diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 9f7fe02310b9..0686c3ad9e27 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -378,4 +378,11 @@ config PWC_RZV2M config RST_RCAR bool "Reset Controller support for R-Car" if COMPILE_TEST +config SYSC_RZ + bool "System controller for RZ SoCs" if COMPILE_TEST + +config SYSC_R9A08G045 + bool "Renesas RZ/G3S System controller support" if COMPILE_TEST + select SYSC_RZ + endif # SOC_RENESAS diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 734f8f8cefa4..8cd139b3dd0a 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -6,7 +6,9 @@ obj-$(CONFIG_SOC_RENESAS) += renesas-soc.o ifdef CONFIG_SMP obj-$(CONFIG_ARCH_R9A06G032) += r9a06g032-smp.o endif +obj-$(CONFIG_SYSC_R9A08G045) += r9a08g045-sysc.o # Family obj-$(CONFIG_PWC_RZV2M) += pwc-rzv2m.o obj-$(CONFIG_RST_RCAR) += rcar-rst.o +obj-$(CONFIG_SYSC_RZ) += rz-sysc.o diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c new file mode 100644 index 000000000000..ceea738aee72 --- /dev/null +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3S System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include + +#include "rz-sysc.h" + +#define SYS_USB_PWRRDY 0xd70 +#define SYS_USB_PWRRDY_PWRRDY_N BIT(0) +#define SYS_MAX_REG 0xe20 + +static const struct rz_sysc_signal_init_data rzg3s_sysc_signals_init_data[] __initconst = { + { + .name = "usb-pwrrdy", + .offset = SYS_USB_PWRRDY, + .mask = SYS_USB_PWRRDY_PWRRDY_N, + .refcnt_incr_val = 0 + } +}; + +const struct rz_sysc_init_data rzg3s_sysc_init_data = { + .signals_init_data = rzg3s_sysc_signals_init_data, + .num_signals = ARRAY_SIZE(rzg3s_sysc_signals_init_data), + .max_register_offset = SYS_MAX_REG, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c new file mode 100644 index 000000000000..dc0edacd7170 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ System controller driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rz-sysc.h" + +/** + * struct rz_sysc - RZ SYSC private data structure + * @base: SYSC base address + * @dev: SYSC device pointer + * @signals: SYSC signals + * @num_signals: number of SYSC signals + */ +struct rz_sysc { + void __iomem *base; + struct device *dev; + struct rz_sysc_signal *signals; + u8 num_signals; +}; + +static int rz_sysc_reg_read(void *context, unsigned int off, unsigned int *val) +{ + struct rz_sysc *sysc = context; + + *val = readl(sysc->base + off); + + return 0; +} + +static struct rz_sysc_signal *rz_sysc_off_to_signal(struct rz_sysc *sysc, unsigned int offset, + unsigned int mask) +{ + struct rz_sysc_signal *signals = sysc->signals; + + for (u32 i = 0; i < sysc->num_signals; i++) { + if (signals[i].init_data->offset != offset) + continue; + + /* + * In case mask == 0 we just return the signal data w/o checking the mask. + * This is useful when calling through rz_sysc_reg_write() to check + * if the requested setting is for a mapped signal or not. + */ + if (mask) { + if (signals[i].init_data->mask == mask) + return &signals[i]; + } else { + return &signals[i]; + } + } + + return NULL; +} + +static int rz_sysc_reg_update_bits(void *context, unsigned int off, + unsigned int mask, unsigned int val) +{ + struct rz_sysc *sysc = context; + struct rz_sysc_signal *signal; + bool update = false; + + signal = rz_sysc_off_to_signal(sysc, off, mask); + if (signal) { + if (signal->init_data->refcnt_incr_val == val) { + if (!refcount_read(&signal->refcnt)) { + refcount_set(&signal->refcnt, 1); + update = true; + } else { + refcount_inc(&signal->refcnt); + } + } else { + update = refcount_dec_and_test(&signal->refcnt); + } + } else { + update = true; + } + + if (update) { + u32 tmp; + + tmp = readl(sysc->base + off); + tmp &= ~mask; + tmp |= val & mask; + writel(tmp, sysc->base + off); + } + + return 0; +} + +static int rz_sysc_reg_write(void *context, unsigned int off, unsigned int val) +{ + struct rz_sysc *sysc = context; + struct rz_sysc_signal *signal; + + /* + * Force using regmap_update_bits() for signals to have reference counter + * per individual signal in case there are multiple signals controlled + * through the same register. + */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) { + dev_err(sysc->dev, + "regmap_write() not allowed on register controlling a signal. Use regmap_update_bits()!"); + return -EOPNOTSUPP; + } + + writel(val, sysc->base + off); + + return 0; +} + +static bool rz_sysc_writeable_reg(struct device *dev, unsigned int off) +{ + struct rz_sysc *sysc = dev_get_drvdata(dev); + struct rz_sysc_signal *signal; + + /* Any register containing a signal is writeable. */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) + return true; + + return false; +} + +static bool rz_sysc_readable_reg(struct device *dev, unsigned int off) +{ + struct rz_sysc *sysc = dev_get_drvdata(dev); + struct rz_sysc_signal *signal; + + /* Any register containing a signal is readable. */ + signal = rz_sysc_off_to_signal(sysc, off, 0); + if (signal) + return true; + + return false; +} + +static int rz_sysc_signals_show(struct seq_file *s, void *what) +{ + struct rz_sysc *sysc = s->private; + + seq_printf(s, "%-20s Enable count\n", "Signal"); + seq_printf(s, "%-20s ------------\n", "--------------------"); + + for (u8 i = 0; i < sysc->num_signals; i++) { + seq_printf(s, "%-20s %d\n", sysc->signals[i].init_data->name, + refcount_read(&sysc->signals[i].refcnt)); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(rz_sysc_signals); + +static void rz_sysc_debugfs_remove(void *data) +{ + debugfs_remove_recursive(data); +} + +static int rz_sysc_signals_init(struct rz_sysc *sysc, + const struct rz_sysc_signal_init_data *init_data, + u32 num_signals) +{ + struct dentry *root; + int ret; + + sysc->signals = devm_kcalloc(sysc->dev, num_signals, sizeof(*sysc->signals), + GFP_KERNEL); + if (!sysc->signals) + return -ENOMEM; + + for (u32 i = 0; i < num_signals; i++) { + struct rz_sysc_signal_init_data *id; + + id = devm_kzalloc(sysc->dev, sizeof(*id), GFP_KERNEL); + if (!id) + return -ENOMEM; + + id->name = devm_kstrdup(sysc->dev, init_data->name, GFP_KERNEL); + if (!id->name) + return -ENOMEM; + + id->offset = init_data->offset; + id->mask = init_data->mask; + id->refcnt_incr_val = init_data->refcnt_incr_val; + + sysc->signals[i].init_data = id; + refcount_set(&sysc->signals[i].refcnt, 0); + } + + sysc->num_signals = num_signals; + + root = debugfs_create_dir("renesas-rz-sysc", NULL); + ret = devm_add_action_or_reset(sysc->dev, rz_sysc_debugfs_remove, root); + if (ret) + return ret; + debugfs_create_file("signals", 0444, root, sysc, &rz_sysc_signals_fops); + + return 0; +} + +static struct regmap_config rz_sysc_regmap = { + .name = "rz_sysc_regs", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, + .reg_read = rz_sysc_reg_read, + .reg_write = rz_sysc_reg_write, + .reg_update_bits = rz_sysc_reg_update_bits, + .writeable_reg = rz_sysc_writeable_reg, + .readable_reg = rz_sysc_readable_reg, +}; + +static const struct of_device_id rz_sysc_match[] = { +#ifdef CONFIG_SYSC_R9A08G045 + { .compatible = "renesas,r9a08g045-sysc", .data = &rzg3s_sysc_init_data }, +#endif + { } +}; +MODULE_DEVICE_TABLE(of, rz_sysc_match); + +static int rz_sysc_probe(struct platform_device *pdev) +{ + const struct rz_sysc_init_data *data; + struct device *dev = &pdev->dev; + struct rz_sysc *sysc; + struct regmap *regmap; + int ret; + + data = device_get_match_data(dev); + if (!data || !data->max_register_offset) + return -EINVAL; + + sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); + if (!sysc) + return -ENOMEM; + + sysc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sysc->base)) + return PTR_ERR(sysc->base); + + sysc->dev = dev; + + ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals); + if (ret) + return ret; + + dev_set_drvdata(dev, sysc); + rz_sysc_regmap.max_register = data->max_register_offset; + regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); +} + +static struct platform_driver rz_sysc_driver = { + .driver = { + .name = "renesas-rz-sysc", + .of_match_table = rz_sysc_match + }, + .probe = rz_sysc_probe +}; + +static int __init rz_sysc_init(void) +{ + return platform_driver_register(&rz_sysc_driver); +} +subsys_initcall(rz_sysc_init); + +MODULE_DESCRIPTION("Renesas RZ System Controller Driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h new file mode 100644 index 000000000000..bb850310c931 --- /dev/null +++ b/drivers/soc/renesas/rz-sysc.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ System Controller + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __SOC_RENESAS_RZ_SYSC_H__ +#define __SOC_RENESAS_RZ_SYSC_H__ + +#include +#include + +/** + * struct rz_sysc_signal_init_data - RZ SYSC signals init data + * @name: signal name + * @offset: register offset controling this signal + * @mask: bitmask in register specific to this signal + * @refcnt_incr_val: increment refcnt when setting this value + */ +struct rz_sysc_signal_init_data { + const char *name; + u32 offset; + u32 mask; + u32 refcnt_incr_val; +}; + +/** + * struct rz_sysc_signal - RZ SYSC signals + * @init_data: signals initialization data + * @refcnt: reference counter + */ +struct rz_sysc_signal { + const struct rz_sysc_signal_init_data *init_data; + refcount_t refcnt; +}; + +/** + * struct rz_sysc_init_data - RZ SYSC initialization data + * @signals_init_data: RZ SYSC signals initialization data + * @num_signals: number of SYSC signals + * @max_register_offset: Maximum SYSC register offset to be used by the regmap config + */ +struct rz_sysc_init_data { + const struct rz_sysc_signal_init_data *signals_init_data; + u32 num_signals; + u32 max_register_offset; +}; + +extern const struct rz_sysc_init_data rzg3s_sysc_init_data; + +#endif /* __SOC_RENESAS_RZ_SYSC_H__ */ From patchwork Tue Nov 26 09:20:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885622 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62AEA1BCA11 for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:10 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 03/15] soc: renesas: rz-sysc: Enable SYSC driver for RZ/G3S Date: Tue, 26 Nov 2024 11:20:38 +0200 Message-Id: <20241126092050.1825607-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable SYSC driver for RZ/G3S. This is necessary for USB support. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new drivers/soc/renesas/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 0686c3ad9e27..c8065f25ee53 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -334,6 +334,7 @@ config ARCH_R9A07G054 config ARCH_R9A08G045 bool "ARM64 Platform support for RZ/G3S" select ARCH_RZG2L + select SYSC_R9A08G045 help This enables support for the Renesas RZ/G3S SoC variants. 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:11 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 04/15] soc: renesas: rz-sysc: Add SoC detection support Date: Tue, 26 Nov 2024 11:20:39 +0200 Message-Id: <20241126092050.1825607-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The RZ SYSC controller has registers that keep the SoC ID data. Add driver support to retrieve the SoC ID and register a SoC driver. Signed-off-by: Claudiu Beznea Reviewed-by: Biju Das --- Changes in v2: - this was patch 05/16 in v1 - changed patch title and description - added SoC initialization code in its own function - addressed the review comments - introduced struct rz_sysc_soc_id_init_data and adjusted the code accordingly - dropped the RZ/G3S SoC detection code (it will be introduced in a separate patch) drivers/soc/renesas/rz-sysc.c | 72 +++++++++++++++++++++++++++++++++-- drivers/soc/renesas/rz-sysc.h | 18 +++++++++ 2 files changed, 86 insertions(+), 4 deletions(-) diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index dc0edacd7170..d34d295831b8 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -14,9 +14,12 @@ #include #include #include +#include #include "rz-sysc.h" +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) + /** * struct rz_sysc - RZ SYSC private data structure * @base: SYSC base address @@ -211,6 +214,59 @@ static int rz_sysc_signals_init(struct rz_sysc *sysc, return 0; } +static int rz_sysc_soc_init(struct rz_sysc *sysc, const struct of_device_id *match) +{ + const struct rz_sysc_init_data *sysc_data = match->data; + const struct rz_sysc_soc_id_init_data *soc_data = sysc_data->soc_id_init_data; + struct soc_device_attribute *soc_dev_attr; + const char *soc_id_start, *soc_id_end; + u32 val, revision, specific_id; + struct soc_device *soc_dev; + char soc_id[32] = {0}; + u8 size; + + if (!soc_data || !soc_data->family || !soc_data->offset || + !soc_data->revision_mask) + return -EINVAL; + + soc_id_start = strchr(match->compatible, ',') + 1; + soc_id_end = strchr(match->compatible, '-'); + size = soc_id_end - soc_id_start; + if (size > 32) + size = 32; + strscpy(soc_id, soc_id_start, size); + + soc_dev_attr = devm_kzalloc(sysc->dev, sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = soc_data->family; + soc_dev_attr->soc_id = devm_kstrdup(sysc->dev, soc_id, GFP_KERNEL); + if (!soc_dev_attr->soc_id) + return -ENOMEM; + + val = readl(sysc->base + soc_data->offset); + revision = field_get(soc_data->revision_mask, val); + specific_id = field_get(soc_data->specific_id_mask, val); + soc_dev_attr->revision = devm_kasprintf(sysc->dev, GFP_KERNEL, "%u", revision); + if (!soc_dev_attr->revision) + return -ENOMEM; + + if (soc_data->id && specific_id != soc_data->id) { + dev_warn(sysc->dev, "SoC mismatch (product = 0x%x)\n", specific_id); + return -ENODEV; + } + + dev_info(sysc->dev, "Detected Renesas %s %s Rev %s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, soc_dev_attr->revision); + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) + return PTR_ERR(soc_dev); + + return 0; +} + static struct regmap_config rz_sysc_regmap = { .name = "rz_sysc_regs", .reg_bits = 32, @@ -235,14 +291,15 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); static int rz_sysc_probe(struct platform_device *pdev) { const struct rz_sysc_init_data *data; + const struct of_device_id *match; struct device *dev = &pdev->dev; - struct rz_sysc *sysc; struct regmap *regmap; + struct rz_sysc *sysc; int ret; - data = device_get_match_data(dev); - if (!data || !data->max_register_offset) - return -EINVAL; + match = of_match_node(rz_sysc_match, dev->of_node); + if (!match || !match->data) + return -ENODEV; sysc = devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) @@ -253,6 +310,13 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); sysc->dev = dev; + ret = rz_sysc_soc_init(sysc, match); + if (ret) + return ret; + + data = match->data; + if (!data->max_register_offset) + return -EINVAL; ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals); if (ret) diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index bb850310c931..babca9c743c7 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -35,13 +35,31 @@ struct rz_sysc_signal { refcount_t refcnt; }; +/** + * struct rz_syc_soc_id_init_data - RZ SYSC SoC identification initialization data + * @family: RZ SoC family + * @id: RZ SoC expected ID + * @offset: SYSC SoC ID register offset + * @revision_mask: SYSC SoC ID revision mask + * @specific_id_mask: SYSC SoC ID specific ID mask + */ +struct rz_sysc_soc_id_init_data { + const char * const family; + u32 id; + u32 offset; + u32 revision_mask; + u32 specific_id_mask; +}; + /** * struct rz_sysc_init_data - RZ SYSC initialization data + * @soc_id_init_data: RZ SYSC SoC ID initialization data * @signals_init_data: RZ SYSC signals initialization data * @num_signals: number of SYSC signals * @max_register_offset: Maximum SYSC register offset to be used by the regmap config */ struct rz_sysc_init_data { + const struct rz_sysc_soc_id_init_data *soc_id_init_data; const struct rz_sysc_signal_init_data *signals_init_data; u32 num_signals; u32 max_register_offset; From patchwork Tue Nov 26 09:20:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885624 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88D021CBE94 for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:13 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 05/15] soc: renesas: rz-sysc: Move RZ/G3S SoC detection to the SYSC driver Date: Tue, 26 Nov 2024 11:20:40 +0200 Message-Id: <20241126092050.1825607-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Now that we have SoC detection in the RZ SYSC driver, move the RZ/G3S SoC detection to it. The SYSC provides SoC ID in its own registers. Signed-off-by: Claudiu Beznea --- Changes in v2: - this was handled though patch 05/16 in v1 - provide SoC specific init data through the SoC specific driver drivers/soc/renesas/r9a08g045-sysc.c | 12 ++++++++++++ drivers/soc/renesas/renesas-soc.c | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a08g045-sysc.c index ceea738aee72..81970db300b2 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -11,6 +11,9 @@ #include "rz-sysc.h" +#define SYS_LSI_DEVID 0xa04 +#define SYS_LSI_DEVID_REV GENMASK(31, 28) +#define SYS_LSI_DEVID_SPECIFIC GENMASK(27, 0) #define SYS_USB_PWRRDY 0xd70 #define SYS_USB_PWRRDY_PWRRDY_N BIT(0) #define SYS_MAX_REG 0xe20 @@ -24,7 +27,16 @@ static const struct rz_sysc_signal_init_data rzg3s_sysc_signals_init_data[] __in } }; +static const struct rz_sysc_soc_id_init_data rzg3s_sysc_soc_id_init_data __initconst = { + .family = "RZ/G3S", + .id = 0x85e0447, + .offset = SYS_LSI_DEVID, + .revision_mask = SYS_LSI_DEVID_REV, + .specific_id_mask = SYS_LSI_DEVID_SPECIFIC +}; + const struct rz_sysc_init_data rzg3s_sysc_init_data = { + .soc_id_init_data = &rzg3s_sysc_soc_id_init_data, .signals_init_data = rzg3s_sysc_signals_init_data, .num_signals = ARRAY_SIZE(rzg3s_sysc_signals_init_data), .max_register_offset = SYS_MAX_REG, diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 172d59e6fbcf..425d9037dcd0 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -71,10 +71,6 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = { .name = "RZ/G2UL", }; -static const struct renesas_family fam_rzg3s __initconst __maybe_unused = { - .name = "RZ/G3S", -}; - static const struct renesas_family fam_rzv2h __initconst __maybe_unused = { .name = "RZ/V2H", }; @@ -176,11 +172,6 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = { .id = 0x8450447, }; -static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = { - .family = &fam_rzg3s, - .id = 0x85e0447, -}; - static const struct renesas_soc soc_rz_v2h __initconst __maybe_unused = { .family = &fam_rzv2h, .id = 0x847a447, @@ -410,9 +401,6 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#ifdef CONFIG_ARCH_R9A08G045 - { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s }, -#endif #ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif From patchwork Tue Nov 26 09:20:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885625 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3849319258B for ; Tue, 26 Nov 2024 09:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:15 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea , Conor Dooley Subject: [PATCH v2 06/15] dt-bindings: usb: renesas,usbhs: Document RZ/G3S SoC Date: Tue, 26 Nov 2024 11:20:41 +0200 Message-Id: <20241126092050.1825607-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The USBHS IP block on RZ/G3S SoC is identitcal to the one found on the RZ/G2L device. Document the RZ/G3S USBHS IP block. Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 09/16 in v1 - collected tags Documentation/devicetree/bindings/usb/renesas,usbhs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index b23ef29bf794..980f325341d4 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -26,6 +26,7 @@ properties: - renesas,usbhs-r9a07g043 # RZ/G2UL and RZ/Five - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} - renesas,usbhs-r9a07g054 # RZ/V2L + - renesas,usbhs-r9a08g045 # RZ/G3S - const: renesas,rzg2l-usbhs - items: @@ -130,6 +131,7 @@ allOf: - renesas,usbhs-r9a07g043 - renesas,usbhs-r9a07g044 - renesas,usbhs-r9a07g054 + - renesas,usbhs-r9a08g045 then: properties: interrupts: From patchwork Tue Nov 26 09:20:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885626 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B29C91D0E26 for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:16 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 07/15] dt-bindings: phy: renesas,usb2-phy: Mark resets as required for RZ/G3S Date: Tue, 26 Nov 2024 11:20:42 +0200 Message-Id: <20241126092050.1825607-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The reset lines are mandatory for the Renesas RZ/G3S platform and must be explicitly defined in device tree. Fixes: f3c849855114 ("dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings") Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index af275cea3456..2babd200bd98 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -105,7 +105,9 @@ allOf: properties: compatible: contains: - const: renesas,rzg2l-usb2-phy + enum: + - renesas,rzg2l-usb2-phy + - renesas,usb2-phy-r9a08g045 then: required: - resets From patchwork Tue Nov 26 09:20:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885627 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B93E1D27BB for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:18 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 08/15] dt-bindings: phy: renesas,usb2-phy: Add renesas,sysc-signal Date: Tue, 26 Nov 2024 11:20:43 +0200 Message-Id: <20241126092050.1825607-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY receives a signal from the system controller that need to be de-asserted/asserted when power is turned on/off. This signal, called PWRRDY, is controlled through a specific register in the system controller memory space. Add the renesas,sysc-signal DT property to describe the relation b/w the system controller and the USB PHY on the Renesas RZ/G3S. This property provides a phandle to the system controller, along with the offset within the system controller memory space that manages the signal and a bitmask that indicates the specific bits required to control the signal. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new .../bindings/phy/renesas,usb2-phy.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 2babd200bd98..3b8dcacc3740 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -85,6 +85,16 @@ properties: dr_mode: true + renesas,sysc-signal: + description: System controller phandle, specifying the register + offset and bitmask associated with a specific system controller signal + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: system controller phandle + - description: register offset associated with a signal + - description: register bitmask associated with a signal + if: properties: compatible: @@ -112,6 +122,18 @@ allOf: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,usb2-phy-r9a08g045 + then: + required: + - renesas,sysc-signal + else: + properties: + renesas,sysc-signal: false + additionalProperties: false examples: From patchwork Tue Nov 26 09:20:44 2024 Content-Type: text/plain; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:20 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Biju Das , Claudiu Beznea Subject: [PATCH v2 09/15] phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe() Date: Tue, 26 Nov 2024 11:20:44 +0200 Message-Id: <20241126092050.1825607-10-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Christophe JAILLET If an error occurs after the reset_control_deassert(), reset_control_assert() must be called, as already done in the remove function. Use devm_add_action_or_reset() to add the missing call and simplify the .remove() function accordingly. Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initialize the bus") Signed-off-by: Christophe JAILLET Reviewed-by: Biju Das [claudiu.beznea: removed "struct reset_control *rstc = data;" from rcar_gen3_reset_assert()] Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new; re-spinned the Christophe's work at https://lore.kernel.org/all/TYCPR01MB113329930BA5E2149C9BE2A1986672@TYCPR01MB11332.jpnprd01.prod.outlook.com/ drivers/phy/renesas/phy-rcar-gen3-usb2.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 775f4f973a6c..59f74aa993ac 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -668,6 +668,11 @@ static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np) return candidate; } +static void rcar_gen3_reset_assert(void *data) +{ + reset_control_assert(data); +} + static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) { struct device *dev = channel->dev; @@ -686,6 +691,11 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) if (ret) goto rpm_put; + ret = devm_add_action_or_reset(dev, rcar_gen3_reset_assert, + channel->rstc); + if (ret) + goto rpm_put; + val = readl(channel->base + USB2_AHB_BUS_CTR); val &= ~USB2_AHB_BUS_CTR_MBL_MASK; val |= USB2_AHB_BUS_CTR_MBL_INCR4; @@ -815,7 +825,6 @@ static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev) if (channel->is_otg_channel) device_remove_file(&pdev->dev, &dev_attr_role); - reset_control_assert(channel->rstc); pm_runtime_disable(&pdev->dev); }; From patchwork Tue Nov 26 09:20:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885629 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 620D31D47CB for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:22 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 10/15] phy: renesas: rcar-gen3-usb2: Add support for PWRRDY Date: Tue, 26 Nov 2024 11:20:45 +0200 Message-Id: <20241126092050.1825607-11-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On the Renesas RZ/G3S SoC, the USB PHY has an input signal called PWRRDY. This signal is managed by the system controller and must be de-asserted after powering on the area where USB PHY resides and asserted before powering it off. The connection b/w the system controller and the USB PHY is implemented through the renesas,sysc-signal device tree property. This property specifies the register offset and the bitmask required to control the signal. The system controller exports the syscon regmap, and the read/write access to the memory area of the PWRRDY signal is reference-counted, as the same system controller signal is connected to both RZ/G3S USB PHYs. Add support for the PWRRDY signal control. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new drivers/phy/renesas/phy-rcar-gen3-usb2.c | 66 ++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c index 59f74aa993ac..84459755adf5 100644 --- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c +++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c @@ -12,12 +12,14 @@ #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -111,6 +113,12 @@ struct rcar_gen3_phy { bool powered; }; +struct rcar_gen3_pwrrdy { + struct regmap *regmap; + u32 offset; + u32 mask; +}; + struct rcar_gen3_chan { void __iomem *base; struct device *dev; /* platform_device's device */ @@ -118,6 +126,7 @@ struct rcar_gen3_chan { struct rcar_gen3_phy rphys[NUM_OF_PHYS]; struct regulator *vbus; struct reset_control *rstc; + struct rcar_gen3_pwrrdy *pwrrdy; struct work_struct work; struct mutex lock; /* protects rphys[...].powered */ enum usb_dr_mode dr_mode; @@ -133,6 +142,7 @@ struct rcar_gen3_phy_drv_data { const struct phy_ops *phy_usb2_ops; bool no_adp_ctrl; bool init_bus; + bool pwrrdy; }; /* @@ -587,6 +597,7 @@ static const struct rcar_gen3_phy_drv_data rz_g3s_phy_usb2_data = { .phy_usb2_ops = &rcar_gen3_phy_usb2_ops, .no_adp_ctrl = true, .init_bus = true, + .pwrrdy = true, }; static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = { @@ -707,6 +718,55 @@ static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel) return ret; } +static void rcar_gen3_phy_usb2_set_pwrrdy(struct rcar_gen3_chan *channel, bool power_on) +{ + struct rcar_gen3_pwrrdy *pwrrdy = channel->pwrrdy; + + /* N/A on this platform. */ + if (!pwrrdy) + return; + + regmap_update_bits(pwrrdy->regmap, pwrrdy->offset, pwrrdy->mask, !power_on); +} + +static void rcar_gen3_phy_usb2_pwrrdy_off(void *data) +{ + rcar_gen3_phy_usb2_set_pwrrdy(data, false); +} + +static int rcar_gen3_phy_usb2_init_pwrrdy(struct rcar_gen3_chan *channel) +{ + struct device *dev = channel->dev; + struct rcar_gen3_pwrrdy *pwrrdy; + struct of_phandle_args args; + int ret; + + pwrrdy = devm_kzalloc(dev, sizeof(*pwrrdy), GFP_KERNEL); + if (!pwrrdy) + return -ENOMEM; + + ret = of_parse_phandle_with_args(dev->of_node, "renesas,sysc-signal", + "#renesas,sysc-signal-cells", 0, &args); + if (ret) + return ret; + + pwrrdy->regmap = syscon_node_to_regmap(args.np); + pwrrdy->offset = args.args[0]; + pwrrdy->mask = args.args[1]; + + of_node_put(args.np); + + if (IS_ERR(pwrrdy->regmap)) + return PTR_ERR(pwrrdy->regmap); + + channel->pwrrdy = pwrrdy; + + /* Power it ON. */ + rcar_gen3_phy_usb2_set_pwrrdy(channel, true); + + return devm_add_action_or_reset(dev, rcar_gen3_phy_usb2_pwrrdy_off, channel); +} + static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) { const struct rcar_gen3_phy_drv_data *phy_data; @@ -763,6 +823,12 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev) platform_set_drvdata(pdev, channel); channel->dev = dev; + if (phy_data->pwrrdy) { + ret = rcar_gen3_phy_usb2_init_pwrrdy(channel); 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:24 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 11/15] dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support Date: Tue, 26 Nov 2024 11:20:46 +0200 Message-Id: <20241126092050.1825607-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The Renesas RZ/G3S USB PHY control block is similar with the one found on the Renesas RZ/G2L. Add documentation for it. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new .../devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml index b0b20af15313..ae59c2dcadbf 100644 --- a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml @@ -20,6 +20,7 @@ properties: - renesas,r9a07g043-usbphy-ctrl # RZ/G2UL and RZ/Five - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} - renesas,r9a07g054-usbphy-ctrl # RZ/V2L + - renesas,r9a08g045-usbphy-ctrl # RZ/G3S - const: renesas,rzg2l-usbphy-ctrl reg: From patchwork Tue Nov 26 09:20:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885631 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AEB11D54D1 for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:25 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 12/15] arm64: dts: renesas: Add #renesas,sysc-signal-cells to system controller node Date: Tue, 26 Nov 2024 11:20:47 +0200 Message-Id: <20241126092050.1825607-13-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea The system controller on RZ/G3S can provide control access to its signals. To enable this, add the #renesas,sysc-signal-cells DT property. Consumers can use the renesas,sysc-signal DT property to reference the specific SYSC signal that needs to be controlled. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 3 ++- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 593c66b27ad1..2ebb951e6a39 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -585,8 +585,9 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g043-sysc"; + compatible = "renesas,r9a07g043-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6b1c77cd8261..9dd229cbf288 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -877,7 +877,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g044-sysc"; + compatible = "renesas,r9a07g044-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -885,6 +885,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 01f59914dd09..31550b8c3143 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -884,7 +884,7 @@ cpg: clock-controller@11010000 { }; sysc: system-controller@11020000 { - compatible = "renesas,r9a07g054-sysc"; + compatible = "renesas,r9a07g054-sysc", "syscon"; reg = <0 0x11020000 0 0x10000>; interrupts = , , @@ -892,6 +892,7 @@ sysc: system-controller@11020000 { ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; + #renesas,sysc-signal-cells = <2>; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:27 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 13/15] arm64: dts: renesas: r9a08g045: Enable the system controller Date: Tue, 26 Nov 2024 11:20:48 +0200 Message-Id: <20241126092050.1825607-14-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable the system controller. It is needed for USB and SoC identification. Signed-off-by: Claudiu Beznea --- Changes in v2: - none; this patch is new arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 169561386f35..89cf57eb8389 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -207,7 +207,6 @@ sysc: system-controller@11020000 { interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; #renesas,sysc-signal-cells = <2>; - status = "disabled"; }; pinctrl: pinctrl@11030000 { From patchwork Tue Nov 26 09:20:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885633 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1197F1D5CF2 for ; Tue, 26 Nov 2024 09:21:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612893; cv=none; b=r5Uu+VlopLk8pr/VpbbVbQh0i6/haoPmXYlb1NBpewOBWSCeV9cybgi6FKZmzKj7zNogfWESzeO0iNgtbt3AJJltyl95B3rcRrlaL/jMZdyjmkqTqGQDE4wAg/0PUl8GVfrJzjWPbBXYo4U/xtqFJx+q03SIoHrBkH8uqE9rm4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732612893; c=relaxed/simple; bh=2DMTJUAMbvgwMO6a642uq7ua8fsNBEbd1Oxy7nZyQa8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hQcta+ZPYlvOMWuTohqx6AVJYEhdTNypXNR5EYhaXNF4jJstrAJuQq4lOdLGOc2/DlyzPHRbjRFmaYiYDVAlOOn/FHCR1lZ8BaEfuKiOXjZMyTIg1Zob3CBBA3Y/D9ikhZVuFo0QYGdelDEbPgWimvSPpTf6je2T7mO7lspHhXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=GHKxhmxe; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="GHKxhmxe" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-434a10588f3so13280355e9.1 for ; Tue, 26 Nov 2024 01:21:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1732612889; x=1733217689; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qLdnHZoveqIvO5Hl0Ml7DeyDrz+2Vaoq4NvOVCNrZ/A=; b=GHKxhmxesIrI/tdCGHSbmOfQHu6ELwNJAb70ipA17qFwm1GMQH19ccoVbHToRt9Csd 8ZMaa8o9HGLQMySu7g+3G35vE56oMEIkRSZwp/gwiUQTNyOb6Zv0y+J85OrZfkT4K9KD On+9M8MDYDVrBBmofSaeo+X6YOUyTX4PIKCxqhKrNeQPoKffc+oATZ1anrOorshIcM00 d9icarOpmzQNPzRMOOC/h+Ae6rtjfLsOlzBvmmm6QiJ+8cZroT13MoZiWwIytjRS26kY TTZgblhCkoouhIJmS3cglEKtKdQbv38tWxcK9L/teWhzlrUDatIygv/HU1BWOQpP/TnV ZPTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732612889; x=1733217689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qLdnHZoveqIvO5Hl0Ml7DeyDrz+2Vaoq4NvOVCNrZ/A=; b=h7YTlnTys+4x6zFpPb92zD5YyZjR2U9+W/5km2YxVtWzI5H6YMq8x6MSpyKfAKYfTS QTbbEQCydtDDBbSsNUqH/HSZcKjRJJ65I8B17rCgcto/qij1AI3g/9SIFjw3IwDHQYcv 2ET10BMUyvyMROs1IbISOwsG/LfB/GwCLIgyWGucfSpPhui4izNl2v+rBVUy4HVAYiwE wArXV5ihNgC3/OIDSYJCTWlfhnKGyC8G5SGMisOcg+QhXll5Y+rpgZ+jaS7aGOFsp6aG beHNg5/qgcijf7TPkPrrdBh031xL4E/LR2OyQHAnCWXvtrY+Nv+wyAVp4DUEhmnpwJuN 2kEQ== X-Forwarded-Encrypted: i=1; AJvYcCXVxDz0vzQeSW0X/HUlxw/dMj1IeTJUvvbI35qt53dJBSp+MCP16fMuVdJkLFmLbfpKXdiiO4eV35exA62wC5oFKw==@vger.kernel.org X-Gm-Message-State: AOJu0YyUd55iVLOAriQlJx3ELMK4PERuf4e/Kx3mItt6N6oBf7+muFCx xxM08d6rOtOU0palS2TajcGIupHgAX4YAbZGJfoP2KrmnQiqvHv68Cu0iaLfnx0= X-Gm-Gg: ASbGncsbQAZiVsnKAU8jnu5+1HzZACpf3+BYtSVT5pQSWFLyYiTvgl/0CX/e27lJN9/ zqnBVy+ZZelS1PAXQBqBU3zecikhfM0X2j+YkTsg7Ak9FGzr6hiHc+B5ItaFcMDM8e0MSMKBxeP 0BQ/V1M71FPEmfSnD5dfGnpS9WgO7YorQYIGqwILXXiGSPBAVHiYtYFX4Tlb25HD5eQR4TjN0+4 gyR+pPowppuagkkLaBIh2d6B8U+g7KhJ07jXBrPxZUnoEv74sCSSFmZGXvtQJGvip/20fWj0g/P A3A= X-Google-Smtp-Source: AGHT+IFJiTv231Q0pA7mNGDg8+ehro7YZHPIBfZNFr1G9xSWhy4hE646eb2huz0yqoJ24h09vlKStA== X-Received: by 2002:a05:6000:1acc:b0:382:450c:2601 with SMTP id ffacd0b85a97d-38260b6b632mr11281224f8f.24.1732612889501; Tue, 26 Nov 2024 01:21:29 -0800 (PST) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:28 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 14/15] arm64: dts: renesas: r9a08g045: Add USB support Date: Tue, 26 Nov 2024 11:20:49 +0200 Message-Id: <20241126092050.1825607-15-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Add USB nodes for the Renesas RZ/G3S SoC. This consists of PHY reset, host and device support. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 14/16 in v1 - added renesas,sysc-signal properties to USB PHYs - collected tags - Geert: I kept your tag; please let me know if you consider otherwise arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 119 +++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 89cf57eb8389..6ce94bbecfa6 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -417,6 +417,125 @@ eth1: ethernet@11c40000 { status = "disabled"; }; + phyrst: usbphy-ctrl@11e00000 { + compatible = "renesas,r9a08g045-usbphy-ctrl", "renesas,rzg2l-usbphy-ctrl"; + reg = <0 0x11e00000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>; + resets = <&cpg R9A08G045_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; + }; + + ohci0: usb@11e10000 { + compatible = "generic-ohci"; + reg = <0 0x11e10000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11e10100 { + compatible = "generic-ehci"; + reg = <0 0x11e10100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11e10200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e10200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2H0_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + renesas,sysc-signal = <&sysc 0xd70 0x1>; + status = "disabled"; + }; + + hsusb: usb@11e20000 { + compatible = "renesas,usbhs-r9a08g045", + "renesas,rzg2l-usbhs"; + reg = <0 0x11e20000 0 0x10000>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A08G045_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11e30000 { + compatible = "generic-ohci"; + reg = <0 0x11e30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11e30100 { + compatible = "generic-ehci"; + reg = <0 0x11e30100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11e30200 { + compatible = "renesas,usb2-phy-r9a08g045"; + reg = <0 0x11e30200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A08G045_USB_PCLK>, + <&cpg CPG_MOD R9A08G045_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A08G045_USB_U2H1_HRESETN>; + #phy-cells = <1>; + power-domains = <&cpg>; + renesas,sysc-signal = <&sysc 0xd70 0x1>; + status = "disabled"; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From patchwork Tue Nov 26 09:20:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu X-Patchwork-Id: 13885634 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8D011D63C6 for ; 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([82.78.167.28]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3825fbc3a47sm13027694f8f.73.2024.11.26.01.21.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 01:21:30 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, geert+renesas@glider.be, magnus.damm@gmail.com, gregkh@linuxfoundation.org, yoshihiro.shimoda.uh@renesas.com, christophe.jaillet@wanadoo.fr Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-usb@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v2 15/15] arm64: dts: renesas: rzg3s-smarc: Enable USB support Date: Tue, 26 Nov 2024 11:20:50 +0200 Message-Id: <20241126092050.1825607-16-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> References: <20241126092050.1825607-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea Enable USB support (host, device, USB PHYs). Signed-off-by: Claudiu Beznea --- Changes in v2: - this was patch 15/16 in v1: - dropped sysc enablement as it is now done in SoC dtsi file arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 57 ++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 4509151344c4..84523e771ebf 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -64,12 +64,35 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; }; +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + &i2c0 { status = "okay"; clock-frequency = <1000000>; }; +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; @@ -128,6 +151,27 @@ cd { pinmux = ; /* SD1_CD */ }; }; + + usb0_pins: usb0 { + peri { + pinmux = , /* VBUS */ + ; /* OVC */ + }; + + otg { + pinmux = ; /* OTG_ID */ + bias-pull-up; + }; + }; + + usb1_pins: usb1 { + pinmux = , /* OVC */ + ; /* VBUS */ + }; +}; + +&phyrst { + status = "okay"; }; &scif0 { @@ -148,3 +192,16 @@ &sdhi1 { max-frequency = <125000000>; status = "okay"; }; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +};