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Tue, 26 Nov 2024 09:35:50 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 26 Nov 2024 01:35:44 -0800 From: Tingguo Cheng Date: Tue, 26 Nov 2024 17:35:05 +0800 Subject: [PATCH 1/2] arm64: dts: qcom: qcs8300: Adds SPMI support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241126-adds-spmi-pmic-peripherals-for-qcs8300-v1-1-28af84cb86f8@quicinc.com> References: <20241126-adds-spmi-pmic-peripherals-for-qcs8300-v1-0-28af84cb86f8@quicinc.com> In-Reply-To: <20241126-adds-spmi-pmic-peripherals-for-qcs8300-v1-0-28af84cb86f8@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Tingguo Cheng X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=ed25519-sha256; t=1732613740; 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Signed-off-by: Tingguo Cheng --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..03bf72d6ec5c9ec92f6f53df9253c8c5953e13c4 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -939,6 +939,28 @@ IPCC_MPROC_SIGNAL_GLINK_QMP #clock-cells = <0>; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + qcom,channel = <0>; + qcom,ee = <0>; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,qcs8300-tlmm"; reg = <0x0 0x0f100000 0x0 0x300000>; From patchwork Tue Nov 26 09:35:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tingguo Cheng X-Patchwork-Id: 13885718 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB2891C4A1E; Tue, 26 Nov 2024 09:35:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732613760; cv=none; b=quAaeqCnZrWALtVOqSe+dKj5rrjEIZM9RqJYyLiFfqsMZCqgwxUZu9oICPe+dy0MHBOzIwKLoqasDa6fraquYWv+IJWuaMPGqCFruY+5YwncHtGQjc/WrIp+fy2L2xY5sD2dHRuScKDTtQY7Bs+7zsZj5KTTfwoDMUu5EMJZ4pw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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The qcs8 300-ride uses 2 pmics(pmm8620au:0,pmm8650au:1) on the board, which are variants of pmm8654au used on sa8775p/qcs9100 -ride(4x pmics). Signed-off-by: Tingguo Cheng --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 7eed19a694c39dbe791afb6a991db65acb37e597..9447efb9cd01654b74ec4c18dec58b1956ffe710 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -9,6 +9,7 @@ #include #include "qcs8300.dtsi" +#include "sa8775p-pmics.dtsi" / { model = "Qualcomm Technologies, Inc. QCS8300 Ride"; compatible = "qcom,qcs8300-ride", "qcom,qcs8300"; @@ -223,6 +224,28 @@ &gcc { <0>; }; +&pmm8654au_0_pon_resin{ + linux,code = ; + + status = "okay"; +}; + +&pmm8654au_2{ + status = "disabled"; +}; + +&pmm8654au_2_thermal{ + status = "disabled"; +}; + +&pmm8654au_3{ + status = "disabled"; +}; + +&pmm8654au_3_thermal{ + status = "disabled"; +}; + &qupv3_id_0 { status = "okay"; };