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[124.171.72.210]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc21c28sm87321175ad.246.2024.11.26.09.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 09:12:56 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles Subject: [PULL 1/6] target/ppc: Fix non-maskable interrupt while halted Date: Wed, 27 Nov 2024 03:12:30 +1000 Message-ID: <20241126171235.362916-2-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126171235.362916-1-npiggin@gmail.com> References: <20241126171235.362916-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=npiggin@gmail.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The ppc (pnv and spapr) NMI injection code does not go through the asynchronous interrupt path and set a bit in env->pending_interrupts and raise an interrupt request that the cpu_exec() loop can see. Instead it injects the exception directly into registers. This can lead to cpu_exec() missing that the thread has work to do, if a NMI is injected while it was idle. Fix this by clearing halted when injecting the interrupt. Probably NMI injection should be reworked to use the interrupt request interface, but this seems to work as a minimal fix. Fixes: 3431648272d3 ("spapr: Add support for new NMI interface") Reviewed-by: Glenn Miles Signed-off-by: Nicholas Piggin --- target/ppc/excp_helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 70daa5076a..9f811af0a4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2495,10 +2495,16 @@ static void ppc_deliver_interrupt(CPUPPCState *env, int interrupt) } } +/* + * system reset is not delivered via normal irq method, so have to set + * halted = 0 to resume CPU running if it was halted. Possibly we should + * move it over to using PPC_INTERRUPT_RESET rather than async_run_on_cpu. + */ void ppc_cpu_do_system_reset(CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); + cs->halted = 0; powerpc_excp(cpu, POWERPC_EXCP_RESET); } @@ -2520,6 +2526,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) /* Anything for nested required here? MSR[HV] bit? */ + cs->halted = 0; powerpc_set_excp_state(cpu, vector, msr); } From patchwork Tue Nov 26 17:12:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13886234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32495D65530 for ; Tue, 26 Nov 2024 17:14:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tFz7e-00077j-Pm; Tue, 26 Nov 2024 12:13:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tFz7X-00075x-O8; Tue, 26 Nov 2024 12:13:04 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tFz7V-0004GW-Rd; Tue, 26 Nov 2024 12:13:03 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-21288d3b387so44431295ad.1; Tue, 26 Nov 2024 09:13:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1732641179; x=1733245979; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LZNPYSPlNBAIgFECBRph2WnB34JU07BYLZNqVQrL8CI=; b=J+51+qZ6YkFk5Wh8hLAQ3CuO5ad0ksA+ykLFriBV6fWpYxGc9Yfp1PlberSRJ2X/5j ToOlw4B71eiwUvYhgz7IwvmVsD5pGYXKAla4Kirj0T/FVIxHb+qOCC/1qnIPS7tKCYJu AZpWuo1NM9f2UW3/BbyzJTBI2XPOjrTUL/jqRinMfRVyvXcqtbDNeS4/EyLzL3K+sgIy tsnd64wodAz+u9HhbiVNsZral85dEyJlAnqCGH3BKK1K7f81LvK98ztAgvPQlsWpwVHU PlFtfarezwBCxRcHKSKX6+8TyHiy0lSYBOw2zzAhydz740YcNtgZ/pnOJ4Y1rnuyMzQZ 06UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732641179; x=1733245979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LZNPYSPlNBAIgFECBRph2WnB34JU07BYLZNqVQrL8CI=; b=QX/YtGlmURVHUzGWpNDSN3oRQ2dNuK8qZyVGIbS4PjM91/DQIbBN3GUljPm9gTlvQD GPD1WACxalHfy2hpteqWflKQyYr1JJNtO3Bb2HzOtbnKW9eF2Ej8sfXA6XNEJGjtOGQ1 nmQhwweQOwpY376k/B9Y1B2X9apdo1qnM/SwaZda7AdnoTI1VxcNeuFJ1RlOe3He4pou 2FGB7EF0GJz8s0cZoYGAUaNigI2//5R6riImDwPT37uyGE6XEXmBojHRMyZDdkQszr8K qbmvFVYp2HuGYqvnYRObXZlHpxtnrBvtGrHR6c6D5Rj+Q9uQ1RT4DQ1dir3j+HDI0W6L AV/w== X-Forwarded-Encrypted: i=1; AJvYcCVX+HNqyKZqeSd9v5x89rj6sKLQaH1B5MzPRdWCW5wNHA3rulOlhpQ2oTlaAXe5lUsLv0ac8jcBpQ==@nongnu.org X-Gm-Message-State: AOJu0YxiEr736MJh8v42v6VCrLXjE+5jiJGNPGyvMnhvNHcmmtdFmLFR xmeo8BrDpcTEPUYqQytPx8rXlSD/l7cjLqzPmZcn5ImjkAD4W8Fu/BiMIg== X-Gm-Gg: ASbGncs59/u+TCWAlwiMmJGonyvQnz/Au3/zIxprPmFXKqLAkckK6VnmwmBtWaLB8Qw qxLSnv7pOxKa6Sl99TN0ZSBzyu/C67LRo+0KHZpfDHDjN+tKz63WnegC8r+SAyPBw4Ibfc4Gctj ApX4SuVWmQwkr3ieaXmn7tKNJe1IfTZjtLKsGMVWLhFWT6fqtL8tjt/nXzyt4vxp6A/VXxuBGBp M7FdMgUnYc7yG9heUkiIeFELYQ7uZ8H0EW3h3B/D88V7yz8YEC//KW+OqcE3oQ7FOslC+gZ9HzV DbiwZg== X-Google-Smtp-Source: AGHT+IHoYQQnXm2PES9Hc054dxAUMVzvfXyo3fLyUP1OW4mFn40WyVw0IAn1BkJaRigBOji6G29mpA== X-Received: by 2002:a17:902:e5d2:b0:211:6b21:5a87 with SMTP id d9443c01a7336-2129f6b909dmr230132035ad.56.1732641179386; Tue, 26 Nov 2024 09:12:59 -0800 (PST) Received: from wheely.local0.net (124-171-72-210.tpgi.com.au. [124.171.72.210]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc21c28sm87321175ad.246.2024.11.26.09.12.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 09:12:59 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles Subject: [PULL 2/6] ppc/pnv: Fix direct controls quiesce Date: Wed, 27 Nov 2024 03:12:31 +1000 Message-ID: <20241126171235.362916-3-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126171235.362916-1-npiggin@gmail.com> References: <20241126171235.362916-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org powernv CPUs have a set of control registers that can stop, start, and do other things to control a thread's execution. Using this interface to stop a thread puts it into a particular state that can be queried, and is distinguishable from other things that might stop the CPU (e.g., going idle, or being debugged via gdb, or stopped by the monitor). Add a new flag that can speficially distinguish this state where it is stopped with control registers. This solves some hangs when rebooting powernv machines when skiboot is modified to allow QEMU to use the CPU control facility (that uses controls to bring all secondaries to a known state). Fixes: c8891955086 ("ppc/pnv: Implement POWER10 PC xscom registers for direct controls") Reviewed-by: Glenn Miles Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_core.c | 9 +++++++-- target/ppc/cpu.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index a30693990b..cbfac49862 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -217,8 +217,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, case PNV10_XSCOM_EC_CORE_RAS_STATUS: for (i = 0; i < nr_threads; i++) { PowerPCCPU *cpu = pc->threads[i]; - CPUState *cs = CPU(cpu); - if (cs->stopped) { + CPUPPCState *env = &cpu->env; + if (env->quiesced) { val |= PPC_BIT(0 + 8 * i) | PPC_BIT(1 + 8 * i); } } @@ -244,20 +244,25 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, for (i = 0; i < nr_threads; i++) { PowerPCCPU *cpu = pc->threads[i]; CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; if (val & PPC_BIT(7 + 8 * i)) { /* stop */ val &= ~PPC_BIT(7 + 8 * i); cpu_pause(cs); + env->quiesced = true; } if (val & PPC_BIT(6 + 8 * i)) { /* start */ val &= ~PPC_BIT(6 + 8 * i); + env->quiesced = false; cpu_resume(cs); } if (val & PPC_BIT(4 + 8 * i)) { /* sreset */ val &= ~PPC_BIT(4 + 8 * i); + env->quiesced = false; pnv_cpu_do_nmi_resume(cs); } if (val & PPC_BIT(3 + 8 * i)) { /* clear maint */ + env->quiesced = false; /* * Hardware has very particular cases for where clear maint * must be used and where start must be used to resume a diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 945af07a64..0b4f1013b8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1355,6 +1355,7 @@ struct CPUArchState { * special way (such as routing some resume causes to 0x100, i.e. sreset). */ bool resume_as_sreset; + bool quiesced; #endif /* These resources are used only in TCG */ From patchwork Tue Nov 26 17:12:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13886235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00F8AD65531 for ; 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[124.171.72.210]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc21c28sm87321175ad.246.2024.11.26.09.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 09:13:01 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles Subject: [PULL 3/6] target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket Date: Wed, 27 Nov 2024 03:12:32 +1000 Message-ID: <20241126171235.362916-4-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126171235.362916-1-npiggin@gmail.com> References: <20241126171235.362916-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=npiggin@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Glenn Miles The THREAD_SIBLING_FOREACH macro wasn't excluding threads from other chips. Add chip_index field to the thread state and add a check for the new field in the macro. Fixes: b769d4c8f4c6 ("target/ppc: Add initial flags and helpers for SMT support") Signed-off-by: Glenn Miles [npiggin: set chip_index for spapr too] Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_core.c | 2 ++ hw/ppc/spapr_cpu_core.c | 1 + target/ppc/cpu.h | 7 +++++-- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index cbfac49862..e6b02294b1 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -322,6 +322,8 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, pir_spr->default_value = pir; tir_spr->default_value = tir; + env->chip_index = pc->chip->chip_id; + if (pc->big_core) { /* 2 "small cores" get the same core index for SMT operations */ env->core_index = core_hwid >> 1; diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index ada439e831..135f86a622 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -313,6 +313,7 @@ static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp) return NULL; } + env->chip_index = sc->node_id; env->core_index = cc->core_id; cpu->node_id = sc->node_id; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0b4f1013b8..2ffac2ed03 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1253,6 +1253,7 @@ struct CPUArchState { /* For SMT processors */ bool has_smt_siblings; int core_index; + int chip_index; #if !defined(CONFIG_USER_ONLY) /* MMU context, only relevant for full system emulation */ @@ -1412,8 +1413,10 @@ struct CPUArchState { #define THREAD_SIBLING_FOREACH(cs, cs_sibling) \ CPU_FOREACH(cs_sibling) \ - if (POWERPC_CPU(cs)->env.core_index == \ - POWERPC_CPU(cs_sibling)->env.core_index) + if ((POWERPC_CPU(cs)->env.chip_index == \ + POWERPC_CPU(cs_sibling)->env.chip_index) && \ + (POWERPC_CPU(cs)->env.core_index == \ + POWERPC_CPU(cs_sibling)->env.core_index)) #define SET_FIT_PERIOD(a_, b_, c_, d_) \ do { \ From patchwork Tue Nov 26 17:12:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13886236 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65607D65530 for ; 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[124.171.72.210]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc21c28sm87321175ad.246.2024.11.26.09.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 09:13:04 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Glenn Miles , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 4/6] ppc/pnv: Add xscom- prefix to pervasive-control region name Date: Wed, 27 Nov 2024 03:12:33 +1000 Message-ID: <20241126171235.362916-5-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126171235.362916-1-npiggin@gmail.com> References: <20241126171235.362916-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org By convention, xscom regions get a xscom- prefix. Fixes: 1adf24708bf7 ("hw/ppc: Add pnv nest pervasive common chiplet model") Reviewed-by: Glenn Miles Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Nicholas Piggin --- hw/ppc/pnv_nest_pervasive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/pnv_nest_pervasive.c b/hw/ppc/pnv_nest_pervasive.c index 77476753a4..780fa69dde 100644 --- a/hw/ppc/pnv_nest_pervasive.c +++ b/hw/ppc/pnv_nest_pervasive.c @@ -177,7 +177,7 @@ static void pnv_nest_pervasive_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&nest_pervasive->xscom_ctrl_regs_mr, OBJECT(nest_pervasive), &pnv_nest_pervasive_control_xscom_ops, - nest_pervasive, "pervasive-control", + nest_pervasive, "xscom-pervasive-control", PNV10_XSCOM_CHIPLET_CTRL_REGS_SIZE); } From patchwork Tue Nov 26 17:12:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13886233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C83ED6552F for ; Tue, 26 Nov 2024 17:13:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tFz7u-0007CO-O0; Tue, 26 Nov 2024 12:13:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tFz7g-00078V-6U; Tue, 26 Nov 2024 12:13:13 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tFz7e-0004Hb-Cb; Tue, 26 Nov 2024 12:13:11 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-21288ce11d7so46378785ad.2; Tue, 26 Nov 2024 09:13:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1732641188; x=1733245988; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oW4RTaGV9Rp5u17+KtSXZQxBCwRUZA2L4Rf2kv6/KHg=; b=R1YXoF6iWrV0RAepwioawUSrIvYqY1TYgZe+XzhRps1swIXoMZZK/p4eNGn5IcQGal 5yWSawY0/0RB2EBtHKA/qJQgQApMJagFUovLhh6DRStLviSl/H8ShSoNEgz+os3xb0Rv b37wXUQI0qq5StSbBmFnfp4qZhXM7LzRsnEilYF4V+a9yvlj4NiTi9saRJEw9lJu7hdX PwE1QAKIjVUZUvSlKrC54eOUtxJYJ/9GjYXQe273+UFI7j7IyNoHqgs1AtwWJeKLdOc9 7uBs47LP7de+Xky2w5E0ffyvWYOuFeFPGyAX6TA4LWPHbxpa1esV1Vhyd74niTOjLOug CmXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732641188; x=1733245988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oW4RTaGV9Rp5u17+KtSXZQxBCwRUZA2L4Rf2kv6/KHg=; b=H9nIsy5k6k2lUL3H2xXa9hbzFG0igYl/v38PQ963CrJ2fO5XVfhNO6kh3UhMd1Zjl9 OSLYJenrsCak9dWXMEMh+TtXSBe+L4N9/FdJyGXBMU0Bjh6Uheobghkl2MRARkURmurs 6ygEjJOBUUZ/36g1exRfBZs1xrQ2mBgHaBGhufsg2hyTLSAs2KDQCwz9ZDvxkJs5ABmV J81Hos6YRPGc14yvoFTDTYNvIoVrwksL1nDlE6j0fDmdhmKupGXDOqcoe3UrcvTJb5Ge u5LfC3uqMlY/vKzawMv3bgpE7n5BgVmmqjIMFJ1ebH/lW8EloFxAYPvMTN6MwF9WhGQh UdPw== X-Forwarded-Encrypted: i=1; AJvYcCUAa9RFC+c8qDGLgB7Pgw5vx8jsSJ8DCg/an63ruqXGHonAzG1qtZrrZaSl8r4jPbABQNUYSlBO4A==@nongnu.org X-Gm-Message-State: AOJu0YzzbYrVFrrVHSUb2meD8MpwOWOJJocMls48ChbvGVa7QKhq5ytv 6II19cX+Hj12Vb8VDP45ufY8JE1evHU47POHCFcn7G9kBepuD0tKOAki0w== X-Gm-Gg: ASbGncueuBPYgt0tPlBwWIFYQKrTyrzYoJylEtAQLlnySqWMngapzvkiEZfUSL+6GNL BfraOil/kpBlcgeKRJZcIfBsb1vw1iOb7PdftiBW8B5F5tRt5CsWssTYvMuCnhOGw+leNd0FE/j fTiUAaSndKusD3iBePIz6SV2FQX2HhGIr7nAe5hAydd2uqIBZTXaWuAOF94g6pmXQCgIEJdp5B0 B1Ulyjh3A0RtBAlxWPySwx5ha9N2ONXF2C1Epa3gQtaS7NIFylQPsRMhoj9DwtZZXn7QRHhvrdU cFGB5w== X-Google-Smtp-Source: AGHT+IFAC37WP3a3JcvI0LxPH+c2GDToSY1JtMkpFeEDEnteAxKhHGUL6BRNk854q/SO/a/tY6wsSg== X-Received: by 2002:a17:902:ecd1:b0:212:67a5:ab24 with SMTP id d9443c01a7336-2129f28a626mr225521065ad.41.1732641188450; Tue, 26 Nov 2024 09:13:08 -0800 (PST) Received: from wheely.local0.net (124-171-72-210.tpgi.com.au. [124.171.72.210]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc21c28sm87321175ad.246.2024.11.26.09.13.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 09:13:08 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Harsh Prateek Bora , Anushree Mathur Subject: [PULL 5/6] ppc/spapr: fix drc index mismatch for partially enabled vcpus Date: Wed, 27 Nov 2024 03:12:34 +1000 Message-ID: <20241126171235.362916-6-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126171235.362916-1-npiggin@gmail.com> References: <20241126171235.362916-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Harsh Prateek Bora In case when vcpus are explicitly enabled/disabled in a non-consecutive order within a libvirt xml, it results in a drc index mismatch during vcpu hotplug later because the existing logic uses vcpu id to derive the corresponding drc index which is not correct. Use env->core_index to derive a vcpu's drc index as appropriate to fix this issue. For ex, for the given libvirt xml config: We see below error on guest console with "virsh setvcpus 5" : pseries-hotplug-cpu: CPU with drc index 10000002 already exists This patch fixes the issue by using correct drc index for explicitly enabled vcpus during init. Reported-by: Anushree Mathur Tested-by: Anushree Mathur Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- hw/ppc/spapr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 5c02037c56..0d4efaa0c0 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -701,7 +701,7 @@ static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; int i; - drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); + drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, env->core_index); if (drc) { drc_index = spapr_drc_index(drc); _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); From patchwork Tue Nov 26 17:12:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 13886237 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA46AD6552F for ; Tue, 26 Nov 2024 17:14:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tFz7v-0007Cc-7J; Tue, 26 Nov 2024 12:13:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tFz7j-00079C-0d; Tue, 26 Nov 2024 12:13:15 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tFz7h-0004Hu-BL; Tue, 26 Nov 2024 12:13:14 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-214d1c6d724so20477345ad.3; Tue, 26 Nov 2024 09:13:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1732641191; x=1733245991; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=er6EAmnjAudD3kPiQB9zkLV3SUfbN2uxnS0cWpglFxE=; b=hWTsozBEg4fBr/w3MGcqXvPvRWoIfDymNGpfCZYeRufnbhBDUDD0bt1OWSuBAZFMg9 O7Fi5hZl66UZdED7auem+lmRa4XnpOF3TcMS5F1niHCERHC3XDmPJpKMdZViXmmJ3eOO K2aBuKKpCFv11bZraZ2txw8PRiWCGNbHilVau6y1J6rIFQ3GGPLsj7SmLP+ne8ndeW5u VjNod05/sf568Z5a3TRH6Lg+srE8uhuD1c1JFIfw8y65u0I9l+dREhH+lFCo6SQVkt3X DW3BGwNWobNLqO3xZfo7DA/ltRV9TdW5a3QakqiQ2pvoeDliU43UtR9FX/Yk78GwLCn7 WHjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732641191; x=1733245991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=er6EAmnjAudD3kPiQB9zkLV3SUfbN2uxnS0cWpglFxE=; b=YdSJPpEKgaCaTe6he1AbShFUE6K3csWJiog9ixpLvXkwslCDljxdzl9G8UYxU2V1QQ gV4oe/JUNomMmCzxIoPknq8EMn+gJoIY/RNvel6z1k+T7F2jQLm312ubpqyBBCZ9f+vF n5xR9lRzlQo7SZ4o8JHV1MnH2pzh2J8rfu/US0BYsWL05P2KIwG1zKQJJ/zJpe7r/vzQ xhTRTXkNkafaTahMdbIdpvHb7gcEJZfnjnwiflzJADJuLGfIO1sDaCQ5+/oSMAsSV6X5 hfeDMVBC6GZMR0BwPax+vcGfQlcd9JgxJRDI5XhOnhq1vFlZOJ3gF8NJXUtT/DASKi5f 0a2Q== X-Forwarded-Encrypted: i=1; AJvYcCWA2vYVG/PRsSbBlmuUWSekQSK261qxyDZI5Ay+gZUcTbF3xze/16LCYc9+bIuBeoF24wzdazvGUw==@nongnu.org X-Gm-Message-State: AOJu0YzAqBE7qMEaFkG6ZMHxB+AZY1T4O24LEBGUIHfg8LqGjW2T3IHf Qzb58SUnbEiCqgEIvQT42TVuOg3UWFgTpT5X/2mVYPrwN910IXdoBbQHPQ== X-Gm-Gg: ASbGncu3csmlCCIrvyuD+ryzxqe54F84vCDtQz2QzhAI1oDYU24afZ4y+hcCOzNVez4 cglfLivdGHgpCt/ycmH65mZkKX0LWBpVQ+hk55Au5oh7/NiubLrR3ny/l3nOIWdFVEMTtFe/UKF FgmaMqBdjqednY03S+hAgtAAYKF/Y+8rIC3m+GsIvYO4Kd5OAPrmUYPsNdBCOHcEiKB5ANxwGS8 3wJ/y4B9lUgK9Mn7wbGSgHiqH+ZEV3pljVwyi0CaLldU6IFHnJ/MJAM8fnXQnHOZY52W3vN0YQb UcO16Q== X-Google-Smtp-Source: AGHT+IE5flv56BZkzOAFRRII/6UguyQi2QW7K7yaJWrdcGa555DTHLRJtWJj68CmzlMLrLrNcFKL0A== X-Received: by 2002:a17:902:ea0b:b0:211:f10e:2dce with SMTP id d9443c01a7336-2129f233babmr185866065ad.21.1732641191148; Tue, 26 Nov 2024 09:13:11 -0800 (PST) Received: from wheely.local0.net (124-171-72-210.tpgi.com.au. [124.171.72.210]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc21c28sm87321175ad.246.2024.11.26.09.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Nov 2024 09:13:10 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, BALATON Zoltan Subject: [PULL 6/6] hw/ppc/pegasos2: Fix IRQ routing from pci.0 Date: Wed, 27 Nov 2024 03:12:35 +1000 Message-ID: <20241126171235.362916-7-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241126171235.362916-1-npiggin@gmail.com> References: <20241126171235.362916-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=npiggin@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: BALATON Zoltan The MV64361 has two PCI buses one of which is used for AGP on PegasosII. So far we only emulated the PCI bus on pci.1 but some graphics cards are only recognised by some guests when connected to pci.0 corresponding to the AGP port. So far the interrupts were not routed from pci.0 so this patch fixes that allowing the use of both PCI buses. On real board only INTA and INTB are connected for AGP but to avoid surprises we connect all 4 PCI interrupt lines so pci.0 can be used for all PCI cards as well. Signed-off-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Nicholas Piggin --- hw/pci-host/mv64361.c | 1 + hw/ppc/pegasos2.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 1036d8600d..421c287eb0 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -95,6 +95,7 @@ static void mv64361_pcihost_realize(DeviceState *dev, Error **errp) &s->mem, &s->io, 0, 4, TYPE_PCI_BUS); g_free(name); pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE); + qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq)); } static Property mv64361_pcihost_props[] = { diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 8ff4a00c34..16abeaac82 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -14,6 +14,7 @@ #include "hw/sysbus.h" #include "hw/pci/pci_host.h" #include "hw/irq.h" +#include "hw/or-irq.h" #include "hw/pci-host/mv64361.h" #include "hw/isa/vt82c686.h" #include "hw/ide/pci.h" @@ -73,8 +74,11 @@ OBJECT_DECLARE_TYPE(Pegasos2MachineState, MachineClass, PEGASOS2_MACHINE) struct Pegasos2MachineState { MachineState parent_obj; + PowerPCCPU *cpu; DeviceState *mv; + IRQState pci_irqs[PCI_NUM_PINS]; + OrIRQState orirq[PCI_NUM_PINS]; qemu_irq mv_pirq[PCI_NUM_PINS]; qemu_irq via_pirq[PCI_NUM_PINS]; Vof *vof; @@ -177,7 +181,6 @@ static void pegasos2_init(MachineState *machine) pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i); } pci_bus = mv64361_get_pci_bus(pm->mv, 1); - pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS); /* VIA VT8231 South Bridge (multifunction PCI device) */ via = OBJECT(pci_new_multifunction(PCI_DEVFN(12, 0), TYPE_VT8231_ISA)); @@ -209,6 +212,31 @@ static void pegasos2_init(MachineState *machine) /* other PC hardware */ pci_vga_init(pci_bus); + /* PCI interrupt routing: lines from pci.0 and pci.1 are ORed */ + for (int h = 0; h < 2; h++) { + DeviceState *pd; + g_autofree const char *pn = g_strdup_printf("pcihost%d", h); + + pd = DEVICE(object_resolve_path_component(OBJECT(pm->mv), pn)); + assert(pd); + for (i = 0; i < PCI_NUM_PINS; i++) { + OrIRQState *ori = &pm->orirq[i]; + + if (h == 0) { + g_autofree const char *n = g_strdup_printf("pci-orirq[%d]", i); + + object_initialize_child_with_props(OBJECT(pm), n, + ori, sizeof(*ori), + TYPE_OR_IRQ, &error_fatal, + "num-lines", "2", NULL); + qdev_realize(DEVICE(ori), NULL, &error_fatal); + qemu_init_irq(&pm->pci_irqs[i], pegasos2_pci_irq, pm, i); + qdev_connect_gpio_out(DEVICE(ori), 0, &pm->pci_irqs[i]); + } + qdev_connect_gpio_out(pd, i, qdev_get_gpio_in(DEVICE(ori), h)); + } + } + if (machine->kernel_filename) { sz = load_elf(machine->kernel_filename, NULL, NULL, NULL, &pm->kernel_entry, &pm->kernel_addr, NULL, NULL, 1,