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So that driver can use regcache to recover registers after suspend and resume. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_xcvr.c | 224 +++++++++++++++++++++++++++++++-------- sound/soc/fsl/fsl_xcvr.h | 13 +++ 2 files changed, 191 insertions(+), 46 deletions(-) diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index 9c184ab73468..b77953cfaa31 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -37,6 +37,8 @@ struct fsl_xcvr { const struct fsl_xcvr_soc_data *soc_data; struct platform_device *pdev; struct regmap *regmap; + struct regmap *regmap_phy; + struct regmap *regmap_pll; struct clk *ipg_clk; struct clk *pll_ipg_clk; struct clk *phy_clk; @@ -257,7 +259,7 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) idx = BIT(phy ? 26 : 24); tidx = BIT(phy ? 27 : 25); - regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); @@ -271,6 +273,59 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) return ret; } +static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) +{ + struct device *dev = &xcvr->pdev->dev; + u32 val, idx, tidx; + int ret; + + idx = BIT(phy ? 26 : 24); + tidx = BIT(phy ? 27 : 25); + + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); + + ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, + (val & idx) == ((val & tidx) >> 1), + 10, 10000); + if (ret) + dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n", + phy ? "PHY" : "PLL", reg); + + regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); + + return ret; +} + +static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_read(xcvr, reg, val, 1); +} + +static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_write(xcvr, reg, val, 1); +} + +static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_read(xcvr, reg, val, 0); +} + +static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_write(xcvr, reg, val, 0); +} + static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) { struct device *dev = &xcvr->pdev->dev; @@ -303,55 +358,55 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) switch (xcvr->soc_data->pll_ver) { case PLL_MX8MP: /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET, - FSL_XCVR_PLL_BANDGAP_EN_VBG, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, + FSL_XCVR_PLL_BANDGAP_EN_VBG); /* PLL: CTRL0: DIV_INTEGER */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); /* PLL: NUMERATOR: MFN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); /* PLL: DENOMINATOR: MFD */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP); udelay(25); /* PLL: CTRL0: Clear Hold Ring Off */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR, - FSL_XCVR_PLL_CTRL0_HROFF, 0); + regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_HROFF); udelay(100); if (tx) { /* TX is enabled for SPDIF only */ /* PLL: POSTDIV: PDIV0 */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, - FSL_XCVR_PLL_PDIVx(log2, 0), 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, + FSL_XCVR_PLL_PDIVx(log2, 0)); /* PLL: CTRL_SET: CLKMUX0_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_CM0_EN, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_CM0_EN); } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ /* PLL: POSTDIV: PDIV1 */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, - FSL_XCVR_PLL_PDIVx(log2, 1), 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, + FSL_XCVR_PLL_PDIVx(log2, 1)); /* PLL: CTRL_SET: CLKMUX1_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_CM1_EN, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_CM1_EN); } else { /* SPDIF / ARC RX */ /* PLL: POSTDIV: PDIV2 */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, - FSL_XCVR_PLL_PDIVx(log2, 2), 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, + FSL_XCVR_PLL_PDIVx(log2, 2)); /* PLL: CTRL_SET: CLKMUX2_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_CM2_EN, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_CM2_EN); } break; case PLL_MX95: val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0); - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR, - fsl_xcvr_pll_cfg[i].mfd, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, + fsl_xcvr_pll_cfg[i].mfd); val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); break; default: dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); @@ -360,22 +415,22 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_TSDIFF_OE | - FSL_XCVR_PHY_CTRL_PHY_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_TSDIFF_OE | + FSL_XCVR_PHY_CTRL_PHY_EN); /* PHY: CTRL2_SET: EARC_TX_MODE */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, - FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, + FSL_XCVR_PHY_CTRL2_EARC_TXMS); } else if (!tx) { /* SPDIF / ARC RX mode */ if (xcvr->mode == FSL_XCVR_MODE_SPDIF) /* PHY: CTRL_SET: SPDIF_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_SPDIF_EN); else /* PHY: CTRL_SET: ARC RX setup */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_PHY_EN | - FSL_XCVR_PHY_CTRL_RX_CM_EN | - fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_PHY_EN | + FSL_XCVR_PHY_CTRL_RX_CM_EN | + fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); } dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", @@ -416,17 +471,17 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_TSDIFF_OE | - FSL_XCVR_PHY_CTRL_PHY_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_TSDIFF_OE | + FSL_XCVR_PHY_CTRL_PHY_EN); /* PHY: CTRL2_SET: EARC_TX_MODE */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, - FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, + FSL_XCVR_PHY_CTRL2_EARC_TXMS); } else { /* SPDIF mode */ /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | - FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | + FSL_XCVR_PHY_CTRL_SPDIF_EN); } dev_dbg(dev, "PLL Fexp: %u\n", freq); @@ -1206,6 +1261,49 @@ static const struct regmap_config fsl_xcvr_regmap_cfg = { .cache_type = REGCACHE_FLAT, }; +static const struct reg_default fsl_xcvr_phy_reg_defaults[] = { + { FSL_XCVR_PHY_CTRL, 0x58200804 }, + { FSL_XCVR_PHY_STATUS, 0x00000000 }, + { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 }, + { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 }, + { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 }, + { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 }, + { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 }, + { FSL_XCVR_PHY_CTRL2, 0x80000000 }, +}; + +static const struct regmap_config fsl_xcvr_regmap_phy_cfg = { + .reg_bits = 8, + .reg_stride = 4, + .val_bits = 32, + .max_register = FSL_XCVR_PHY_CTRL2_TOG, + .reg_defaults = fsl_xcvr_phy_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults), + .cache_type = REGCACHE_FLAT, + .reg_read = fsl_xcvr_phy_reg_read, + .reg_write = fsl_xcvr_phy_reg_write, +}; + +static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = { + .reg_bits = 8, + .reg_stride = 4, + .val_bits = 32, + .max_register = FSL_XCVR_PLL_STAT0_TOG, + .cache_type = REGCACHE_FLAT, + .reg_read = fsl_xcvr_pll_reg_read, + .reg_write = fsl_xcvr_pll_reg_write, +}; + +static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = { + .reg_bits = 8, + .reg_stride = 4, + .val_bits = 32, + .max_register = FSL_XCVR_GP_PLL_STATUS_TOG, + .cache_type = REGCACHE_FLAT, + .reg_read = fsl_xcvr_pll_reg_read, + .reg_write = fsl_xcvr_pll_reg_write, +}; + static void reset_rx_work(struct work_struct *work) { struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); @@ -1421,6 +1519,40 @@ static int fsl_xcvr_probe(struct platform_device *pdev) return PTR_ERR(xcvr->regmap); } + if (xcvr->soc_data->use_phy) { + xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, + &fsl_xcvr_regmap_phy_cfg); + if (IS_ERR(xcvr->regmap_phy)) { + dev_err(dev, "failed to init XCVR PHY regmap: %ld\n", + PTR_ERR(xcvr->regmap_phy)); + return PTR_ERR(xcvr->regmap_phy); + } + + switch (xcvr->soc_data->pll_ver) { + case PLL_MX8MP: + xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, + &fsl_xcvr_regmap_pllv0_cfg); + if (IS_ERR(xcvr->regmap_pll)) { + dev_err(dev, "failed to init XCVR PLL regmap: %ld\n", + PTR_ERR(xcvr->regmap_pll)); + return PTR_ERR(xcvr->regmap_pll); + } + break; + case PLL_MX95: + xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, + &fsl_xcvr_regmap_pllv1_cfg); + if (IS_ERR(xcvr->regmap_pll)) { + dev_err(dev, "failed to init XCVR PLL regmap: %ld\n", + PTR_ERR(xcvr->regmap_pll)); + return PTR_ERR(xcvr->regmap_pll); + } + break; + default: + dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); + return -EINVAL; + } + } + xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(xcvr->reset)) { dev_err(dev, "failed to get XCVR reset control\n"); diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h index c72cb05184df..dade3945cc0c 100644 --- a/sound/soc/fsl/fsl_xcvr.h +++ b/sound/soc/fsl/fsl_xcvr.h @@ -234,6 +234,7 @@ #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30) #define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15) +#define FSL_XCVR_PHY_AI_CTRL_AI_RWB BIT(31) #define FSL_XCVR_PLL_CTRL0 0x00 #define FSL_XCVR_PLL_CTRL0_SET 0x04 @@ -241,13 +242,25 @@ #define FSL_XCVR_PLL_NUM 0x20 #define FSL_XCVR_PLL_DEN 0x30 #define FSL_XCVR_PLL_PDIV 0x40 +#define FSL_XCVR_PLL_BANDGAP 0x50 #define FSL_XCVR_PLL_BANDGAP_SET 0x54 +#define FSL_XCVR_PLL_STAT0 0x60 +#define FSL_XCVR_PLL_STAT0_TOG 0x6c + #define FSL_XCVR_PHY_CTRL 0x00 #define FSL_XCVR_PHY_CTRL_SET 0x04 #define FSL_XCVR_PHY_CTRL_CLR 0x08 +#define FSL_XCVR_PHY_CTRL_TOG 0x0c +#define FSL_XCVR_PHY_STATUS 0x10 +#define FSL_XCVR_PHY_ANALOG_TRIM 0x20 +#define FSL_XCVR_PHY_SLEW_RATE_TRIM 0x30 +#define FSL_XCVR_PHY_DATA_TEST_DELAY 0x40 +#define FSL_XCVR_PHY_TEST_CTRL 0x50 +#define FSL_XCVR_PHY_DIFF_CDR_CTRL 0x60 #define FSL_XCVR_PHY_CTRL2 0x70 #define FSL_XCVR_PHY_CTRL2_SET 0x74 #define FSL_XCVR_PHY_CTRL2_CLR 0x78 +#define FSL_XCVR_PHY_CTRL2_TOG 0x7c #define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0) #define FSL_XCVR_PLL_CTRL0_HROFF BIT(13) From patchwork Wed Nov 27 03:00:35 2024 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Dn0/57H+1NMYL0hF6r4QP9ASTbtZOyWZqGE6U2pAWr3W6xtpKJdGsf955TRfZ/ajxn3fhcaPX+WDDt1klWy9wI7882XLWyNDmfDeKKr3mdIIirRTzafa1Gqp0VyJLYdpphYz5IpfyKIrOBp+5ym9C6+Wt4cyUujsNZcXdoR+ctLfi573TZeWc1uZ/JPetke75E7TShquxA9XGIp4KLYku2HjOLOYRo6V9KuNOJHXixIJgANeS8lNpea2Y29kAPz8TsBvO6r6G2Mw6DtyYCnmTKxkwmXX0xBrw5RrNWWswp6P6jjxg0M8/0xE5w8tW6PweuLaHvKm7e6fwmtlWxOIHSXGG7C9GZzy2ULjLV0eM8YpXaW5Oh97PGo27NibJXkCXCuhlfB5NXS14Y/gik/iNT5M48WFDxVDslLmCgoJNJ1Ga+LixwAuy/ETMJ4FViqRsG/B3yizbnaNHRoCHNFxj3Yck9gckEKKdLn+JhhvczHxu2Yjb9rmvwCZ3gZkUbxja2OqFOkJ9MARW0oafDYvnQsMeIURzdTFkeaMCbV/ehWSZMODyKKymbytfXGwCj6yqe+dmvSaYKuLcv4mx1seCunHuH+mSvGL5rAIzfILmzfrG7iMnZu+xF562Y4eb6Z8EUb61JY0A1AnGsjlhQSBJpmK8s/uQRdcTucoNnxJle9+grMOQ0yVxyX+u8QNg1uQmDzGYDYr1Qi20fUqMWXB8kP7lQSuQHe8y9oFBwppdDawOXIh4MHoVWGRLzms4ct3Z/lip0z9aNM+9uUeGKveGa5NLx03ZjkUmLarR/TNthx6GefRtS/3TGztiCFVqvpN/D/GFEYxnXePaNTtXV/w4Jo3gQyYTpbDccwqqzIb3Usd+K08doiXdftCNbefeD1GT+xOG4hGGlNuqoHurGLPe62AJ9TByporyjYlUpuIt0yjSoD6RnIwPL7DEUC7pshOkJbBjB+K9RXBsn4pIYXUOCv0RCYlLsWBDxvD9Ufy+S8TCC0J0mUT0mpOdi8srZqvgMeqBvzNHmyjxF8pr0uwOYRVhk6WV3lvT0r3Kv/iB1aniV47pLuz0wBle2hSy9ZQ2sMW7GZOEwxsBs7n83aDVf8zbmkonMQ35PbrbPCXahEtgFFupyQXbJOeJeU26Onm32lyFG71kLEaF0w57eYCm+Ce09AQ7zp1XoLzO9L6bdc9IvAD0nr0pm/TObuK70jlDxRCDWqFiBtSJ5L5hFxOjCHmT3zXDwvoxOfGiRhac4SFTozy9EIfOXXF9I87XZxu7c9Z0cpaUMkiUFX8uAgnVZLKfU5y17MlGp8CfUyWrQitW5Q5QM1NRpcfbo8+baygSyd60m5JNPTN4a5qqtbZyjbQVe5SVQqcSuDz49ESXqwjwzDScr5qAlL2mbZuyYbd5adNLZGNsKc3ipegt+FV4TGJMh/PzLTY980ih+LSVXVVw6xVhw++CDPdHUm1q0oykVKxvPLPuM86H0NdYvd24tnBymE1P5aHMytBwQey/0rELIuuoLEvOnceo6ptF8VgniJlXalt9fAc/sYj7ZfE5oEF3OYB+sbgZAt1wVJ88AvXncB6+p5K3+KbWtGPwURB X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5c6c566a-45be-45f2-3afe-08dd0e8fc40b X-MS-Exchange-CrossTenant-AuthSource: AM0PR04MB7044.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Nov 2024 03:01:19.1702 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zjdUTbDzBTOQGBfsrfcnv/UXlyOLRxek8S1sj2/af6wSHMS2iubvASjnyuKhXwTOZaZsEHAXruYsItRWJt+rjw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7771 Use regcache_sync() to recover the registers of controller, PHY and PLL after suspend and resume. In order to recover the registers need to avoid use the *_SET, *_CLR and *_TOG registers. Recovery of the registers should be done before loading XCVR firmware otherwise some registers set by firmware are overwritten. Besides only in eARC mode is it necessary to load XCVR firmware. Signed-off-by: Shengjiu Wang Signed-off-by: Chancel Liu --- sound/soc/fsl/fsl_xcvr.c | 160 +++++++++++++++++++++++++++++---------- 1 file changed, 118 insertions(+), 42 deletions(-) diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index b77953cfaa31..4524cb7ada2e 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -503,7 +503,7 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, switch (xcvr->mode) { case FSL_XCVR_MODE_SPDIF: if (xcvr->soc_data->spdif_only && tx) { - ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, + ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); if (ret < 0) { @@ -521,8 +521,8 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, return ret; } - ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, - FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); + ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, + FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); if (ret < 0) { dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); return ret; @@ -539,11 +539,11 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, * Clear RX FIFO, flip RX FIFO bits, * disable eARC related HW mode detects */ - ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, - FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | - FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | - FSL_XCVR_RX_DPTH_CTRL_COMP | - FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); + ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, + FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | + FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | + FSL_XCVR_RX_DPTH_CTRL_COMP | + FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); if (ret < 0) { dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); return ret; @@ -560,18 +560,18 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, case FSL_XCVR_MODE_EARC: if (!tx) { /** Clear RX FIFO, flip RX FIFO bits */ - ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, - FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | - FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); + ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, + FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | + FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); if (ret < 0) { dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); return ret; } /** Enable eARC related HW mode detects */ - ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, - FSL_XCVR_RX_DPTH_CTRL_COMP | - FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); + ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, + FSL_XCVR_RX_DPTH_CTRL_COMP | + FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); if (ret < 0) { dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); return ret; @@ -751,9 +751,9 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, } fallthrough; case FSL_XCVR_MODE_SPDIF: - ret = regmap_write(xcvr->regmap, - FSL_XCVR_TX_DPTH_CTRL_SET, - FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); + ret = regmap_set_bits(xcvr->regmap, + FSL_XCVR_TX_DPTH_CTRL, + FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); if (ret < 0) { dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); goto release_lock; @@ -809,9 +809,9 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, if (tx) { switch (xcvr->mode) { case FSL_XCVR_MODE_SPDIF: - ret = regmap_write(xcvr->regmap, - FSL_XCVR_TX_DPTH_CTRL_CLR, - FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); + ret = regmap_clear_bits(xcvr->regmap, + FSL_XCVR_TX_DPTH_CTRL, + FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); if (ret < 0) { dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); goto release_lock; @@ -1224,6 +1224,7 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_TX_DPTH_CTRL: case FSL_XCVR_TX_DPTH_CTRL_SET: case FSL_XCVR_TX_DPTH_CTRL_CLR: case FSL_XCVR_TX_DPTH_CTRL_TOG: @@ -1245,7 +1246,49 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) { - return fsl_xcvr_readable_reg(dev, reg); + switch (reg) { + case FSL_XCVR_EXT_STATUS: + case FSL_XCVR_EXT_ISR: + case FSL_XCVR_EXT_ISR_SET: + case FSL_XCVR_EXT_ISR_CLR: + case FSL_XCVR_EXT_ISR_TOG: + case FSL_XCVR_ISR: + case FSL_XCVR_ISR_SET: + case FSL_XCVR_ISR_CLR: + case FSL_XCVR_ISR_TOG: + case FSL_XCVR_PHY_AI_CTRL: + case FSL_XCVR_PHY_AI_CTRL_SET: + case FSL_XCVR_PHY_AI_CTRL_CLR: + case FSL_XCVR_PHY_AI_CTRL_TOG: + case FSL_XCVR_PHY_AI_RDATA: + case FSL_XCVR_RX_CS_DATA_0: + case FSL_XCVR_RX_CS_DATA_1: + case FSL_XCVR_RX_CS_DATA_2: + case FSL_XCVR_RX_CS_DATA_3: + case FSL_XCVR_RX_CS_DATA_4: + case FSL_XCVR_RX_CS_DATA_5: + case FSL_XCVR_RX_DPTH_CNTR_CTRL: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_RX_DPTH_TSCR: + case FSL_XCVR_RX_DPTH_BCR: + case FSL_XCVR_RX_DPTH_BCTR: + case FSL_XCVR_RX_DPTH_BCRR: + case FSL_XCVR_TX_DPTH_CNTR_CTRL: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_TX_DPTH_TSCR: + case FSL_XCVR_TX_DPTH_BCR: + case FSL_XCVR_TX_DPTH_BCTR: + case FSL_XCVR_TX_DPTH_BCRR: + case FSL_XCVR_DEBUG_REG_0: + case FSL_XCVR_DEBUG_REG_1: + return true; + default: + return false; + } } static const struct regmap_config fsl_xcvr_regmap_cfg = { @@ -1586,6 +1629,10 @@ static int fsl_xcvr_probe(struct platform_device *pdev) platform_set_drvdata(pdev, xcvr); pm_runtime_enable(dev); regcache_cache_only(xcvr->regmap, true); + if (xcvr->soc_data->use_phy) { + regcache_cache_only(xcvr->regmap_phy, true); + regcache_cache_only(xcvr->regmap_pll, true); + } /* * Register platform component before registering cpu dai for there @@ -1624,7 +1671,8 @@ static int fsl_xcvr_runtime_suspend(struct device *dev) struct fsl_xcvr *xcvr = dev_get_drvdata(dev); int ret; - if (!xcvr->soc_data->spdif_only) { + if (!xcvr->soc_data->spdif_only && + xcvr->mode == FSL_XCVR_MODE_EARC) { /* Assert M0+ reset */ ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, FSL_XCVR_EXT_CTRL_CORE_RESET, @@ -1634,6 +1682,10 @@ static int fsl_xcvr_runtime_suspend(struct device *dev) } regcache_cache_only(xcvr->regmap, true); + if (xcvr->soc_data->use_phy) { + regcache_cache_only(xcvr->regmap_phy, true); + regcache_cache_only(xcvr->regmap_pll, true); + } clk_disable_unprepare(xcvr->spba_clk); clk_disable_unprepare(xcvr->phy_clk); @@ -1678,6 +1730,12 @@ static int fsl_xcvr_runtime_resume(struct device *dev) goto stop_phy_clk; } + ret = reset_control_deassert(xcvr->reset); + if (ret) { + dev_err(dev, "failed to deassert M0+ reset.\n"); + goto stop_spba_clk; + } + regcache_cache_only(xcvr->regmap, false); regcache_mark_dirty(xcvr->regmap); ret = regcache_sync(xcvr->regmap); @@ -1687,31 +1745,49 @@ static int fsl_xcvr_runtime_resume(struct device *dev) goto stop_spba_clk; } - if (xcvr->soc_data->spdif_only) - return 0; + if (xcvr->soc_data->use_phy) { + ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, + FSL_XCVR_PHY_AI_CTRL_AI_RESETN); + if (ret < 0) { + dev_err(dev, "Error while release PHY reset: %d\n", ret); + goto stop_spba_clk; + } - ret = reset_control_deassert(xcvr->reset); - if (ret) { - dev_err(dev, "failed to deassert M0+ reset.\n"); - goto stop_spba_clk; - } + regcache_cache_only(xcvr->regmap_phy, false); + regcache_mark_dirty(xcvr->regmap_phy); + ret = regcache_sync(xcvr->regmap_phy); + if (ret) { + dev_err(dev, "failed to sync phy regcache.\n"); + goto stop_spba_clk; + } - ret = fsl_xcvr_load_firmware(xcvr); - if (ret) { - dev_err(dev, "failed to load firmware.\n"); - goto stop_spba_clk; + regcache_cache_only(xcvr->regmap_pll, false); + regcache_mark_dirty(xcvr->regmap_pll); + ret = regcache_sync(xcvr->regmap_pll); + if (ret) { + dev_err(dev, "failed to sync pll regcache.\n"); + goto stop_spba_clk; + } } - /* Release M0+ reset */ - ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, - FSL_XCVR_EXT_CTRL_CORE_RESET, 0); - if (ret < 0) { - dev_err(dev, "M0+ core release failed: %d\n", ret); - goto stop_spba_clk; - } + if (xcvr->mode == FSL_XCVR_MODE_EARC) { + ret = fsl_xcvr_load_firmware(xcvr); + if (ret) { + dev_err(dev, "failed to load firmware.\n"); + goto stop_spba_clk; + } - /* Let M0+ core complete firmware initialization */ - msleep(50); + /* Release M0+ reset */ + ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, + FSL_XCVR_EXT_CTRL_CORE_RESET, 0); + if (ret < 0) { + dev_err(dev, "M0+ core release failed: %d\n", ret); + goto stop_spba_clk; + } + + /* Let M0+ core complete firmware initialization */ + msleep(50); + } return 0;