From patchwork Wed Nov 27 10:30:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13886812 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08CF71991B2; Wed, 27 Nov 2024 10:30:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703435; cv=none; b=kcf8vbgQyWTPzBckC2uESiINakk0b+d83CD/JdP4+ILvDYUY0ELTeNlag8bXQaaDBmvUJxpQV3URv9vav3u2780h2vjZzEO9C+xKwcRRtEKUmYPZOw2OZF2GTH97AhsJPBvjbBmt9D4c8l3GNsirEcmj+EtduHk2lwyv0J4cico= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703435; c=relaxed/simple; bh=xKvC8c0LPS2zto1FLCcDihb3dhIOCSAgeRGoSrmHlcY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LaX6HEqBFOlHiQU29iNKjwbGmVOALz7Vz8BC0Ck+t2O/FuoAuRlX0aJr4Nh4G1o2LPKKTCzhwwyeXerXeAmLF27hq8iR3b7vQNGwfatuhHoyhB/sEc748LvmvaHstXcWh1HQ9U+KorIj+pHiN8CWYzwS/VCL5nI12JPwY+tYbbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CTb5G3cY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CTb5G3cY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D9936C4CECC; Wed, 27 Nov 2024 10:30:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732703434; bh=xKvC8c0LPS2zto1FLCcDihb3dhIOCSAgeRGoSrmHlcY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CTb5G3cYie5TF+VvR21B+rHiWXqE0oxBr0m4lPq0GI8eayHQ8dq5VEoDOFUkWnzlk 9NlvJ+NfyLb4NKX356tTTrhhrc+NC/ZziMnEmIT6sW115NVQO5U75MhA3+JGew5tya mL1yBwC80VDgZofrhePHHouVOTo7rhngr0c7jFC3FAGGX/r7w4UkGF1YuuUcxw2EFo 4hnjHwJgjgeN0g4HOuACYrIZE3h+tbRKu/telI62y1V/us4Ji+A9EPCtwFaq6VgHPL XMidNB4E3Cu6zwAE5dGJfJnTACeYCz72e6/6Tn5KrbM3f5blWIJ4ZfVkY9CoEkiV0i fDF/KRxuTcewA== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , stable@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v5 1/6] PCI: dwc: ep: iATU registers must be written after the BAR_MASK Date: Wed, 27 Nov 2024 11:30:17 +0100 Message-ID: <20241127103016.3481128-9-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241127103016.3481128-8-cassel@kernel.org> References: <20241127103016.3481128-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2565; i=cassel@kernel.org; h=from:subject; bh=xKvC8c0LPS2zto1FLCcDihb3dhIOCSAgeRGoSrmHlcY=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLdvuxdH5onvsSPY+fHxq32Kw1Wbyp6IXNCVnPJsjUSO 48utjrp01HKwiDGxSArpsji+8Nlf3G3+5TjindsYOawMoEMYeDiFICJ3NzP8L/i9NsphxjEb8kX 26s07D5Qsu5Pn8Od5sL1qy5xLC7uyDjMyHBP8nKaR8fFOyJrjNUbZip6CTRayRn/6eWp5J+rM3V qLzcA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. If we do not write the BAR_MASK before writing the iATU registers, we are relying the reset value of the BAR_MASK being larger than the requested size of the first set_bar() call. The reset value of the BAR_MASK is SoC dependent. Thus, if the first set_bar() call requests a size that is larger than the reset value of the BAR_MASK, the iATU will try to write to read-only bits, which will cause the iATU to end up redirecting to a physical address that is different from the address that was intended. Thus, we should always write the iATU registers after writing the BAR_MASK. Cc: stable@vger.kernel.org Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 28 ++++++++++--------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f3ac7d46a855..bad588ef69a4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -222,19 +222,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) return -EINVAL; - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - if (!(flags & PCI_BASE_ADDRESS_SPACE)) - type = PCIE_ATU_TYPE_MEM; - else - type = PCIE_ATU_TYPE_IO; - - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); - if (ret) - return ret; - if (ep->epf_bar[bar]) - return 0; + goto config_atu; + + reg = PCI_BASE_ADDRESS_0 + (4 * bar); dw_pcie_dbi_ro_wr_en(pci); @@ -246,9 +237,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); } - ep->epf_bar[bar] = epf_bar; dw_pcie_dbi_ro_wr_dis(pci); +config_atu: + if (!(flags & PCI_BASE_ADDRESS_SPACE)) + type = PCIE_ATU_TYPE_MEM; + else + type = PCIE_ATU_TYPE_IO; + + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + if (ret) + return ret; + + ep->epf_bar[bar] = epf_bar; + return 0; } From patchwork Wed Nov 27 10:30:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13886813 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3756619883C for ; Wed, 27 Nov 2024 10:30:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 27 Nov 2024 10:30:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732703437; bh=j9gRtPAhuBuJha0qKMSBpmyuO6GmdHdWJO5z2g+PXrk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CP3eroBJdVTrbgRb4jgXVtAcNayOhObldsUsqWkmJ1l9ft+QoybZh9qen1nGupPdw EoQ5sfWFSCxhTnVOD1y3HKnx/okkqNYmlgU0b8hCm8SOJd8gUlpgzszMIEAwZ+EwYx scqY5mUXQ/P6lEk/0uq9+GvpbYBOHk3F3lnhpRRJw6Ojfgw3AUKrEJiNya9JSkNkCX HlQS8F10yN10qLjJaV6SSedzewQmC0LDVWZuNCsjBQyNnfDf79NTX7yv2fdN0wDADq VPf2QOldcoz8t1jPbF2RtlfkYkbZz4hwJ/PG8PSbXlrldy49j5Qh94L3TBkiVqJRfM nVnpAPtHx297w== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Jon Mason , Frank Li Cc: Damien Le Moal , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v5 2/6] PCI: dwc: ep: Add missing checks when dynamically changing a BAR Date: Wed, 27 Nov 2024 11:30:18 +0100 Message-ID: <20241127103016.3481128-10-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241127103016.3481128-8-cassel@kernel.org> References: <20241127103016.3481128-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2208; i=cassel@kernel.org; h=from:subject; bh=j9gRtPAhuBuJha0qKMSBpmyuO6GmdHdWJO5z2g+PXrk=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLdvuyt6H53t+Aca/3iexy3YrimS+eeEc+wudIQIOUl8 KPK+eGHjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEykI5Phf+1ypXi3F5vEb63z XplmItsqp2Q1+Vl9g9Rq/jbezWuc/zEyfJ3neuBtz97/yiIb3t+YM+Pb/6i37gEcnz76lfq773d axQkA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA In commit 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address") set_bar() was modified to support dynamically changing the physical address of a BAR. This means that set_bar() can be called twice, without ever calling clear_bar(), as calling clear_bar() would clear the BAR's PCI address assigned by the host). This can only be done if the new BAR configuration doesn't fundamentally differ from the existing BAR configuration. Add these missing checks. While at it, add comments which clarifies the support for dynamically changing the physical address of a BAR. (Which was also missing.) Fixes: 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address") Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index bad588ef69a4..01c739aaf61a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -222,8 +222,28 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) return -EINVAL; - if (ep->epf_bar[bar]) + /* + * Certain EPF drivers dynamically change the physical address of a BAR + * (i.e. they call set_bar() twice, without ever calling clear_bar(), as + * calling clear_bar() would clear the BAR's PCI address assigned by the + * host). + */ + if (ep->epf_bar[bar]) { + /* + * We can only dynamically change a BAR if the new configuration + * doesn't fundamentally differ from the existing configuration. + */ + if (ep->epf_bar[bar]->barno != bar || + ep->epf_bar[bar]->size != size || + ep->epf_bar[bar]->flags != flags) + return -EINVAL; + + /* + * When dynamically changing a BAR, skip writing the BAR reg, as + * that would clear the BAR's PCI address assigned by the host. + */ goto config_atu; + } reg = PCI_BASE_ADDRESS_0 + (4 * bar); From patchwork Wed Nov 27 10:30:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13886814 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48A5919883C for ; Wed, 27 Nov 2024 10:30:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703442; cv=none; b=VKRRRM1KPKibeHuJHTlWiKgyzi6Crp/qHvkbXZJO4YPpieLVUF5PGkThd/zNmPpV5H/jbX70nXF86ogOx4eD0QrXEC6CT2gaSycVZAnLCn7vQnYNJ0l+0v7x44s84ujr7u+7LEs+z0Eujv3aID6rLabwgx6mkgIS8CnBESi4D2Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703442; c=relaxed/simple; bh=wjELfxA42eHfRs0SsDqkNakU9ZOrveNgVLE1pGsZ14E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kq2A/qLqrFcZczlxCM2B9biyIwue3WO+Gc85Yn9EC5yt1JjIa7MdaLDUp1G4ZDyg3rdtDTKZjvk4Ug6rZZgvEG8Doro8NagP9DqRrsnN7Kj1wVU4H9wX8eMoKmVIJXWb7FvA8m3NH/FcmBG9YHWvIM5tcLJ+6fIPXCGPWZih9Rw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jKCYsJlG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jKCYsJlG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A659C4CECC; Wed, 27 Nov 2024 10:30:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732703440; bh=wjELfxA42eHfRs0SsDqkNakU9ZOrveNgVLE1pGsZ14E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jKCYsJlGR3mX4rzM+IDLTQAa/JvJY22aXoGvy+lESpDzxUoY/koEe76o/+nnWo3CI lZYfASKgDpMNWOjad1rGWToTs1eX21oSXFy8HAau218WKTfHMlKOhJa9JbEDRttBdl ny5G0h4UuwDxWsZdggDR3gOmGe1xM3k1dvNJX+9cJ1rVgFvLMleqyvg+0I/1ccbW7p Prr7Ps+eotw3uCYg3a7p93QIbmLRW5270ceFCmtmEbmtzGQJiVKCz92EcqBZGKmQO4 EPfg9OkJ57Lq0iHsQpfs5NqC9BISD7tR8J+KVZAh4YrmioWsmB6nu9ZCb7IUp80S2b H5KWTQlN50zSw== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v5 3/6] PCI: dwc: ep: Add 'address' alignment to 'size' check in dw_pcie_prog_ep_inbound_atu() Date: Wed, 27 Nov 2024 11:30:19 +0100 Message-ID: <20241127103016.3481128-11-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241127103016.3481128-8-cassel@kernel.org> References: <20241127103016.3481128-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4323; i=cassel@kernel.org; h=from:subject; bh=wjELfxA42eHfRs0SsDqkNakU9ZOrveNgVLE1pGsZ14E=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLdvuyV6S9oM5nVfz689wzTp1A2lj3mW6rs/B/E622av JLHNVCzo5SFQYyLQVZMkcX3h8v+4m73KccV79jAzGFlAhnCwMUpABMp2cDwP2hCsUJn5/p/F9RS 3tabnfR8HmW9UeDRS3dLld8/2vuuPGZkeKl+8e4klRwn898Ffzy9nfbyO/hs3hN1aL32wmVCk3s ecAEA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA dw_pcie_prog_ep_inbound_atu() is used to program an inbound iATU in "BAR Match Mode". A memory address returned by e.g. kmalloc() is guaranteed to have natural alignment (aligned to the size of the allocation). It is however not guaranteed that pci_epc_set_bar() (and thus dw_pcie_prog_ep_inbound_atu()) is supplied an address that has natural alignment. (An EPF driver can send in an arbitrary physical address to pci_epc_set_bar().) The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. Add a check to ensure that the physical address programmed in the iATU is aligned to the size of the BAR (BAR_MASK+1), as without this, we can get hard to debug errors, as we could write to bits that are read-only (without getting a write error), which could cause the iATU to end up redirecting to a physical address that is different from the address that we intended. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 +++++--- drivers/pci/controller/dwc/pcie-designware.c | 5 +++-- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 01c739aaf61a..4914751950cb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -128,7 +128,8 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, - dma_addr_t cpu_addr, enum pci_barno bar) + dma_addr_t cpu_addr, enum pci_barno bar, + size_t size) { int ret; u32 free_win; @@ -145,7 +146,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, } ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type, - cpu_addr, bar); + cpu_addr, bar, size); if (ret < 0) { dev_err(pci->dev, "Failed to program IB window\n"); return ret; @@ -265,7 +266,8 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, else type = PCIE_ATU_TYPE_IO; - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar, + size); if (ret) return ret; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..3c683b6119c3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -597,11 +597,12 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, } int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar) + int type, u64 cpu_addr, u8 bar, size_t size) { u32 retries, val; - if (!IS_ALIGNED(cpu_addr, pci->region_align)) + if (!IS_ALIGNED(cpu_addr, pci->region_align) || + !IS_ALIGNED(cpu_addr, size)) return -EINVAL; dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..fc0872711672 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -491,7 +491,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u64 size); int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar); + int type, u64 cpu_addr, u8 bar, size_t size); void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci); From patchwork Wed Nov 27 10:30:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13886815 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 045DBD2FB for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YiKtN7ud" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 87EE6C4CED3; Wed, 27 Nov 2024 10:30:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732703443; bh=obhY6AtGTkukXDhvCiyEMdDJkOGz3EhqkpEu/0NcHv0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YiKtN7udK3IURdKdjxAN1iEPHZJTVTsd91/m2f6xlPXpZhdnjB1jTxac+Q9yH1gDQ UT/d0fI9TkqdLGoSixtO7tHV1KOxst57tE99mUSOQs4JHACKkPndgSGivLEniflIzA p/sHfKZpgXYmLSGFKD3YOZcI2jv13Mk8aguU/WO0yShrnUYVhtjXuHZ7gJxGmD6kL4 Fc7kw7wGurJygQjdTEVoUYGJPHRE+yBCzc30f37WdmiJXj69jB6TtgXbsf2x9cPOs+ ayaRSk6tlS8FZHTLVQzgDpExiv4Gkj3RoGVf/XQfcTxllro898pVNUAN0sjPp+pYeA CjFqvL8aasdMQ== From: Niklas Cassel To: Jesper Nilsson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Niklas Cassel , linux-arm-kernel@axis.com, linux-pci@vger.kernel.org Subject: [PATCH v5 4/6] PCI: artpec6: Implement dw_pcie_ep operation get_features Date: Wed, 27 Nov 2024 11:30:20 +0100 Message-ID: <20241127103016.3481128-12-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241127103016.3481128-8-cassel@kernel.org> References: <20241127103016.3481128-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1719; i=cassel@kernel.org; h=from:subject; bh=obhY6AtGTkukXDhvCiyEMdDJkOGz3EhqkpEu/0NcHv0=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLdvuyL+BsRfMr+8CHWv/89zZeVmn9YExg4+Y2BR2Hm1 aAr7auiOkpZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCRyYsZ/rvJbZ3rm7PoSoh7 q+KRLxOnGPg6FZpwvtA4ct1ev9VcuZmR4ae6kdX+xwuDVK7O+N1/p3bZxvarclz+zqfTvnL8+jN PjgcA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA All non-DWC EPC drivers implement (struct pci_epc *)->ops->get_features(). All DWC EPC drivers implement (struct dw_pcie_ep *)->ops->get_features(), except for pcie-artpec6.c. epc_features has been required in pci-epf-test.c since commit 6613bc2301ba ("PCI: endpoint: Fix NULL pointer dereference for ->get_features()"). A follow-up commit will make further use of epc_features in EPC core code. Implement epc_features in the only EPC driver where it is currently not implemented. Signed-off-by: Niklas Cassel Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam Acked-by: Jesper Nilsson --- drivers/pci/controller/dwc/pcie-artpec6.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index f8e7283dacd4..234c8cbcae3a 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -369,9 +369,22 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static const struct pci_epc_features artpec6_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, +}; + +static const struct pci_epc_features * +artpec6_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &artpec6_pcie_epc_features; +} + static const struct dw_pcie_ep_ops pcie_ep_ops = { .init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, + .get_features = artpec6_pcie_get_features, }; static int artpec6_pcie_probe(struct platform_device *pdev) From patchwork Wed Nov 27 10:30:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13886816 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D60D4D2FB for ; Wed, 27 Nov 2024 10:30:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703446; cv=none; b=gybSMC2UKKIq+sHE578rN2MPNEB20g3I7FvzGjF63PkCGFlvU1gzYKifoHopmZw2I5Zf3YUOkPE8uqmmKSFGaNQeu2u1tKay3+vZbIhUvm+fESzuDSlkFf7L/AhIZdFX7eVyq8l71PsUlQYGJleEwkCz6JAxqOwzQv6Beed5VRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703446; c=relaxed/simple; bh=JPAPPTYojFjkEssBwOlkkI+afZc5nd+o0CH9b5v2RkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lIF/gkC1LfjoBoPrkhmqaMWc52gIiQwtxX9IHyyTizIpCbi8Gje5tUZkMtWwYBYQKYQ/zOhN7V/PGTN1A8+38FCuGXPdAMiKTMSyvc23CtNYDo8IuylDjY35ONShiBRUeKLnKuBBfMV7HM/QmHi2rIQKKj1C6t4tGUz/gXEYjkA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QlvVic8/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QlvVic8/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 836AFC4CED2; Wed, 27 Nov 2024 10:30:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732703446; bh=JPAPPTYojFjkEssBwOlkkI+afZc5nd+o0CH9b5v2RkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QlvVic8/kl3lHliQIpaZ8FOlNQROmTYWJOpiqgzZlZpBR+Jd0AB0vETBYhO8hiXxL fcKYtypjrsacRov4fLOnfMSh6wzL2dtV2QtqysjiPD/Yrldj50Mwi0A+nM7DefIyII XDktBOPCFnfXFjDUXYwdqZdSXgLEmcpMyRMeHEHjZp+G8bC3OucNxI8U++TlflwBb3 HzzOB1wJJjh9G6V3/urWvzADtciQv8j00Mtr4IKSgLVNny9Aaz+eJTs7Nx8Tn6Q7wn xRBIql+2X2C/7tagdhdQYJb3xj/zmPOQSWBkJ/kCt9utz7U4GCdmxxdXezapEQ+sbR PEc16Nyc8ph5A== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v5 5/6] PCI: endpoint: Add size check for fixed size BARs in pci_epc_set_bar() Date: Wed, 27 Nov 2024 11:30:21 +0100 Message-ID: <20241127103016.3481128-13-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241127103016.3481128-8-cassel@kernel.org> References: <20241127103016.3481128-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1895; i=cassel@kernel.org; h=from:subject; bh=JPAPPTYojFjkEssBwOlkkI+afZc5nd+o0CH9b5v2RkU=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLdvuxj7s+s8+wWv5BtsZrvU1HMxXzfGXvP8cwT5p1wK VCr9f/SjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAEykipWRYZcix5PbRyUP6li/ /GAueM8/KO7jhJaCKqnFsvtnPN6z8hvD/3LN7tkHl9QmJ004IsOYq6bLod5o17BA1fHM21/GpbL BvAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A BAR of type BAR_FIXED has a fixed BAR size (the size cannot be changed). When using pci_epf_alloc_space() to allocate backing memory for a BAR, pci_epf_alloc_space() will always set the size to the fixed BAR size if the BAR type is BAR_FIXED (and will give an error if you the requested size is larger than the fixed BAR size). However, some drivers might not call pci_epf_alloc_space() before calling pci_epc_set_bar(), so add a check in pci_epc_set_bar() to ensure that an EPF driver cannot set a size different from the fixed BAR size, if the BAR type is BAR_FIXED. The pci_epc_function_is_valid() check is removed because this check is now done by pci_epc_get_features(). Signed-off-by: Niklas Cassel Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index bed7c7d1fe3c..c69c133701c9 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -609,10 +609,17 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { - int ret; + const struct pci_epc_features *epc_features; + enum pci_barno bar = epf_bar->barno; int flags = epf_bar->flags; + int ret; - if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + epc_features = pci_epc_get_features(epc, func_no, vfunc_no); + if (!epc_features) + return -EINVAL; + + if (epc_features->bar[bar].type == BAR_FIXED && + (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || From patchwork Wed Nov 27 10:30:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13886817 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D36918E0E for ; Wed, 27 Nov 2024 10:30:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703449; cv=none; b=ToEX5oO+EyJ24kWlMEKYWX7u8PTZvcix6PYboAjThV6brCzrcCfCBLTfGiQl5xCJjkLr5xzc7XIkoWe/PSgOPwVHliAvsDsUwD20gT3d1U2NFFJvGC0E3gijWMC5a3Jdd6cGSUC9lf35MUevHHSWfJRzhO5IbhXU03CAZmSXP0M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732703449; c=relaxed/simple; bh=yoUldh/uZchEIwYIHV5nk8tHJLu9/aT+70+9evMH1PU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aME+cyEPobzSTjubLlQYJuoMF207LFdagJf9cy8utEVkL9khXdcbx555TDDvPVKWBjC1M3tkHgt37A6hsubML50E0LfZU+TNVJldRH7LJ8goFC0juiQ+llc6wDtOMV45lqgibz5qVaEKpXA2CZQ0do9AIBi5E0Q1h34pHkXNJTE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TMGRsGvb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TMGRsGvb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 24FDEC4CECC; Wed, 27 Nov 2024 10:30:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732703449; bh=yoUldh/uZchEIwYIHV5nk8tHJLu9/aT+70+9evMH1PU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TMGRsGvb8RZNXqcTGn7DIxihj81lfuvyOTfiVf6Wlmyhq0BIfTtMIT9RV+fkjIB5U yPthu6bhlyWpJXvtnJ/qWinZQ7SyIjnEHmMrr3U+vdnfx6YvG6FmXQyojAGtL1+Vev OsfC3sfPRREmgPCXhGjqR1JFM4pQlCOkP7XjRIo1aAluGAJn/ZEwJAxPCYoYDo2YpI kZOgot/uNFmxu1GHUa1mHLUHkXTUp9tjpXTQRx6CCOxHQqmJhiI/DeVsmOtKNzqnsy KcJiY5d/TeuhjxND4XEVztFDnM8WNi5pPC0GhNm+BtH+dJZPbAyysBwm2rTUoEsG7j Sv1JZOyJVIyhw== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v5 6/6] PCI: endpoint: Verify that requested BAR size is a power of two Date: Wed, 27 Nov 2024 11:30:22 +0100 Message-ID: <20241127103016.3481128-14-cassel@kernel.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241127103016.3481128-8-cassel@kernel.org> References: <20241127103016.3481128-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1205; i=cassel@kernel.org; h=from:subject; bh=yoUldh/uZchEIwYIHV5nk8tHJLu9/aT+70+9evMH1PU=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNLdvuwL9V4w63ap//ytyo6T/aPtzrF9usD0e27O+Z3PA /nqwt5u6ihlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBEWkUYGe49mVCx+fTV+Wou itViLLytoQlKrxTmBWy7ON/DfXqkvC8jw+R23cPnVSc/yH48bbrgg0Jzi7071Fh6He39tuatNHT UYAEA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA When allocating a BAR using pci_epf_alloc_space(), there are checks that round up the size to a power of two. However, there is no check in pci_epc_set_bar() which verifies that the requested BAR size is a power of two. Add a power of two check in pci_epc_set_bar(), so that we don't need to add such a check in each and every PCI endpoint controller driver. Signed-off-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index c69c133701c9..6062677e9ffe 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -622,6 +622,9 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; + if (!is_power_of_2(epf_bar->size)) + return -EINVAL; + if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || (flags & PCI_BASE_ADDRESS_SPACE_IO && flags & PCI_BASE_ADDRESS_IO_MASK) ||