From patchwork Thu Nov 28 02:10:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13887645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53D14D6D254 for ; Thu, 28 Nov 2024 02:12:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzK-0005kU-Bu; Wed, 27 Nov 2024 21:10:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzG-0005jA-PU for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzB-0006v8-W7 for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxieAR0UdnFFRKAA--.13853S3; Thu, 28 Nov 2024 10:10:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S3; Thu, 28 Nov 2024 10:10:24 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 1/5] hw/intc/loongson_ipi: Add more output parameter for cpu_by_arch_id Date: Thu, 28 Nov 2024 10:10:20 +0800 Message-Id: <20241128021024.662057-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add logic cpu index output parameter for function cpu_by_arch_id, CPUState::cpu_index is logic cpu slot index for possible_cpus. However it is logic cpu index with LoongsonIPICommonState::IPICore, here hide access for CPUState::cpu_index directly, it comes from function cpu_by_arch_id(). Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 19 +++++++++++++++---- hw/intc/loongson_ipi.c | 23 ++++++++++++++++++++++- hw/intc/loongson_ipi_common.c | 21 ++++++++++++--------- include/hw/intc/loongson_ipi_common.h | 3 ++- 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 2ae1a42c46..c5ecd68952 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -36,17 +36,28 @@ static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) return found_cpu; } -static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState **pcs) { MachineState *machine = MACHINE(qdev_get_machine()); CPUArchId *archid; + CPUState *cs; archid = find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); + if (archid && archid->cpu) { + cs = archid->cpu; + if (index) { + *index = cs->cpu_index; + } + + if (pcs) { + *pcs = cs; + } + + return MEMTX_OK; } - return NULL; + return MEMTX_ERROR; } static void loongarch_ipi_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 4e08f03510..885916e9cd 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -19,6 +19,27 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } +static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState **pcs) +{ + CPUState *cs; + + cs = cpu_by_arch_id(arch_id); + if (cs == NULL) { + return MEMTX_ERROR; + } + + if (index) { + *index = cs->cpu_index; + } + + if (pcs) { + *pcs = cs; + } + + return MEMTX_OK; +} + static const MemoryRegionOps loongson_ipi_core_ops = { .read_with_attrs = loongson_ipi_core_readl, .write_with_attrs = loongson_ipi_core_writel, @@ -74,7 +95,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, void *data) device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); licc->get_iocsr_as = get_iocsr_as; - licc->cpu_by_arch_id = cpu_by_arch_id; + licc->cpu_by_arch_id = loongson_cpu_by_arch_id; } static const TypeInfo loongson_ipi_types[] = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index a6ce0181f6..2f574947ef 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -105,16 +105,17 @@ static MemTxResult mail_send(LoongsonIPICommonState *ipi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { + ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret != MEMTX_OK) { return MEMTX_DECODE_ERROR; } /* override requester_id */ addr = SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id = cs->cpu_index; + attrs.requester_id = cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } @@ -125,16 +126,17 @@ static MemTxResult any_send(LoongsonIPICommonState *ipi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; cpuid = extract32(val, 16, 10); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL) { + ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret != MEMTX_OK) { return MEMTX_DECODE_ERROR; } /* override requester_id */ addr = val & 0xffff; - attrs.requester_id = cs->cpu_index; + attrs.requester_id = cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } @@ -148,6 +150,7 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, uint32_t cpuid; uint8_t vector; CPUState *cs; + int cpu, ret; addr &= 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); @@ -178,11 +181,11 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, cpuid = extract32(val, 16, 10); /* IPI status vector */ vector = extract8(val, 0, 5); - cs = licc->cpu_by_arch_id(cpuid); - if (cs == NULL || cs->cpu_index >= ipi->num_cpu) { + ret = licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret != MEMTX_OK || cpu >= ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF, BIT(vector), 4, attrs); break; default: diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongson_ipi_common.h index df9d9c5168..2f1646a5f9 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -44,7 +44,8 @@ struct LoongsonIPICommonClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; AddressSpace *(*get_iocsr_as)(CPUState *cpu); - CPUState *(*cpu_by_arch_id)(int64_t id); + int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, + int *index, CPUState **pcs); }; MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, From patchwork Thu Nov 28 02:10:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13887642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3D857D6D254 for ; Thu, 28 Nov 2024 02:11:44 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzI-0005jv-2X; Wed, 27 Nov 2024 21:10:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzE-0005iw-V4 for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:32 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzC-0006v7-0b for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:32 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxPOIR0UdnGFRKAA--.13898S3; Thu, 28 Nov 2024 10:10:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S4; Thu, 28 Nov 2024 10:10:25 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 2/5] hw/intc/loongarch_ipi: Add basic hotplug framework Date: Thu, 28 Nov 2024 10:10:21 +0800 Message-Id: <20241128021024.662057-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org LoongArch ipi can send interrupt to multiple CPUs, interrupt routing to CPU comes from destination physical cpu id. Here hotplug interface is added for IPI object, sot that logic cpu mapping from physical cpu id can be setup. Here only basic hotplug framework is added, it is stub function. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index c5ecd68952..7ea65bcef3 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -7,6 +7,7 @@ #include "qemu/osdep.h" #include "hw/boards.h" +#include "qemu/error-report.h" #include "hw/intc/loongarch_ipi.h" #include "target/loongarch/cpu.h" @@ -60,12 +61,39 @@ static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, return MEMTX_ERROR; } +static void loongarch_cpu_plug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + Object *obj = OBJECT(dev); + + if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { + warn_report("LoongArch IPI: Invalid %s device type", + object_get_typename(obj)); + return; + } +} + +static void loongarch_cpu_unplug(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + Object *obj = OBJECT(dev); + + if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { + warn_report("LoongArch IPI: Invalid %s device type", + object_get_typename(obj)); + return; + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); licc->get_iocsr_as = get_iocsr_as; licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; + hc->plug = loongarch_cpu_plug; + hc->unplug = loongarch_cpu_unplug; } static const TypeInfo loongarch_ipi_types[] = { @@ -73,6 +101,10 @@ static const TypeInfo loongarch_ipi_types[] = { .name = TYPE_LOONGARCH_IPI, .parent = TYPE_LOONGSON_IPI_COMMON, .class_init = loongarch_ipi_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { } + } } }; From patchwork Thu Nov 28 02:10:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13887643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD845D6D254 for ; Thu, 28 Nov 2024 02:11:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzI-0005k4-N3; Wed, 27 Nov 2024 21:10:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzG-0005jC-Pk for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzC-0006v9-6X for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxL60S0UdnHFRKAA--.40553S3; Thu, 28 Nov 2024 10:10:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S5; Thu, 28 Nov 2024 10:10:25 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/intc/loongarch_ipi: Add cpu map table from physical cpu id Date: Thu, 28 Nov 2024 10:10:22 +0800 Message-Id: <20241128021024.662057-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Bitmap table present_cpu_map is added, it is to allocate logical cpu when CPU object is created. Also present_cpu array is added to get logical cpu from physical cpu id. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 24 ++++++++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 6 ++++++ include/hw/loongarch/virt.h | 9 +++++++++ 3 files changed, 39 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 7ea65bcef3..9296006cf6 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "hw/boards.h" #include "qemu/error-report.h" +#include "qapi/error.h" #include "hw/intc/loongarch_ipi.h" #include "target/loongarch/cpu.h" @@ -85,11 +86,33 @@ static void loongarch_cpu_unplug(HotplugHandler *hotplug_dev, } } +static void loongarch_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongarchIPIState *lis = LOONGARCH_IPI(dev); + LoongarchIPIClass *lic = LOONGARCH_IPI_GET_CLASS(dev); + Error *local_err = NULL; + int i; + + lic->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (i = 0; i < MAX_PHY_ID; i++) { + lis->present_cpu[i] = INVALID_CPU; + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc = DEVICE_CLASS(klass); LoongsonIPICommonClass *licc = LOONGSON_IPI_COMMON_CLASS(klass); + LoongarchIPIClass *lic = LOONGARCH_IPI_CLASS(klass); HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); + device_class_set_parent_realize(dc, loongarch_ipi_realize, + &lic->parent_realize); licc->get_iocsr_as = get_iocsr_as; licc->cpu_by_arch_id = loongarch_cpu_by_arch_id; hc->plug = loongarch_cpu_plug; @@ -100,6 +123,7 @@ static const TypeInfo loongarch_ipi_types[] = { { .name = TYPE_LOONGARCH_IPI, .parent = TYPE_LOONGSON_IPI_COMMON, + .instance_size = sizeof(LoongarchIPIState), .class_init = loongarch_ipi_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h index 276b3040a3..1ef64af85c 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -10,16 +10,22 @@ #include "qom/object.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/loongarch/virt.h" +#define INVALID_CPU -1 #define TYPE_LOONGARCH_IPI "loongarch_ipi" OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) struct LoongarchIPIState { LoongsonIPICommonState parent_obj; + DECLARE_BITMAP(present_cpu_map, LOONGARCH_MAX_CPUS); + int present_cpu[MAX_PHY_ID]; + CPUState *cs[MAX_PHY_ID]; }; struct LoongarchIPIClass { LoongsonIPICommonClass parent_class; + DeviceRealize parent_realize; }; #endif diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 9ba47793ef..7754c85f0b 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -14,6 +14,15 @@ #include "hw/loongarch/boot.h" #define LOONGARCH_MAX_CPUS 256 +/* + * LoongArch Reference Manual Vol1, Chapter 7.4.12 CPU Identity + * For CPU architecture, bit0 .. bit8 is valid for CPU id, max cpuid is 512 + * However for IPI/Eiointc interrupt controller, max supported cpu id for + * irq routing is 256 + * + * Here max cpu id is 256 for virt machine + */ +#define MAX_PHY_ID 0x100 #define VIRT_FWCFG_BASE 0x1e020000UL #define VIRT_BIOS_BASE 0x1c000000UL From patchwork Thu Nov 28 02:10:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13887640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CACA3D6D254 for ; Thu, 28 Nov 2024 02:11:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzJ-0005kH-Eu; Wed, 27 Nov 2024 21:10:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzG-0005j8-Op for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzC-0006vE-0f for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:33 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxYa8S0UdnIVRKAA--.14883S3; Thu, 28 Nov 2024 10:10:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S6; Thu, 28 Nov 2024 10:10:26 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 4/5] hw/intc/loongarch_ipi: Implment cpu hotplug interface Date: Thu, 28 Nov 2024 10:10:23 +0800 Message-Id: <20241128021024.662057-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add logic cpu allocation and cpu mapping with cpu hotplug interface. When cpu is added, connect ipi gpio irq to CPU IRQ_IPI irq pin. Also use hotplug_handler_plug() to nofity ipi object when cold-plug is created. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 46 +++++++++++++++++++++++++++++++++++++++++ hw/loongarch/virt.c | 5 ++--- 2 files changed, 48 insertions(+), 3 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 9296006cf6..579c9c830b 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -65,25 +65,71 @@ static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, static void loongarch_cpu_plug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { + LoongarchIPIState *lis = LOONGARCH_IPI(hotplug_dev); Object *obj = OBJECT(dev); + LoongArchCPU *cpu; + int phy_id, index; if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { warn_report("LoongArch IPI: Invalid %s device type", object_get_typename(obj)); return; } + + cpu = LOONGARCH_CPU(dev); + phy_id = cpu->phy_id; + if ((phy_id >= MAX_PHY_ID) || (phy_id < 0)) { + warn_report("LoongArch IPI: Invalid phy id %d", phy_id); + return; + } + + if (lis->present_cpu[phy_id] >= 0) { + warn_report("LoongArch IPI: phy id %d is added already", phy_id); + return; + } + + index = find_first_zero_bit(lis->present_cpu_map, LOONGARCH_MAX_CPUS); + if (index == LOONGARCH_MAX_CPUS) { + error_setg(errp, "no free cpu slots available"); + return; + } + + /* connect ipi irq to cpu irq */ + set_bit(index, lis->present_cpu_map); + lis->present_cpu[phy_id] = index; + lis->cs[phy_id] = CPU(dev); + qdev_connect_gpio_out(DEVICE(lis), index, qdev_get_gpio_in(dev, IRQ_IPI)); } static void loongarch_cpu_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { + LoongarchIPIState *lis = LOONGARCH_IPI(hotplug_dev); Object *obj = OBJECT(dev); + LoongArchCPU *cpu; + int phy_id; if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) { warn_report("LoongArch IPI: Invalid %s device type", object_get_typename(obj)); return; } + + cpu = LOONGARCH_CPU(dev); + phy_id = cpu->phy_id; + if ((phy_id >= MAX_PHY_ID) || (phy_id < 0)) { + warn_report("LoongArch IPI: Invalid phy id %d", phy_id); + return; + } + + if (lis->present_cpu[phy_id] < 0) { + warn_report("LoongArch IPI: phy id %d is not added", phy_id); + return; + } + + clear_bit(lis->present_cpu[phy_id], lis->present_cpu_map); + lis->present_cpu[phy_id] = INVALID_CPU; + lis->cs[phy_id] = NULL; } static void loongarch_ipi_realize(DeviceState *dev, Error **errp) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 9a635d1d3d..8147897cc7 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -794,6 +794,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) CPUState *cpu_state; int cpu, pin, i, start, num; uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; + Error *local_err = NULL; /* * Extended IRQ model. @@ -859,9 +860,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lvms) lacpu = LOONGARCH_CPU(cpu_state); env = &(lacpu->env); env->address_space_iocsr = &lvms->as_iocsr; - - /* connect ipi irq to cpu irq */ - qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); + hotplug_handler_plug(HOTPLUG_HANDLER(ipi), cpudev, &local_err); env->ipistate = ipi; } From patchwork Thu Nov 28 02:10:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: bibo mao X-Patchwork-Id: 13887641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA653D6D253 for ; Thu, 28 Nov 2024 02:11:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzJ-0005kC-Ac; Wed, 27 Nov 2024 21:10:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzG-0005jB-PT for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzC-0006vI-Gx for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:33 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxQK8S0UdnJVRKAA--.55590S3; Thu, 28 Nov 2024 10:10:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S7; Thu, 28 Nov 2024 10:10:26 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 5/5] hw/intc/loongarch_ipi: Optimize function cpu_by_arch_id Date: Thu, 28 Nov 2024 10:10:24 +0800 Message-Id: <20241128021024.662057-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is cpu mapping from physical cpu id inside, cpu_by_arch_id can be optimized from cpu mapping table. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 47 ++++++++++------------------------------- 1 file changed, 11 insertions(+), 36 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 579c9c830b..7fd237bd14 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -17,49 +17,24 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return LOONGARCH_CPU(cpu)->env.address_space_iocsr; } -static int archid_cmp(const void *a, const void *b) -{ - CPUArchId *archid_a = (CPUArchId *)a; - CPUArchId *archid_b = (CPUArchId *)b; - - return archid_a->arch_id - archid_b->arch_id; -} - -static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) -{ - CPUArchId apic_id, *found_cpu; - - apic_id.arch_id = id; - found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, - ms->possible_cpus->len, - sizeof(*ms->possible_cpus->cpus), - archid_cmp); - - return found_cpu; -} - static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, int64_t arch_id, int *index, CPUState **pcs) { - MachineState *machine = MACHINE(qdev_get_machine()); - CPUArchId *archid; - CPUState *cs; - - archid = find_cpu_by_archid(machine, arch_id); - if (archid && archid->cpu) { - cs = archid->cpu; - if (index) { - *index = cs->cpu_index; - } + LoongarchIPIState *lis = LOONGARCH_IPI(lics); - if (pcs) { - *pcs = cs; - } + if ((arch_id >= MAX_PHY_ID) || (lis->cs[arch_id] == NULL)) { + return MEMTX_ERROR; + } + + if (index) { + *index = lis->present_cpu[arch_id]; + } - return MEMTX_OK; + if (pcs) { + *pcs = lis->cs[arch_id]; } - return MEMTX_ERROR; + return MEMTX_OK; } static void loongarch_cpu_plug(HotplugHandler *hotplug_dev,