From patchwork Fri Nov 29 06:50:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13888434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 98717D6D25B for ; Fri, 29 Nov 2024 06:50:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AE1910E26A; Fri, 29 Nov 2024 06:50:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="G8U0JNom"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9BDAD10E26A for ; Fri, 29 Nov 2024 06:50:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732863021; x=1764399021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nf8tAorTsdTHxzRpEK90h3CagUqwvx9Se/b4avykyi8=; b=G8U0JNomlGIHG2gc/MJT89NdJdx4xa+/0bF+lHndopV+OJdHBCAy/1jW 7vNIF+HkZNNAc/JqXzYAry3tlTULZwEUU4ia4nn8AJIlfwbBRh5vpiBRi DfiPAq75uKA+hI/YR5edA8/j4qvlfa1j6GO64OrQ3+wU1wO9DnOaqYyj3 LYpQ8CgyXh9GmMoX/p1OK8QAroAZojE9rxB+uLeXZ+pLTk/mGptPJmVTh AGeNBVeLHyl0i8IoqwPrbiiAzYbIc0f+iTViQdUm7xTbJX1lfPQ2Um7dz F4bT0GBAUZ38KFpo3x0ZgfqfErtk1HlUAK/h5m6ESEMZKRtAByaJWtpIu g==; X-CSE-ConnectionGUID: xRQhiUvWQFqSBwSLq+fugA== X-CSE-MsgGUID: A9mYxQMURiCo2HoLLEaclw== X-IronPort-AV: E=McAfee;i="6700,10204,11270"; a="44468020" X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="44468020" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2024 22:50:21 -0800 X-CSE-ConnectionGUID: i+BJFHLDScm0TbIsmmWAqQ== X-CSE-MsgGUID: uHjolGQcSuStvEqnOjJ4ZQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="92589181" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 28 Nov 2024 22:50:19 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 29 Nov 2024 08:50:17 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Sagar Ghuge , Nanley Chery , Xi Ruoyao Subject: [PATCH 1/4] drm/i915/fb: Relax clear color alignment to 64 bytes Date: Fri, 29 Nov 2024 08:50:11 +0200 Message-ID: <20241129065014.8363-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129065014.8363-1-ville.syrjala@linux.intel.com> References: <20241129065014.8363-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Mesa changed its clear color alignment from 4k to 64 bytes without informing the kernel side about the change. This is now likely to cause framebuffer creation to fail. The only thing we do with the clear color buffer in i915 is: 1. map a single page 2. read out bytes 16-23 from said page 3. unmap the page So the only requirement we really have is that those 8 bytes are all contained within one page. Thus we can deal with the Mesa regression by reducing the alignment requiment from 4k to the same 64 bytes in the kernel. We could even go as low as 32 bytes, but IIRC 64 bytes is the hardware requirement on the 3D engine side so matching that seems sensible. Cc: stable@vger.kernel.org Cc: Sagar Ghuge Cc: Nanley Chery Reported-by: Xi Ruoyao Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13057 Closes: https://lore.kernel.org/all/45a5bba8de009347262d86a4acb27169d9ae0d9f.camel@xry111.site/ Link: https://gitlab.freedesktop.org/mesa/mesa/-/commit/17f97a69c13832a6c1b0b3aad45b06f07d4b852f Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 6a7060889f40..223c4218c019 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1694,7 +1694,7 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * * arithmetic related to alignment and offset calculation. */ if (is_gen12_ccs_cc_plane(&fb->base, i)) { - if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE)) + if (IS_ALIGNED(fb->base.offsets[i], 64)) continue; else return -EINVAL; From patchwork Fri Nov 29 06:50:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13888435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECFDBD6D25C for ; Fri, 29 Nov 2024 06:50:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 94A5C10E499; Fri, 29 Nov 2024 06:50:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="CwST0lLo"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id E193810E499 for ; Fri, 29 Nov 2024 06:50:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732863025; x=1764399025; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JWJFAPXU53XGtet39m2t9mCk9sPweUk/DRDeSUkkBZk=; b=CwST0lLodNSIWO5z/ohtUlFRDt2R6nDo6W+QosBc+11SiLrMISm+p1Pk hiv9SVU8H/MNgWXezgq2dShBdEMgbGrHWT7zXHGjaOUzw2QkEGO9Vit55 XvlclqumDotYBpW8JIS0820YKKT/Go5Kc4dLqnrOa5j+CoKcOr5NR1P/7 gfxbivwWXbO8RePxSAFa94Hzv9lLtIZxJ/MjN4nntzNcx+826cyfhFZC7 sR4cUA7dFRe9vmWXByL2wWXOiCSK7RElqll90nHdL7HWOHIJpNOWdEXIr sydM5WWQyHRWY/nWEdxfcukC0MpwAp3VzrvjGaP2sINGaclEMkHSgqMra g==; X-CSE-ConnectionGUID: 9Qbmg+EhT/uv2uTPg3PxDQ== X-CSE-MsgGUID: DiqNdWYkQKS0Lc4zfy3adg== X-IronPort-AV: E=McAfee;i="6700,10204,11270"; a="44468031" X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="44468031" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2024 22:50:25 -0800 X-CSE-ConnectionGUID: zSPjyrGSS8eeAB4ugLjaTg== X-CSE-MsgGUID: SqjvL2pCQzyk5554MlMGaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="92589189" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 28 Nov 2024 22:50:23 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 29 Nov 2024 08:50:21 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: Sagar Ghuge , Nanley Chery , Xi Ruoyao Subject: [PATCH 2/4] drm/i915/fb: Add debug spew for misaligned CC plane Date: Fri, 29 Nov 2024 08:50:12 +0200 Message-ID: <20241129065014.8363-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129065014.8363-1-ville.syrjala@linux.intel.com> References: <20241129065014.8363-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We're currently failing to provide any debug output when the user passes in a misaligned offset for the clear color plane. Add some debugs prints to make debugging actually possible. Cc: Sagar Ghuge Cc: Nanley Chery Cc: Xi Ruoyao Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 223c4218c019..e478d412785e 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1694,10 +1694,14 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * * arithmetic related to alignment and offset calculation. */ if (is_gen12_ccs_cc_plane(&fb->base, i)) { - if (IS_ALIGNED(fb->base.offsets[i], 64)) - continue; - else + if (!IS_ALIGNED(fb->base.offsets[i], 64)) { + drm_dbg_kms(&i915->drm, + "fb misaligned clear color plane %d offset (0x%x)\n", + i, fb->base.offsets[i]); return -EINVAL; + } + + continue; } intel_fb_plane_dims(fb, i, &width, &height); From patchwork Fri Nov 29 06:50:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13888436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECCADD6D25C for ; Fri, 29 Nov 2024 06:50:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C64B10EDAD; Fri, 29 Nov 2024 06:50:30 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="naeZGWrl"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4F0D210EDAD for ; Fri, 29 Nov 2024 06:50:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732863029; x=1764399029; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LbTQjlh4pQ0UVNwHqzoBMm2loS8AMIHp7l1RmJVa5fA=; b=naeZGWrlgvvRL6LMTWWBpbMH+NYdpwNljzoAL5FhdJmxDOLl6Ez4up8P kk2hZQFZzYy6JdW4yVMjviAr/E8SVcNWuJliRVmnSAYyFr772g4tzQ793 M9kNXqkbJGNGULao6VRp9H84NiCJFjnVKYUJ/MrVhtbi1P6cAm5xJytjm BIgV1751sP3+S7prWJf6fp2V8tMzUjOxlGgWP0+H2My6jic3JvlT4Kxwe jYOjeZWc2ZC11ZeiNe2N1QDDW66Kre0bilf6ItiQsD5feyPOVcJwdUbMm xp60/TyTAFj7UYPmgZbLQBTrDGmHUR2igKoejeNpiYx7AZy2jHvaBm6Sq w==; X-CSE-ConnectionGUID: popSwZv4Rx2+ajwHmrFBvA== X-CSE-MsgGUID: C5L7CTB2T+mpvmhSb9iphA== X-IronPort-AV: E=McAfee;i="6700,10204,11270"; a="44468039" X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="44468039" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2024 22:50:29 -0800 X-CSE-ConnectionGUID: 6ap9CiN0SnGn1a9w5MhXCg== X-CSE-MsgGUID: gPNveTl+TayXMuvrNfF/Qw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="92589202" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 28 Nov 2024 22:50:27 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 29 Nov 2024 08:50:25 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: Sagar Ghuge , Nanley Chery , Xi Ruoyao Subject: [PATCH 3/4] drm/i915/fb: Check that the clear color fits within the BO Date: Fri, 29 Nov 2024 08:50:13 +0200 Message-ID: <20241129065014.8363-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129065014.8363-1-ville.syrjala@linux.intel.com> References: <20241129065014.8363-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Make sure the user supplied offset[] for the clear color plane fits within the actual BO. Note that we use tile units to track the size here. All the other color/aux planes are already being checked correctly. Cc: Sagar Ghuge Cc: Nanley Chery Cc: Xi Ruoyao Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index e478d412785e..9f7f1b9f3275 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1694,6 +1694,8 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * * arithmetic related to alignment and offset calculation. */ if (is_gen12_ccs_cc_plane(&fb->base, i)) { + unsigned int end; + if (!IS_ALIGNED(fb->base.offsets[i], 64)) { drm_dbg_kms(&i915->drm, "fb misaligned clear color plane %d offset (0x%x)\n", @@ -1701,6 +1703,14 @@ int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer * return -EINVAL; } + if (check_add_overflow(fb->base.offsets[i], 64, &end)) { + drm_dbg_kms(&i915->drm, + "fb bad clear color plane %d offset (0x%x)\n", + i, fb->base.offsets[i]); + return -EINVAL; + } + + max_size = max(max_size, DIV_ROUND_UP(end, tile_size)); continue; } From patchwork Fri Nov 29 06:50:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 13888437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 347C5D6D25B for ; Fri, 29 Nov 2024 06:50:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D86A010EDAE; Fri, 29 Nov 2024 06:50:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="NIkqvX2x"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id CCF4C10EDAE for ; Fri, 29 Nov 2024 06:50:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1732863032; x=1764399032; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9XzREiPdVKCbGFj2yQy4hn3XUcNXWCClhjURNW9UuLE=; b=NIkqvX2xeQwLga06fUAxbyj2uynT+fUFMUsA21XPRZeBPcbRcj+3N4Ki C3L67Vet6ZHQv6lnfrs41QLzxJd5oKSmt7JFv5V+S/mXDj+HGcLySZNKh HymQVZf6JZUKBb6a7Tap8eqizKB3fXnNxP31evqjJNuFDJg4vFqUrkbr6 9YZLUdFwRjmFoOFu+3XBnkPUAD2byy2NxEsoKnVNdnP3lJ1XZCg2V2pEX IAXdB7pgcj7DG4g42D6VZZvySMMUaaD9G46s+6QqyUErKlBGRZDYKLh58 IYIlCkrVF9LyB9IMfK/kkuYK1IpSMJ6SIPdz681bx3NsxZ+wlKWzOgH7W Q==; X-CSE-ConnectionGUID: p5zCYBSRQi+idw334XQQMA== X-CSE-MsgGUID: JOztF+baQ46B2PYxt/+2NA== X-IronPort-AV: E=McAfee;i="6700,10204,11270"; a="44468047" X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="44468047" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Nov 2024 22:50:32 -0800 X-CSE-ConnectionGUID: NZDwcdarRWeoe421o0BohQ== X-CSE-MsgGUID: gw6Bp+glSbydnu3WGG4row== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,194,1728975600"; d="scan'208";a="92589217" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 28 Nov 2024 22:50:30 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 29 Nov 2024 08:50:29 +0200 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: Sagar Ghuge , Nanley Chery , Xi Ruoyao Subject: [PATCH 4/4] drm/uapi/fourcc: Document the Intel clear color alignment better Date: Fri, 29 Nov 2024 08:50:14 +0200 Message-ID: <20241129065014.8363-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241129065014.8363-1-ville.syrjala@linux.intel.com> References: <20241129065014.8363-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Document the fact that the Intel clear color offset and pitch must be 64 byte aligned. Cc: Sagar Ghuge Cc: Nanley Chery Cc: Xi Ruoyao Link: https://gitlab.freedesktop.org/mesa/mesa/-/commit/17f97a69c13832a6c1b0b3aad45b06f07d4b852f Signed-off-by: Ville Syrjälä --- include/uapi/drm/drm_fourcc.h | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 70f3b00b0681..8234db1f484a 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -598,7 +598,7 @@ extern "C" { * compression. * * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear - * and at index 1. The clear color is stored at index 2, and the pitch should + * and at index 1. The clear color is stored at index 2, and the offset and pitch must * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits * represents Raw Clear Color Red, Green, Blue and Alpha color each represented * by 32 bits. The raw clear color is consumed by the 3d engine and generates @@ -652,7 +652,7 @@ extern "C" { * outside of the GEM object in a reserved memory area dedicated for the * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The * main surface pitch is required to be a multiple of four Tile 4 widths. The - * clear color is stored at plane index 1 and the pitch should be 64 bytes + * clear color is stored at plane index 1, and the offset and pitch must be 64 bytes * aligned. The format of the 256 bits of clear color data matches the one used * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description * for details. @@ -688,17 +688,18 @@ extern "C" { * compression. * * The main surface is tile4 and is at plane index 0 whereas CCS is linear - * and at index 1. The clear color is stored at index 2, and the pitch should - * be ignored. The clear color structure is 256 bits. The first 128 bits - * represents Raw Clear Color Red, Green, Blue and Alpha color each represented - * by 32 bits. The raw clear color is consumed by the 3d engine and generates - * the converted clear color of size 64 bits. The first 32 bits store the Lower - * Converted Clear Color value and the next 32 bits store the Higher Converted - * Clear Color value when applicable. The Converted Clear Color values are - * consumed by the DE. The last 64 bits are used to store Color Discard Enable - * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line - * corresponds to an area of 4x1 tiles in the main surface. The main surface - * pitch is required to be a multiple of 4 tile widths. + * and at index 1. The clear color is stored at index 2, and the offset and + * pitch must be 64 bytes aligned. The clear color structure is 256 bits. + * The first 128 bits represents Raw Clear Color Red, Green, Blue and Alpha + * color each represented by 32 bits. The raw clear color is consumed by the + * 3d engine and generates the converted clear color of size 64 bits. The + * first 32 bits store the Lower Converted Clear Color value and the next 32 + * bits store the Higher Converted Clear Color value when applicable. The + * Converted Clear Color values are consumed by the DE. The last 64 bits are + * used to store Color Discard Enable and Depth Clear Value Valid which are + * ignored by the DE. A CCS cache line corresponds to an area of 4x1 tiles in + * the main surface. The main surface pitch is required to be a multiple of + * 4 tile widths. */ #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)