From patchwork Fri Nov 29 23:20:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13888992 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6ED1538FAD; Fri, 29 Nov 2024 23:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922495; cv=none; b=p6MhA8JU43wZE8fg5QjHGfPB9RQDRv2YKF+Vk6nw4V+MqEGTRCosH5AmIviaQ3JLnNt5geYDV3RCV+cIPCvFqHPOnMOeQxwjDkGf7VEDKkIwoHUkxY+M3A2gVbbhbIlm0Jp55PO6IF0KtQxrcRP6oF1/8fo7SRgJ9cJq37p7BVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922495; c=relaxed/simple; bh=hl2S2LZwn2smx9ARAoEF8vIrYGRpQBw8WQAXlixKIJw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ABouaVkgOLIXameVWoNL3I5URfq6vvxKejIec7trhY+1cszSoHr/MSOle8HXiLv8rIGC0iZi9s8BmM5B5Bx9beMnY9m88H48zfwqVqVuBej04un6xttC7O6FUMduGL8ZspTCbo+MKpNz+z6gGkjWtAYrJxo1NwDZwfd76zBV9vw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tmpixqma; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tmpixqma" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CDB9C4CECF; Fri, 29 Nov 2024 23:21:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732922494; bh=hl2S2LZwn2smx9ARAoEF8vIrYGRpQBw8WQAXlixKIJw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tmpixqmaOETTs+0vhnV4hlMMgX3B8z5zvkAy+PrmhlC2Je2XIGNJG1WSZgBMaigd8 mVvexJAPbuaeVBHtDMXQk/bmMHjHUfptc394fRCdG11EKyWsVAUFMw8GOVRtKzSDoS elBn0x5UIK0IgbuPylKK5tKmfvbSGsWiL/njD3Jj7M/HmmGGFSbwSofKs6jvXA9eaQ pvznIbPl5N9ju6kSRW671B+A4LKbwR8wsZoCZ/yroX0ra8GmrmWrToAxt9q4HuRgFL MJCStRSqvDa3xW/yKI4YUhAVDbEHFCEh8ufHlQMfgrhNwFJrjbE58+dz1xh7fugVeQ iiUNQMsmCWANw== From: Lorenzo Bianconi Date: Sat, 30 Nov 2024 00:20:10 +0100 Subject: [PATCH v5 1/6] PCI: mediatek-gen3: Add missing reset_control_deassert() for mac_rst in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-pcie-en7581-fixes-v5-1-dbffe41566b3@kernel.org> References: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> In-Reply-To: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Even if this is not a real issue since Airoha EN7581 SoC does not require the mac reset line, add missing reset_control_deassert() for mac reset line in mtk_pcie_en7581_power_up() callback. Reviewed-by: Manivannan Sadhasivam Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 64ef8ff71b0357b9bf9ad8484095b7aa60c22271..4d1c797a32c236faf79428eb8a83708e9c4f21d8 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -942,6 +942,9 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* MAC power on and enable transaction layer clocks */ + reset_control_deassert(pcie->mac_reset); + pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -976,6 +979,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) err_clk_prepare: pm_runtime_put_sync(dev); pm_runtime_disable(dev); + reset_control_assert(pcie->mac_reset); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); err_phy_deassert: phy_power_off(pcie->phy); From patchwork Fri Nov 29 23:20:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13888993 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B46338FAD; Fri, 29 Nov 2024 23:21:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922498; cv=none; b=utLT8bRVVf6+M+bD/X/+VxZp/Abkdz/0S6O5Ma4jrmTG5IN6PbFA3xH4wqzq2Vg6sJXL4Vo3/NjbE/L/Et/uMS18TWu4HxD9Tcsy4nhwh7XU+J48EGOZPLrO4qMZQyDdLLt66aah1wvEdeykl8xjB04ETmPvjvTBBEl38FYVVc0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922498; c=relaxed/simple; bh=2VEtGqjec9nicO3CSib69XF9LVTOgYFa/s85m9iDYH0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZbMx32IMQK07sN4cXw2irHhZqFWpFX2cXnp3eTAHx0ILVg+az0RJodVal+SfHop9TFmmM9+QKVkX3qmUuD3LYmMjZpY7unwWGSru5F824vHZ8yJ0YQ49S709CyR3XspjmorM6XatF+mxzVhwgR5THp5HuZtBzoL4U6DFCLxBUHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=OM7K39CT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="OM7K39CT" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26242C4CECF; Fri, 29 Nov 2024 23:21:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732922497; bh=2VEtGqjec9nicO3CSib69XF9LVTOgYFa/s85m9iDYH0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=OM7K39CTf0ik0jHUf8OSiB8ua/pwbgTKD3e952FdPIkdEoziqALoLp7mL9nImzgMI 7WEq+TFdvvRf/Ev6l+gumRm1vMmnnlMHbVasnBpKVWQGVf1HiPUTyxNADevqo7vK03 /wQJxmaRyTLFute/GwvfgQ4Fo+aEjWrjU3EZs9mrLeeMwPOBRwBo3AjuYsYroj00i8 rND9z9vsm9v9CoVZ3ct/UlAlxipUBoWr0bOtq7W8HO+8/6JUawIGZUT1oWz+oeJNN2 dNeAw5Z404X1QtIaxDazD6P4GBosybPFpRlAwa3UvisQtLQLDsgcjcjepPk+rIPojD ZH+kBLlKH6FJA== From: Lorenzo Bianconi Date: Sat, 30 Nov 2024 00:20:11 +0100 Subject: [PATCH v5 2/6] PCI: mediatek-gen3: rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-pcie-en7581-fixes-v5-2-dbffe41566b3@kernel.org> References: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> In-Reply-To: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Replace clk_bulk_prepare() and clk_bulk_enable() with clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 4d1c797a32c236faf79428eb8a83708e9c4f21d8..3cfcb45d31508142d28d338ff213f70de9b4e608 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -948,12 +948,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - err = clk_bulk_prepare(pcie->num_clks, pcie->clks); - if (err) { - dev_err(dev, "failed to prepare clock\n"); - goto err_clk_prepare; - } - val = FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | @@ -966,17 +960,15 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err = clk_bulk_enable(pcie->num_clks, pcie->clks); + err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); - goto err_clk_enable; + goto err_clk_prepare_enable; } return 0; -err_clk_enable: - clk_bulk_unprepare(pcie->num_clks, pcie->clks); -err_clk_prepare: +err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); reset_control_assert(pcie->mac_reset); From patchwork Fri Nov 29 23:20:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13888994 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C8FD38FAD; Fri, 29 Nov 2024 23:21:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922500; cv=none; b=e1ZV5qFwMtWyoi/W+wuHspKlx4sfisjBEOaoFhsqHc5TX7rOUGiV5aMJik7jAodKnGljy1BZGUi+n08yZTB+ncybmksMgcNuczPMa4OQTQMTXZwKYWOkeLDnWY97wD+dn6MSL+5IyHw3puqreZKLRN9rOz7azhmViRgDzi9gwMw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922500; c=relaxed/simple; bh=ugku9pso3x81u0glSHvCY10Yvp4iU8R62ycqNYCHwBQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OqJ6zklHXtgg/rk3NRRzdDmjjm7unsika03N37FgNDaoYorLVDISUwT803n8dbuowFHoZpG7k5YZ3Dt2d+z0jsxKxFpxVDeyItfBVjqf0UzJMS0sNwgRL5eqMBV0TukjQERjQm9TxpnwluHeOZfif5MyKL9LUFFQHAktpqALoBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V1b5l6Nm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V1b5l6Nm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 29233C4CECF; Fri, 29 Nov 2024 23:21:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732922500; bh=ugku9pso3x81u0glSHvCY10Yvp4iU8R62ycqNYCHwBQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=V1b5l6Nmc075l4sr3Ys4TGuhI/3wI2OjE9pxwEjjZUcmwm59Zf1FgZLqX3bODkdhk QECDC+oE0ZxU67esPyIQH9Soa0TZnakJTTLOviybcBVL0+hHCIYn+VgTv/IYczOETj WQiFvRnsOsBzf+FktVBkuf7GKbq8Mh1ceEtqBud+4vCp7vfWjUrCgnuXSH9LjI+2rl e5fMMgnCNUkHDS4ZG/f8x7EPupqW1OiSzXTkYSwLCRJFbS2xvUWiHbpQbwJihsLrMl u4IRdzWqEGGnwEfoulS5dtutxsrSSuhtPxUkx1Fh6vAQL6PqN+gQbcmr+PTf+kfrcq 5NyT+J7B33zsw== From: Lorenzo Bianconi Date: Sat, 30 Nov 2024 00:20:12 +0100 Subject: [PATCH v5 3/6] PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-pcie-en7581-fixes-v5-3-dbffe41566b3@kernel.org> References: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> In-Reply-To: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 In order to make the code more readable, the reset_control_bulk_assert() for PHY reset lines is moved to make it pair with reset_control_bulk_deassert() in mtk_pcie_power_up() and mtk_pcie_en7581_power_up(). The same change is done for reset_control_assert() used to assert MAC reset line. Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 3cfcb45d31508142d28d338ff213f70de9b4e608..6c5e1fb16d17de0325d66277e0508b781fe45112 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -125,6 +125,8 @@ #define MAX_NUM_PHY_RESETS 3 +#define PCIE_MTK_RESET_TIME_US 10 + /* Time in ms needed to complete PCIe reset on EN7581 SoC */ #define PCIE_EN7581_RESET_TIME_MS 100 @@ -913,9 +915,14 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) u32 val; /* - * Wait for the time needed to complete the bulk assert in - * mtk_pcie_setup for EN7581 SoC. + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + + /* Wait for the time needed to complete the reset lines assert. */ mdelay(PCIE_EN7581_RESET_TIME_MS); err = phy_init(pcie->phy); @@ -986,6 +993,15 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie) struct device *dev = pcie->dev; int err; + /* + * The controller may have been left out of reset by the bootloader + * so make sure that we get a clean start by asserting resets here. + */ + reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, + pcie->phy_resets); + reset_control_assert(pcie->mac_reset); + usleep_range(PCIE_MTK_RESET_TIME_US, 2 * PCIE_MTK_RESET_TIME_US); + /* PHY power on and enable pipe clock */ err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); if (err) { @@ -1070,14 +1086,6 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie) * counter since the bulk is shared. */ reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - /* - * The controller may have been left out of reset by the bootloader - * so make sure that we get a clean start by asserting resets here. - */ - reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); - - reset_control_assert(pcie->mac_reset); - usleep_range(10, 20); /* Don't touch the hardware registers before power up */ err = pcie->soc->power_up(pcie); From patchwork Fri Nov 29 23:20:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13888995 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F0C138FAD; Fri, 29 Nov 2024 23:21:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922503; cv=none; b=KE6k9W48qPhAfmUXXLyEQh3gnbTL7ZdRmX20N0nKto4Kdo485St+b3TFdcaNeGknF7gGib0ccypBKbyu+vxzfstQgG5D14kEE59Lsdfq07MWEKaWB3Kf+7ImHp5NvFhZp7PIe3BlqtrmITnDkVTUdLc7irUuRnxbgZ5YK+Z2kHA= ARC-Message-Signature: i=1; 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b=qthJv+iaisz53lJt0zi8tV23TGU2AnESm16mC17EqGgCI/CFirTTflXZLQ0SK/PdB e/Hm/9btNaYNpVVZQZuhUCOro4bN23tGXJvO8evJp4uHj24+BlagIGEn348dSk7WNn EPsMv6K4JdNsFRbTsWchN8BaKUIQzBq++VQUMd0DdUNzxQt5tRB/lVcadW2+BDd2AQ YP/qq+LJXd2pyq6N1w+Za8mFqgen3oBoOzkic1hCSKtxI3r304vcJvVIfGGhMq4tVW MvT4wjqcya4YrF89rX9WFTRBLjn9KG9rzW2L425iTsq4gwT601Y1uvaPAkSIGtbbLp jpHAj/F1Nh4WQ== From: Lorenzo Bianconi Date: Sat, 30 Nov 2024 00:20:13 +0100 Subject: [PATCH v5 4/6] PCI: mediatek-gen3: Add comment about initialization order in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-pcie-en7581-fixes-v5-4-dbffe41566b3@kernel.org> References: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> In-Reply-To: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike the other MediaTek Gen3 controllers, the Airoha EN7581 requires PHY initialization and power-on before PHY reset deassert. Reviewed-by: Manivannan Sadhasivam Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 6c5e1fb16d17de0325d66277e0508b781fe45112..01e8fde96080fa55f6c23c7d1baab6e22c49fcff 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -925,6 +925,10 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) /* Wait for the time needed to complete the reset lines assert. */ mdelay(PCIE_EN7581_RESET_TIME_MS); + /* + * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 + * requires PHY initialization and power-on before PHY reset deassert. + */ err = phy_init(pcie->phy); if (err) { dev_err(dev, "failed to initialize PHY\n"); From patchwork Fri Nov 29 23:20:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13888996 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F94C1A08CA; Fri, 29 Nov 2024 23:21:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922506; cv=none; b=nslgNlEWEsf5W/a7IfeEn/cH32ee2MyCVbW21Zwf0cx+/r8UH7V7+iFq5hnZ1YeR+MZ9FPLpo53Ss+9YUiHWVjo836+ADILpFWrsXWS9oA8ZU3+EJz7MXx20C+HbtBeEoklWU/2+KzBjs+8Y/hHbKimhzGMzo8k2AcTSzuNkYaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922506; c=relaxed/simple; bh=RF3q5O23wBAonOVltARg7fJQ3V5muUeYMukIBjPft+0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mvd7Yk47SWiUXbcR+aQQLFiZzY9iz4D1YFdjnPTZkMqqEYJSy50K2fR87UPEAVwx+fS+eYeqSzwges4B+6ai01AKbuKs4SD5qLjJT73WVyc/9j1S0CSWawz2HHY7L03x7ElARrHEaJaJTLkS6hHh8x2WO0uR9ju2gjG9a/XcnBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kY4Q+u5M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kY4Q+u5M" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 763F8C4CECF; Fri, 29 Nov 2024 23:21:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732922506; bh=RF3q5O23wBAonOVltARg7fJQ3V5muUeYMukIBjPft+0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kY4Q+u5MYbYurISr6lmZRf/rHl7NOIa1OCmedWiWjAZvUw/+1U8fqT5DnYLTfhU3m VsasxitWqdDAZNyvSDc2SL3c9np7j/lb/uZlmWoJ8Znibwpx7oRH/Ps18Ts7KI+aDg Ee4DRCBw1VjT4uXl3DKcsJTuhk1FDo+BSvJeze9Qk6Oa4azcgw062GygOwqTxBD8sK 2b56+H1bYmcFLuNmhQgPcoBEHZdfPBsd6wgpAIgN9iOCP2domJyndDuHESc7MZG//g fc3itkw/Pa2JpEfelXQ2d4DSSykEm2Ds28H+Frls/XauhqA+1nREDVfw7gS0oWMzOL OjpV5ev1h9NeA== From: Lorenzo Bianconi Date: Sat, 30 Nov 2024 00:20:14 +0100 Subject: [PATCH v5 5/6] PCI: mediatek-gen3: Add reset delay in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-pcie-en7581-fixes-v5-5-dbffe41566b3@kernel.org> References: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> In-Reply-To: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal causing occasional PCIe link down issues. In order to overcome the problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and REG_RESET_CONTROL (0x834) registers available in the clock module running clk_bulk_prepare_enable in mtk_pcie_en7581_power_up(). In order to make the code more readable, move the wait for the time needed to complete the PCIe reset from en7581_pci_enable() to mtk_pcie_en7581_power_up(). Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value (100ms) since it has no impact on the driver behavior. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Stephen Boyd Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/clk/clk-en7523.c | 1 - drivers/pci/controller/pcie-mediatek-gen3.c | 7 +++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 22fbea61c3dcc05e63f8fa37e203c62b2a6fe79e..bf9d9594bef8a54316e28e56a1642ecb0562377a 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -393,7 +393,6 @@ static int en7581_pci_enable(struct clk_hw *hw) REG_PCI_CONTROL_PERSTOUT; val = readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); - msleep(250); return 0; } diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index 01e8fde96080fa55f6c23c7d1baab6e22c49fcff..da01e741ff290464d28e172879520dbe0670cc41 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -977,6 +977,13 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) goto err_clk_prepare_enable; } + /* + * Airoha EN7581 performs PCIe reset via clk callabacks since it has a + * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to + * complete the PCIe reset. + */ + msleep(PCIE_T_PVPERL_MS); + return 0; err_clk_prepare_enable: From patchwork Fri Nov 29 23:20:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 13888997 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8951165F1D; Fri, 29 Nov 2024 23:21:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922508; cv=none; b=QEwpNn4JbUqw95PSgLUvV/pYaMhw/4vht8DpBzjS8DTbjEghhHUmfJq3txsXeXvfDAMEH65/6brrHaKaVkMQvCWXwJ6OYmESbKRgbaBnMOAUl7KTXkY8wvcDtfRqOo7esQOgXtlLzAsghzTDfYbCHzirA5FiJkPCg2v1kD/hgXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732922508; c=relaxed/simple; bh=zff8+jE90CeXzoQGgZrfYREKOMGTptEOnRjdJiM7uwE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Km4zThomhbg2GcBuAZdShMns+C3iMO3503hRQgeQDaaSMWH75xy9phazJGHPTGCC/L2k27wOZkjXUNsiwQ7b/TpGdUdUHmc2sUq7HFSxbhLlzgBxL/+lVgh764vLoReH2EOuWeDePq+lcDzRZtX17NOfJsoaYB/3o9C+uKEoGgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i2aAenO7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i2aAenO7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55F83C4CECF; Fri, 29 Nov 2024 23:21:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732922508; bh=zff8+jE90CeXzoQGgZrfYREKOMGTptEOnRjdJiM7uwE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=i2aAenO7PjaXMxVmbrH8v5iL+Nr/zSj3Oo36EWAa8m7R16YaCWQvT3MOk7Lvymtu7 3wDMJdGIp+rUzennJFLtqKDUyCwGFudSdTeAL+Rs9JrKAOJYUk5yktGfLuW27IsnoS wl+0vfaTGPNl6/6RNP6KLwUcoI4O7omVzIhRi3gboarCCnib2BMtmKLoRAQ1IN41IH 19cgJqTXRjZndL2iTULFhHJ/EQNgrJ7YBh+ve+j/UUrHWgSIx1c946CQXNdrDA4eCa lq0R/tkUxetZCSRaHoOlxwN2Z+OccQiLk9Bm6+Ad5ix8tzBerWOtYmIjmUFK/W2bfV FqEUXsCoZizkQ== From: Lorenzo Bianconi Date: Sat, 30 Nov 2024 00:20:15 +0100 Subject: [PATCH v5 6/6] PCI: mediatek-gen3: rely on msleep() in mtk_pcie_en7581_power_up() Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-pcie-en7581-fixes-v5-6-dbffe41566b3@kernel.org> References: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> In-Reply-To: <20241130-pcie-en7581-fixes-v5-0-dbffe41566b3@kernel.org> To: Ryder Lee , Jianjun Wang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Michael Turquette , Stephen Boyd Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, Lorenzo Bianconi X-Mailer: b4 0.14.2 Since mtk_pcie_en7581_power_up() runs in non-atomic context, rely on msleep() routine instead of mdelay(). Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Bianconi --- drivers/pci/controller/pcie-mediatek-gen3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c index da01e741ff290464d28e172879520dbe0670cc41..0b4367fe2c3387ac55f4f44d8c2aace4df840a37 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -923,7 +923,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) reset_control_assert(pcie->mac_reset); /* Wait for the time needed to complete the reset lines assert. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 @@ -951,7 +951,7 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) * Wait for the time needed to complete the bulk de-assert above. * This time is specific for EN7581 SoC. */ - mdelay(PCIE_EN7581_RESET_TIME_MS); + msleep(PCIE_EN7581_RESET_TIME_MS); /* MAC power on and enable transaction layer clocks */ reset_control_deassert(pcie->mac_reset);