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a=openpgp-sha256; l=922; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=RRNUGJhydbP97WLehq1T9w+y0AXTLiZzoSCdrYYWsLQ=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3y8sGkg4cbFhbievKqVk4IBQYf7oTigPWWd GC3yaD7idCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8gAKCRCLPIo+Aiko 1cYnB/4nCxLTczH3plii1y5u6b2Agwm/84QIJwC2w1M5TaC5NKjGEZ3MrXI1c3qTlpx751Xu5rg xphBhbwii3Zr/O4Isu/Qe6K3lmd9HN25m/9KmOEkdfbwx46/f5DycqoGvYBdJTjm1ODsEuPfuki UhU/PPkssXLvIBnCNHuYHO7delXV1Myi61/cm8SQQio8yzsE41zl6bNedQt/JhfhZiuRMZcJAfv cUsx69r0UmBA/7ZY+niAKenCpqoJ+KMiznDJLxMbgMt1vMbB3ccIM6REglmFTxJvcUo2KFfiZFp AR2eQiA7/wuoesJTfjiVo6iX3gPwzqJUUX4zjZWWSieoAcD5 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The MSM8916 platform uses PM8916 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: f4fb6aeafaaa ("arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5e558bcc9d87893486352e5e211f131d4a1f67e5..8f35c9af18782aa1da7089988692e6588c4b7c5d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -125,7 +125,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; }; }; From patchwork Sat Nov 30 01:44:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889046 Received: from mail-lj1-f169.google.com (mail-lj1-f169.google.com [209.85.208.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C700C70802 for ; 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Fri, 29 Nov 2024 17:44:30 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:30 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:14 +0200 Subject: [PATCH v2 02/31] arm64: dts: qcom: msm8939: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-2-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=891; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=AcRj8PcnHg5wF8WrCCf+iONlLmGYiLAyr6ue6biir2o=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3zjTODhGaXhMw5GjsZz6c6FWII/z/YB0Ziy Ek9y2EK+wmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8wAKCRCLPIo+Aiko 1XQ0CACPZUwXJeTKce9ZLzkELUgLoBtmhNIJ47J3t7RF0mOLVW8i7hH3PNG1DLlHnNe+3XJs2oM gx9Gm33onq/pI427yx7avVYmxYHqziVLV/xioQlIvKCme8YOzo6gfBTd1jAGjer8bXgbw+BqgwZ TpCRZTpRpdffPyt5xyIDg2fk24KOmD3HAT58FxirrMLhdxtJnWEYnups4ZAZ1c0SfYyLuliTvmw JQuJodVGdURcwf8P22tHW0SaD2rZROcbM3xaLL90+NNj8vXtOs3+rFW+Pda0KtgK9qo4eP2PLsQ EEX39yoJDg6zL3vzc9b8Agp1r7u31N2hK/tBPI7Yi3wO30uh X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The MSM8939 platform uses PM8916 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 7a6f1eeaa3fc438f7b6c1d3b2dd17fb1b6f81d9a..7cd5660de1b33def5b9dc8a0d02583c3eaffb17f 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -34,7 +34,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; }; }; From patchwork Sat Nov 30 01:44:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889047 Received: from mail-lj1-f174.google.com (mail-lj1-f174.google.com [209.85.208.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66979139579 for ; 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Fri, 29 Nov 2024 17:44:33 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:32 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:15 +0200 Subject: [PATCH v2 03/31] arm64: dts: qcom: msm8994: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-3-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=956; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ICsKkpn5EvTWejmupXrRW9hTH7/us+kf6N9oJ7E9bww=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3zk09ns0089zqinIfwldAGTE/e9tpdne0E1 d9WLHWwoWmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8wAKCRCLPIo+Aiko 1cgnCACl6LKeTCxlSH2Uc5kV4MVd5oBaHtbUGVCUgWxopMMc++/8PS+pOarwMxypWWJiq7iqSeH /EeKxHRvm2hLq9gJBRX4DTZe01orTqBBnvmxchjqFBsvzwddya/kzIkey8OXiIpBlySDxMFsHyB /JtOLwk7Z9rENXxvuMb6Ia8PiuyFiz2pu+ttuTRKiHP5DyIXo5HdAmZJKv0bSARgUIXiqTogGM3 ac4pkhEpWZC2oaUPGeTjvJj0iEE/OJWaQs0DQq9niPrZYcBWG2FhSfN0h1yp2QLcvNwooR4wiPr OI3dZXcnyN4VapP/xDedb33YomzaOc8W1AGJPx0vJKQQX4S/ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The MSM8994 platform uses PM8994/6 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: feeaf56ac78d ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 1acb0f159511996db07bc7543cf4f194a4ebd0fa..e6c6582ce1eab5bb6831d3458861d0d68c056316 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -34,7 +34,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; }; From patchwork Sat Nov 30 01:44:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889048 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0089713D638 for ; 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Fri, 29 Nov 2024 17:44:36 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:34 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:16 +0200 Subject: [PATCH v2 04/31] arm64: dts: qcom: qcs404: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-4-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=910; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=rR33tk4iShQizxX1vNrKanPGs6fsj3vgKiMhLvDMp+M=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3zc0cOtxzcV+s0AdlejbFKfCk3MoBgg7lHI mdE/TXRJr+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8wAKCRCLPIo+Aiko 1QlOB/9R4WPOD5FR9qjxe/CCeC1L3cVvKs+q7z4z2LeVjql5LDA9RaD3lDajRH60NKnYbzwbnBT MucSphWrWWsOspuOnFPcgfOnMM2G1pdxD0O4Yzen7I4gt1Tin1CmYCCHIe45ubo6b0VF4Yquzpb QfHHcfrf8aa8gl4bXrbLZ1djLrGH9/TzmVdbEOe5mRWxfOjJTM05jTY9u+vsL2+dATs2TM5j9gM iPmyfNPf0w/P/eNLj+XF7rH2+pYRmvzuZkSs9lXzdNvXt3GQcdOPe/koeGwXVQyjc4tbI5LDURc 5fgr32id6mSgRNJrQ4AUle2qb/orjv6JI1M/Dr4+8EWiJoml X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QCS40x platforms use PMS405 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 215ba146207afd25128692781926cf1964743655..2862474f33b0eab7c42fa2b22006f580c567ad2e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -28,7 +28,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <32764>; }; }; From patchwork Sat Nov 30 01:44:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889049 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64A37146A6F for ; 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Fri, 29 Nov 2024 17:44:38 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:37 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:17 +0200 Subject: [PATCH v2 05/31] arm64: dts: qcom: q[dr]u1000: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-5-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1483; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=dSm81W8OxeK3gTXqKdadDd4ykcQub/N1yof6klx6nCs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3zji8ysP4UCyVSUFXQNYuboVWy0jiybtvMa Vceh82CBViJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8wAKCRCLPIo+Aiko 1ZKuB/42Y3fJ2gZdOCfRli2Ua8j6hXuPAaIHMdEnD+jW7pLFAr6VpHuA9ETSrl0IJ7cPwlD/TMR JlinKHMOQZDJJFY0XFZsbpNH6OG/CPD5hkBW8SOBqP+ENPcOB4UA5YNphR3SGrV6v2baJHhwbJx yyY40TSWwNNf/iFBFq4r59nXkNWD9BO2ws4ncc74gJ7mIZFIrCm1TdPFsWRJ/Huo7KGXXch1slc +TmutrSynN2fPh8nKZVLvoesQIBv4UiNmnSzxO5cmwdsCfKVqaE+zKgTkuCL1cYJHySwP5px6CK xAupWdrwm7dz2d24Pc6lpbwbVE8NADIv1Cb2epwoEHjheMLF X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The Q[DR]U1000 platforms use PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: d1f2cfe2f669 ("arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 2 +- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index e65305f8136c886c076bd9603b48aadedf59730a..c73eda75faf8206181764df4d1ea32f96c9cfcd0 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -31,7 +31,7 @@ xo_board: xo-board-clk { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 1c781d9e24cf4d4f45380860c6d89c21e8df9925..52ce51e56e2fdc51c05fb637ed4b1922801ff94b 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -31,7 +31,7 @@ xo_board: xo-board-clk { sleep_clk: sleep-clk { compatible = "fixed-clock"; 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Fri, 29 Nov 2024 17:44:41 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:39 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:18 +0200 Subject: [PATCH v2 06/31] arm64: dts: qcom: qrb4210-rb2: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-6-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 8d58a8c0d930 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index a9540e92d3e6fc314fa91d4f055325680233f6c4..d8d4cff7d5abed405d1b4cdf9ab8264aab076830 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -545,7 +545,7 @@ can@0 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm { From patchwork Sat Nov 30 01:44:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889051 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2D461537CE for ; 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Fri, 29 Nov 2024 17:44:43 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:42 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:19 +0200 Subject: [PATCH v2 07/31] arm64: dts: qcom: sar2130p: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-7-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=916; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=YYLN/oY9BZAxpdyRliEHDR3RyIM74cdws5RTMVCcPsE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3zvZ1CMfQQQXt/FKizxvxGmQVmawDmA5ho8 E5VSxlMeG2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt8wAKCRCLPIo+Aiko 1UFWCACbOlzc7IlAG8oCNlJCwQl136NIunQVh+fy1O/hu13ZJFfYCegoa7LpJEjDn4wcrpr4z9p w2aVs2ptzbkgUiRVe6T+FxsHmhMrNEo8Cv9/rRVsowcz/iTYSNwGFJKu6JgnLQE8LebOTRvX+jk T5HP+ZPfNLwmcHHCC1Ehffa01vtJeleYbZNG8yCHYtCw6bhW9I8OmKVa8Hh2vGgP97BH5KzY1LC iNJ6IIsh6I8rf8F7apys1tmTE2/4MZNGHhjy9EDbL9iLX6qw1vyUrC8hcfzof2Dc/+j9jw0F8TL 5UOmVeQG9t19apBQNNSZfEek3wLqsX3kugYkOCUigI2hqQ7s X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SAR2130P platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: be9115bfe5bf ("arm64: dts: qcom: sar2130p: add support for SAR2130P") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 56f40e8ecae561d49331e51c57581d517dbc9b51..dd832e6816be85817fd1ecc853f8d4c800826bc4 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -37,7 +37,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; }; }; From patchwork Sat Nov 30 01:44:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889052 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 255DD155330 for ; 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Fri, 29 Nov 2024 17:44:46 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:45 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:20 +0200 Subject: [PATCH v2 08/31] arm64: dts: qcom: sc7280: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-8-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=918; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=cwHGT8dW2fufdVjeg8a7nAT+ERCmV5CuNqJS2eXbLFY=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm30t8SRmKOAuhUMuhgKfV7LHUvg4Wstu57so qZdzx/edM6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9AAKCRCLPIo+Aiko 1aLuB/sECWiL2m2/MeQbPYtq6Q21sh6UP8on1KMocDd5jR4v6VgOSCOz7vTlB4l5sLpMYAXD5gp Gr8eB6kG/oGpdemcwWSVhmNvmySIxn1Ad0JMVx+PtXf9Pq7yCQhtYDzCQfbk2LuhW+c03cbq/5Y jrLwQC4RKjNyK9OS3grA3nKD5exT8t0y3XUKtIe2iuqnszRHuVxeXcQuAJcV1YHyyjP0EYYc4Q/ CiW5lhaL0VYBdVZJNsiFgrgfsnsHE9vo9noJ1g9LC+Y5O6tLzsDB/WVwJIlunnAaHTaQZVuovop l6TzjBSgDM5Skn3CZZmyFNW5DkFut5i91qCIcxJizY5V0cx6 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SC7280 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1f4e7f740d ("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 55db1c83ef5517f82504816baeee583695065225..d12e0a63fd087461a33622e8771422c8acfdbc25 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -83,7 +83,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Sat Nov 30 01:44:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889053 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1E02155336 for ; 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Fri, 29 Nov 2024 17:44:48 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:47 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:21 +0200 Subject: [PATCH v2 09/31] arm64: dts: qcom: sdx75: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-9-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=905; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=uDWgj6B6z6pMSFBL1pDRW22fgNDuN+DRFtZx84ZsB8Q=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm30pfJMn8PDDLs925WYOn/LCHvSzJP4zGYkY KKGceA+neeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9AAKCRCLPIo+Aiko 1VPGCACCKSMVPp1sa9k9ikCTg6c8wgTiucncPgose2E2WhjKjVKGIYWNTuT8TtGHLwu6fkJsFzY zx7Vcidqf0sBvJ0YcZv9Xp7xSMLkLCW9MZHuxRSgEMll0MlM5Eu1sb0nD+MY4hoQcwy40eWBxH8 UNjd6DTHEKJNQAfUQ8gnNxTNBvouhJ2t+I7DqloaaHmopzj6A2n6u2B8LB0N98RtiLW6C4H2Mm9 bbsU0sC5lKF+Wd2wK49Xac4oXaKCaKt4mmta8TyTMCwzfpHfqVTJZ4TyHDe2s7fn5o2h0QDpuLL qgsHdn4E80tqCOVNBldGp9Le7iAsO0ivi/jzgA6zabS+aVwJ X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SDX75 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9181bb939984 ("arm64: dts: qcom: Add SDX75 platform and IDP board support") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 5f7e59ecf1ca6298cb252ee0654bc7eaeefbd303..68d7dbe037b6ac49c746171e8dabd416c8813a38 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -34,7 +34,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Sat Nov 30 01:44:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889054 Received: from mail-lf1-f53.google.com (mail-lf1-f53.google.com [209.85.167.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3858315A86A for ; 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Fri, 29 Nov 2024 17:44:51 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:50 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:22 +0200 Subject: [PATCH v2 10/31] arm64: dts: qcom: sm4450: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-10-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=888; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=o/j8/+TO8OD48smfSUKUdOz/ApCt6Naf9bzdvgRGXWo=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm30Q9G1cCTXOPTx2dTJNxkog61JFfnb5hKE1 85pZ2nBxB2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9AAKCRCLPIo+Aiko 1eo4B/9Z4HSdH7h5Ma+J+mN8AU7NmBowokudpJz9rVuhxYMWz3xdMQx57sm7THAX9CKFhA7Fdn+ tgvPenMdzkYidciMrmcXw/Z0Qbt5oD+TO2DG4bRbMarDNFeGPBqPIwufwJxUkPrmpQN9xi7LGky /uryff+5Z87MzG0e9RCXzHtjge5nm6GbiVuq671Ut8Lb6KhuNE6DZGkbyiOxBQumNCAyzAlkH0v BxhaKPTitoasm23Dc3gv9R8Rm3psCGAzZFNBI8RG1pLtkvXIIb+TD5RD6PJzjWmhvzokVOB1aoN h33uMTSSSnYyDCYeu+LhdnNltO1XKpfWsvsX0Ao/zzq+a8cP X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM4450 platform uses PM4450 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 7a1fd03e7410 ("arm64: dts: qcom: Adds base SM4450 DTSI") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index a0de5fe16faae5674efb0070d4017983c86603c4..27453771aa68a1c4dbd2a986af6785fa05db147d 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -29,7 +29,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; From patchwork Sat Nov 30 01:44:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889055 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD04C16F8E9 for ; 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Fri, 29 Nov 2024 17:44:54 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:52 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:23 +0200 Subject: [PATCH v2 11/31] arm64: dts: qcom: sm6125: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-11-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=928; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=q3UE0E2mDZCC929aI9do16YaC9c3UMVZhi0tXk/GPcs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm30wZw1UBZsPTjf9xNdqvcaOd9XA8j7YB7bR oxw1NHD9lKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9AAKCRCLPIo+Aiko 1TV6B/kB8sg3FuiJJxDK8ulc0P4XwZf6YfrWFQfF2PkODvBX5FwGdrS/It0JBMHAbbbhWYSo8lS ya5FFkeQ2ixl/GZLih1jNIilAwUOy4HKdkAdJVyBSoa2YFzgDQ6o+ugPdf1am+IxAoya4PYAVme NHEQ6hSOsun3Xz6vD1tBRTUhPYT+yvgFdHxexqM/ncm2dLe66LhiePOxav49zyI7I3hgI7i8D2S hCqudhtGq/dr+Aco20746ZDK9zy2hshwcMFfynXf8zmjaaa/Hc8fswHtKvgZBLLQVdnsXQpJTC5 BxWIqP9VSdcBMtAcxTPgP/q6LNFiOUluVJy/8SRlC7z6Neor X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM6125 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 17d528d639343b9d649167d231aad3aa63474435..f3f207dcac84fa2f72fa9222c26ab3d7fe8813b2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -28,7 +28,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; }; From patchwork Sat Nov 30 01:44:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889056 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B235188717 for ; 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Fri, 29 Nov 2024 17:44:56 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:55 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:24 +0200 Subject: [PATCH v2 12/31] arm64: dts: qcom: sm6375: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-12-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=912; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=pg+0ixud7QxxrDakgimvHJR2/Qzsae3oMGYCum0sTmc=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm30pgr9Naoq+3Qet72FV6DwivG+cEdaNoCl8 Co+czkbIsyJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9AAKCRCLPIo+Aiko 1Xg1B/92NJCJdlLS/k0Z3h+rzI/LkaRkV9Jl8wywC9w93L/MjLmdjFWCIUkp9sXn4GmRhwXVeAr MUu9whrSnpmxNRWjpyIQ+MFNLjUKRy0yQmA1JeT3u/gudy7hqUoglQA4ejPTTDZOzbuh2chys0D jFGa9k72G7oqDrieYKHc9rONxkKFoj/jbUqXC62Ov95V9wMOqGNF8LZBAR7wTEy96dBRcmRgY98 IZzUPXSN+phglaoYbCasSiOxN8kwqsgFMRobRniIbUfb2bCmYnkrKpSqpjGa7EXyCNFgdqsyC9Y IknUev7fIFeNcYRAJy7FgqnXyW1H6oXo/PYxAqv4qbfLtllA X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM6375 platform uses PM6125 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index e0b1c54e98c0e8d244b5f658eaee2af5001c3855..7c929168ed0805e832b818516083d48968d3bbce 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -29,7 +29,7 @@ xo_board_clk: xo-board-clk { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Sat Nov 30 01:44:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889057 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42BB0197A87 for ; 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Fri, 29 Nov 2024 17:44:59 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:44:58 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:25 +0200 Subject: [PATCH v2 13/31] arm64: dts: qcom: sm8250: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-13-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=920; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=t0rQXPrtoBaJrNoELAVHdj8ug8kB5TUw+I/NzNZW0co=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm30/qqutm8AVBRdVsmflA7t8c5bUdq73r6kN R+8xAYCD4aJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9AAKCRCLPIo+Aiko 1eW5B/46A3mdgHPzPqYR3PvfQwBQ9sznJYapBsJiiLdEFmxjr0JD084s3D54kXfBT7PPLOZSV2C Pju8Zov83BNTZgPTrSA+Zx6HUYOoxAvP8Lc3Hn/Pmh0uHXxeG0Soltp6cPi1x5S6FAR1dXiEDNj FKvBpVAs4gBWuKBqsCxmHNSQ/2iaL6vOCTtU41y96avgkTHbCouvIP3pz+f+yLEL3X364tAdNsf +gAzeGEvHFR/fm5ppnbRssqBvdeD4SXp1D13W7B/G19qnxLkU//sq8Ta4YVh7H8kSSgeia7+0/G ZUm4Wya0m5oBe2th1Kn3UNIPobBmXsvXnm5JAzTssurUruIO X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8250 platform uses PM8150 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 9ff8b0591fcf ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 48318ed1ce98ab40de75129cb9bdfe32eda4c004..f39318304da8d02ded9bc4ff833bc88139ded744 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -84,7 +84,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32768>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Sat Nov 30 01:44:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889058 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D52FE199FDE for ; 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Fri, 29 Nov 2024 17:45:02 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:00 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:26 +0200 Subject: [PATCH v2 14/31] arm64: dts: qcom: sm8350: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-14-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 877905dfd861edbcd083e6691a7cfa1279164ffc..15b7f15b3836dc544cb1209ab36df85263d612a1 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -42,7 +42,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; }; From patchwork Sat Nov 30 01:44:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889059 Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8322713A3F2 for ; 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Fri, 29 Nov 2024 17:45:04 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:03 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:27 +0200 Subject: [PATCH v2 15/31] arm64: dts: qcom: sm8450: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-15-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=891; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=kRo+lLE1W0MzRHuVjiZ53lpqFjRc/n5gL1+u9Wg23vI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm31ZCubTdxrQSYCqGPtgwvvXuH0vanV5BbkQ E+EKRfB7JmJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9QAKCRCLPIo+Aiko 1eSBB/wKjVAzUj5M6b+XByRsvi0UZPlpv5qTLjszhyTKQzXl2fkADYu43wP5syy0QdmbuQ9oV9f Pk24fHsozeixUuPa+Z6EvgRX83KZiU/7t9t8czMg+tvMIzv5BtW0aXD3GwGZ55ure1p/UpNygKx U7DZrgFebI1njHwsrPfHpsH73HqKw6WQsPS5iJ2j4C9pd7VkanjsEcGzZFgxzrYEm78cwINl6Zz /tJc/vKNrB9bIVGKVX+vJbotSAj1ky9FNTJAXzQc6EzhqfT1JyqDB1JKqMofM+EARBprGS8BfOp G5mv4xPQba21kxtcVJsJM0ML9/me3tQ/1n1hOmMS6RQeDGoV X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8450 platform uses PMK8350 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 53147aa6f7e4acb102dd5dee51f0aec164b971c7..7a0b901799bc327b9d31bd84e8a00fd62b451596 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -43,7 +43,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32000>; + clock-frequency = <32764>; }; }; From patchwork Sat Nov 30 01:44:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889060 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14CED198E9E for ; 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Fri, 29 Nov 2024 17:45:06 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:06 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:28 +0200 Subject: [PATCH v2 16/31] arm64: dts: qcom: sm8550: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-16-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3849; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=oCnFN08aVITyKXapk9h/eTP1McSoWUQ0a6cbzA6vc4M=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm3152hw1YL7asiFs4Su9D0LkAteWjzprRzAj u7wUlgNx7CJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9QAKCRCLPIo+Aiko 1RRUCACeWyG6A8xUX2FF3xZdrvsh31tzdcn3f6pPfdU6n8Taks8khEMH+DAkjLdqcT9OL0499N5 wMj4Sfb/2pPEg6pk8u1XAzSdcWvu60w1WUjUMsQLIiAb0TylD8i6jmQT8eozYrxUATQD0LPV0NP 7lc+x9/axKbU1M9HBrfo8tU+jKKQ8TLDVYKcLW4ukm+E6Zf2fhxjypgJc9xA9bQ1nFeG5rdWeRK S9KVKvw/mPhqVO8Og+iX1N1o3Kw4mBCCuiUnCTYs86KMPLjYAUv0dRCLEjjbHmek3aVgre0+YrL 46MUMzLMH0g3/o+6bXHEkT3POLLDu+tvjqqVB9Srg/XjrcJ5 X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8550 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: ba2c082a401f ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index f6960e2d466a26bec4e5c3d31ac0bf54168ca1e5..e6ac529e6b7216ac4b9e10900c5ddc9a06c9011c 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -367,7 +367,7 @@ &pm8550b_eusb2_repeater { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 01c921602605726928bcba71abd937869880ea0d..29bc1ddfc7b25f203c9f3b530610e45c44ae4fb2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1172,7 +1172,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index ab447fc252f7dd705fbe29725805bc1c146c10f9..5648ab60ba4c4bfaf5baa289969898277ee57cef 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -825,7 +825,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 6052dd922ec55c65089e6b08e36c355b01bf24fa..3a6cb279130489168f8d20a6e27808647debdb41 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1005,7 +1005,7 @@ &remoteproc_mpss { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 3c5d8d26704fd925857b5ddcc6067c2b14e1403d..e8383faac576a2f401fff74231a764712c832291 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -565,7 +565,7 @@ &remoteproc_mpss { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 85d487ef80a0be5c3586d9de69327abd2b64209b..d90dc7b37c4a74cbfb03c929646fda3381413084 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -722,7 +722,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &tlmm { From patchwork Sat Nov 30 01:44:29 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=1965; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=k6VUs1ScFCdCh+SFXZEEGEWQ1wMPimPue9P3iT/F5+E=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm31N53BVunJtGm69GZ1EaEc658s6CQsIs60X wwwFfQMxH6JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9QAKCRCLPIo+Aiko 1YppB/9BnIg7VHJpJlZtPXIQoFZHFrdmnWqOYrVY879AQBFUvrYFyCQp7XLARzoNb+Kt8q5W8Nm bHInu6YNUUYDtpWSA5QxCVppNwXctb7uvWHJf1qJpqTAHlxniqxwAaZd//MyPiPlqtQO4l3SRi6 CAy9kF4JoW0fixpR61Yh1MbkZgRBxAZ6A5ok/FwetIis8PN5ES3xlx0Rw0+MVClNLM3HTPOhY2m n/p+w43OPCvKZYlu/5GczV5JSF14FEi5NnQBlOJL6PHoZLZdwnGgR50E6+nBAgP68ihJxh+cGPg /Yqi77HjFsFcSX3aaBv8+3lH8FITTojvJY12v0iuA6ifLNrC X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SM8650 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 2 +- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index f00bdff4280af22f6f8b23e33238f53c602bc169..d0912735b54e5090f9f213c2c9341e03effbbbff 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1113,7 +1113,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 0db2cb03f252d19a1f8b171a562a8e06290c8a21..76ef43c10f77d8329ccf0a05c9d590a46372315f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -730,7 +730,7 @@ &sdhc_2 { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &swr0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index c5e8c3c2df91a49476f49832c0bd6418f4dfae3d..71033fba21b56bc63620dca3e453c14191739675 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1041,7 +1041,7 @@ &remoteproc_mpss { }; &sleep_clk { - clock-frequency = <32000>; + clock-frequency = <32764>; }; &spi4 { From patchwork Sat Nov 30 01:44:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889062 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD19E1A01D4 for ; Sat, 30 Nov 2024 01:45:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 29 Nov 2024 17:45:09 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:08 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:30 +0200 Subject: [PATCH v2 18/31] arm64: dts: qcom: x1e80100: correct sleep clock frequency Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-18-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=918; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=ZvLjLTixMdBQjoPe24nZu6YTlSKcs32JUm86ti1qKNg=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQ7pX7tdeIW0JHfv00sobK/M55wbeeu6Y6GF9Zlvycb+9v /sV9bw7GY1YGBi5GGTFFFl8ClqmxmxKDvuwY2o9zCBWJpApDFycAjCRoofs39QiZTY78QbWcGx8 c5vzXYrg5GrJtcnrFJQjA5fEtf4MnyWXPqXM6VTHh2CGfR5GslsXBTtUsT0Q/X7fbCN7TlzaifQ VksICe9m5VnFH1B4/FbfHYFF+a/PNA68nq2065Syo3Rz+Uk+t6MWvQ4l5lWczQkVm7ldgemNeee 908O7Lmq/Ej0cmxR7QEpuzflf6V/0ga872+H3/1+3U6Np3QTRpz48DZUmeyq/sax1lq35kfVO/G axm8LV2uqxXUc5r89m6Z7JVlsTe/Fd9O/gn6wqBztlKRd5cV26EZfm23fhhLriJ20nJ9sVC0c7g jhcOdrefC9wJskpLkLld8l/uclnNdc/18i9OnRdcGg4A X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The X1E80100 platform uses PMK8550 to provide sleep clock. According to the documentation, that clock has 32.7645 kHz frequency. Correct the sleep clock definition. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..8f3c4c6a1fbc57412258be820e480c1bff7b520a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -38,7 +38,7 @@ xo_board: xo-board { sleep_clk: sleep-clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32764>; #clock-cells = <0>; }; From patchwork Sat Nov 30 01:44:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889063 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CC2F1A2C15 for ; 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Fri, 29 Nov 2024 17:45:12 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:11 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:31 +0200 Subject: [PATCH v2 19/31] arm64: dts: qcom: sc8180x: drop extra XO clock frequencies Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-19-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Drop duplicate overrides from Primus and Lenovo Flex 5G DT files. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 4 ---- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 4 ---- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 62de4774c556d3954a797287ba2ecb36d979dc9f..21c2d25a294506de41f6e8b7197be85c02d03568 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -681,10 +681,6 @@ &wifi { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL */ &pmc8180c_gpios { diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 79b4d293ea1e70d68346e7c5458c94f7c2b6f1eb..7a4bd6955470338dd9c7a628c9f9a01de8b480ac 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -773,10 +773,6 @@ &wifi { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; 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This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 8 -------- arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts | 8 -------- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 ++ 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index 8460b538eb6a3e2d6b971bd9637309809e0c0f0c..9bb87b7fd25777d4ba13bd2bb36024b8035d8afd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -38,10 +38,6 @@ &sdhc_1 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - &tlmm { sdc_default_state: sdc-default-state { clk-pins { @@ -78,7 +74,3 @@ &usb_dwc { &usbphy0 { status = "okay"; }; - -&xo_board_clk { - clock-frequency = <24000000>; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts index 5bb021cb29cd39cb95035bfac1bdbc976439838b..af281c285447f9845f542cc9d976fcdc7f1cf766 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-tplink-archer-ax55-v1.dts @@ -95,10 +95,6 @@ &blsp1_uart1 { status = "okay"; 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Fri, 29 Nov 2024 17:45:17 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:16 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:33 +0200 Subject: [PATCH v2 21/31] arm64: dts: qcom: ipq5332: move board clocks to ipq5332.dtsi file Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-21-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1803; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=dkeL8p4HqSsIjxDugM32Q10QGE/4T67RadiEMJJD0gI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm32X/ox1dWMNmNpSwGRsBnocHf/cdBjMzQVw 7vsl7U7+KOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9gAKCRCLPIo+Aiko 1d7hB/9+/oXyifnNs5CTfv485a6zBmhHI3Ptc77Y4K8SMCjRhkvmwqRbkPsUVqtVSWReNxdLTY3 9LxoWLzJ9M6KrgY81QkFxwps8zZHSVKlOUTCrP3YI2BNOwbZ6lxLEsv3vxGsRGngTEGd3+oebk6 ySHLdyBQ8ms6pJ4r8vIGjYgtbq0+xi7xNCAU5joyQKlSBWmDX8OFSkb4BNLEaCkcXgw9qMjzsNd 62ZdknBL0xgtKGJ2ZdX47N/EbkOV876Jxvs6IItK3Vt1s6fnmvoTb6JgvT80AY+Pi1FNV7mXNx4 C0B8Q0+vwZcUvjUqvOtRXPm5eIF8d+0a6g4DfBn/iEf4OmHT X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A IPQ5332 is one of the platforms where board-level clocks (XO, sleep) definitions are split between the SoC dtsi file and the board file. This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 8 -------- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 2 ++ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi index b37ae7749083f43f482231c1de9f99ac28ea2b66..efe4ed4a5d9fabad1137fc7211c95ef38e69c0be 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -55,14 +55,6 @@ &blsp1_uart0 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - /* PINCTRL */ &tlmm { gpio_keys_default: gpio-keys-default-state { diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index d3c3e215a15cfc3998f8e30656828a46b6991898..29feb27df5d4314bb2d2eac50ab320e173e8c7f9 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -19,11 +19,13 @@ clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; 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Fri, 29 Nov 2024 17:45:19 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:18 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:34 +0200 Subject: [PATCH v2 22/31] arm64: dts: qcom: ipq5424: move board clocks to ipq5424.dtsi file Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-22-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 9 --------- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 2 ++ 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index d4d31026a02624fb5ca08cd7fc6dde9d10fc9b81..e78d2dd9148d7daaffc007322493577ff2ca6c7a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -18,10 +18,6 @@ aliases { }; }; -&sleep_clk { - clock-frequency = <32000>; -}; - &tlmm { sdc_default_state: sdc-default-state { clk-pins { @@ -52,8 +48,3 @@ &uart1 { pinctrl-names = "default"; status = "okay"; }; - -&xo_board { - clock-frequency = <24000000>; -}; - diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 5e219f9004123caa45e5e9e303662e3e92a56c57..85bfe5edd9ddc2da0897aa5a4d43a68116007d9a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -20,11 +20,13 @@ clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; 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This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi | 8 -------- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi index 91e104b0f86534ce02349c7b69b36f4c5e602c6d..d1af7c55f6256e9297c86df2b3a1ab68fc636862 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi @@ -114,10 +114,6 @@ mp5496_l2: l2 { }; }; -&sleep_clk { - clock-frequency = <32000>; -}; - &tlmm { spi_0_pins: spi-0-state { pins = "gpio11", "gpio12", "gpio13", "gpio14"; @@ -163,7 +159,3 @@ &usb_0_qusbphy { &usb3 { status = "okay"; }; - -&xo_board_clk { - clock-frequency = <24000000>; -}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index d1fd35ebc4a28bafee77e7be441709f99f482558..7e519db962d140989887f6ca9cc270a6666dfb58 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -22,11 +22,13 @@ clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; 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This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1 + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index f0746123e594d5ce5cc314c956eaca11556a9211..c653b178f5034d2cb19868b241a4c36459028d57 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -29,6 +29,7 @@ clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; + clock-frequency = <38400000>; }; sleep_clk: sleep-clk { diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 7a789b41c2f1887f0c41ae24da2e2fe8915ab13c..2030e59f8fa162fdd8b66d31dce00bb44aabde5e 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -624,7 +624,3 @@ &wifi { firmware-name = "qcm2290"; status = "okay"; }; - -&xo_board { - clock-frequency = <38400000>; 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a=openpgp-sha256; l=3869; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=JjPpXCp+YkT/eXiY1YYIwN7gXkPlXjyGgVYw6L4BL40=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm32JloeBcaHMD8trR1qmOsBaxUwdHmP74ZvY kJFzPnM5DqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9gAKCRCLPIo+Aiko 1WTOB/45i3FcA/MSkn4F8pspIU946puZFdxeMttvqaZOPviCYKTQz9KgKvXTNEz83GvSGH4p2WL EDaq7YnwoMZeXJsKw/5cVeklyKHSsIDSY9JkdaS8PeVtJxx6hRqJHpdOwxmC3s9JWr/CxwWRgMH /sUiA1iB3khayI1tBOoaP30W8O/d5HmLHrBsH7ah/dUlxttxaPvSszeQhtRwCIB3BF1l1setmYN EhBfHvhmsXjXJRLQ3rHmXlvVZ5nqPeOVfcimDXyz+2HaY9sdD2X2+EnsSwRDzfZppHrSOq2Tur3 +C/hlPl/mBrvqLDMx8X0fF6fntbYtD+lXKUU5KYs3KbPNMQA X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A SC8280XP, SA8540P and SA8295P have main XO clock definition split between the SoC dtsi file and the board file. This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 4 ---- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ---- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 4 ---- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 4 ---- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 4 ---- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + 6 files changed, 1 insertion(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 2fd1dafe63ce7a4f409d19946b9f10ffe324fba3..c536df2acc66276a0bf4e3b2640ee204109867f7 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -728,10 +728,6 @@ &usb_2_qmpphy1 { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL */ &pmm8540a_gpios { diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 177b9dad6ff703467ea4d10e0f5a651d11569275..64c35a72a828c128f9dbe9e3537a3f777d21713b 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -503,10 +503,6 @@ &usb_2_qmpphy0 { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL */ &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 75adaa19d1c3e0c8fcad40c7d0b0afb504331d75..61ae4d0a9e7d10387a8331fbc22d5f88edaa9c23 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -868,10 +868,6 @@ &usb_1_qmpphy_out { remote-endpoint = <&pmic_glink_con1_ss>; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL - additions to nodes defined in sc8280xp.dtsi */ &pmc8280_1_gpios { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index f3190f408f4b2c7ca9fe368d652d5d66bb3949af..bee1e143178be5971a5916c368a5e8c864927b47 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1481,10 +1481,6 @@ &wsamacro { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL */ &lpass_tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index ae5daeac8fe284bbec86622c10e6831d60a25297..c4a19ecbd894cbdd0521bbf784efd23f46eb07f0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -837,10 +837,6 @@ &wsamacro { status = "okay"; }; -&xo_board_clk { - clock-frequency = <38400000>; -}; - /* PINCTRL */ &lpass_tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ef06d1ac084d3205a149feff880f457822dca2b4..e6517ad9408d9a49da9c00bcb661f32539fa32e6 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -31,6 +31,7 @@ clocks { xo_board_clk: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-frequency = <38400000>; }; sleep_clk: sleep-clk { From patchwork Sat Nov 30 01:44:38 2024 Content-Type: text/plain; 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a=openpgp-sha256; l=3935; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Uy0U0ERr39hDg3O49x0h3zoYcwr/oL9Yd1/e2vOTYSE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm33+KjqyOEr/xJY9QiDeHeTCec5MxeXer3v3 /563gSdcqWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9wAKCRCLPIo+Aiko 1SHpB/9HXYBNkPzn7RniXXS5K8Hjs0qzQAZvGwSnyAEaIVO595wk5rkt8gtsNyzffh3xH/XX2vC fmaEx/jrdtVetRV5IGsvfcCVIG7r/5sdf/kr2vyvKC6ahlTdK9e5wVElry+xK1nWvWtNtDiksz6 74/1NdXFLvAVzaUiNH0FkBPSMsXAbDx/m0P9FjxedLtdEb7UrY+x2lUUN+GkJNoqxAWGvC+kjL8 5GFGQB3iEsBRhR4PmKGMEeJMerHCk2Gj4lPk8VG59Rg9rHUAiFiDhnW9AyVDeSN2ffhx2QwsuM3 jSdV1z8WhzA4GmoPbz9DQpLR8N5iSku9fvE9Ea5NidYBLOKP X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A SM6115, SM4250 and QRB4210 have board-level clocks (XO, sleep) definitions split between the SoC dtsi file and the board file. This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 8 -------- arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 8 -------- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 8 -------- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 8 -------- 5 files changed, 2 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index d8d4cff7d5abed405d1b4cdf9ab8264aab076830..675f9057ed442fb4afd22064b4022df5ed8cb882 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -544,10 +544,6 @@ can@0 { }; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &tlmm { gpio-reserved-ranges = <43 2>, <49 1>, <54 1>, <56 3>, <61 2>, <64 1>, @@ -695,7 +691,3 @@ &wifi { status = "okay"; }; - -&xo_board { - clock-frequency = <19200000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index 9153a5a55ed9fe82ea6771ef87dae5620a4fbf2f..ae65dc2abe510d35f1aeeeac5ccf5c576d688734 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -193,10 +193,6 @@ vreg_l24a: l24 { }; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &sdhc_2 { vmmc-supply = <&vreg_l22a>; vqmmc-supply = <&vreg_l5a>; @@ -254,7 +250,3 @@ &usb_hsphy { vdda-phy-dpdm-supply = <&vreg_l15a>; status = "okay"; }; - -&xo_board { - clock-frequency = <19200000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index f60d36c03b9b51d1ba5fb2db7d619916fe42f084..5cf0d2383019abec53f875c727e86656f3ac4478 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -471,10 +471,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &tlmm { gpio-reserved-ranges = <0 4>, <14 4>; @@ -570,7 +566,3 @@ &wifi { status = "okay"; }; - -&xo_board { - clock-frequency = <19200000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 9b23534c456bde8c400cc331e847f0f84ae0b74a..29eb179ac519dd0965977902ca0edf6a06fa147b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -28,11 +28,13 @@ clocks { xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; + clock-frequency = <19200000>; }; sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; + clock-frequency = <32764>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 9d78bb3f71901705fd22d88b472f6fc1d0c0fffb..27936023175bcb73e73a85b463c4b9f5c00541cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -305,10 +305,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &tlmm { gpio-reserved-ranges = <14 4>; @@ -382,7 +378,3 @@ &wifi { qcom,ath10k-calibration-variant = "Lenovo_P11"; status = "okay"; }; - -&xo_board { - clock-frequency = <19200000>; -}; From patchwork Sat Nov 30 01:44:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889071 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 760A51AB534 for ; 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This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts | 4 ---- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index e04a3b8f81c556713550cd22feb2d0f282564baa..9840868fc7196316bbf9d2de9b8967ba73e541d9 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -454,7 +454,3 @@ &wifi { vdd-3.3-ch1-supply = <&pm6125_l21>; status = "okay"; }; - -&xo_board_clk { - clock-frequency = <19200000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 7c929168ed0805e832b818516083d48968d3bbce..013666efbbe8b5b9c12f3d7dcab0b59de8a69c50 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -25,6 +25,7 @@ clocks { xo_board_clk: xo-board-clk { compatible = "fixed-clock"; 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Fri, 29 Nov 2024 17:45:34 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:33 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:40 +0200 Subject: [PATCH v2 28/31] arm64: dts: qcom: sm8550: move board clocks to sm8550.dtsi file Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-28-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5523; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Nreu1u5iw3CPT/3n6jHeCOVz+ph8i8GPQOf5hBrI5+Y=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm33pfZrPKRbfNTzfbxoE3XkoZqqTSBvkHhTz m6B89ThZYiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9wAKCRCLPIo+Aiko 1RTuB/9/fvVB6jLGXy1ipcXvp1c/GzBhPxTJ2aExfiZCJYgjPAZmpAdl1sID4fRTorI97hLJnJB CsNoY4JH0XP0HiRub9vGha0FfcPoBhVSpRVnH9eFv3fUqYMFU9NcFEDH4tYy5hxMnlAlm1T600C 5GfBD/Z39PySdcNHSdBX5rFFvnOhmleY5UHYrFHaKhC2OKj7d6kNaUmDVn0WPyApSMeR2G8VzGo 8qhqUE2ev8QW8XJJ3OVvoogIELj4rFbflnqEJieTK4JYqnhncsh4g2vXxKaGM8MRxctIogmidKu eZwtx1vd5S/AtCDDnXx0Rp+M8+DO37rPkxCFK5O5clWU3MsK X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A SM8550 is one of the platforms where board-level clocks (XO, sleep) definitions are split between the SoC dtsi file and the board file. This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 8 -------- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 7 files changed, 2 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b7216ac4b9e10900c5ddc9a06c9011c..9f1f99f892f5f92ba0e44bd9cc3daeb2916387b2 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -366,10 +366,6 @@ &pm8550b_eusb2_repeater { vdd3-supply = <&vreg_l5b_3p1>; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &ufs_mem_hc { reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l17b_2p5>; @@ -399,7 +395,3 @@ &usb_dp_qmpphy { vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 29bc1ddfc7b25f203c9f3b530610e45c44ae4fb2..656c2b1facd656736495d103b7aa57708d6ad38b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1171,10 +1171,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &swr0 { status = "okay"; @@ -1367,7 +1363,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5648ab60ba4c4bfaf5baa289969898277ee57cef..0e04ca10d04cefe197bc3278675809f73d61b65a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -824,10 +824,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &swr0 { status = "okay"; @@ -971,7 +967,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 3a6cb279130489168f8d20a6e27808647debdb41..63b5f4be6fe91af799104d1384624b0a4dc592fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1004,10 +1004,6 @@ &remoteproc_mpss { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &swr0 { status = "okay"; @@ -1229,7 +1225,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&redriver_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index e8383faac576a2f401fff74231a764712c832291..9d319a0c89be4b67ff4f2934b5526ce2ab5734cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -564,10 +564,6 @@ &remoteproc_mpss { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &tlmm { gpio-reserved-ranges = <36 4>, <50 2>; }; @@ -587,7 +583,3 @@ &ufs_mem_phy { vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a74cbfb03c929646fda3381413084..0e03ab2ac2eed716712833195ae56f5689a577cb 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -721,10 +721,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &tlmm { gpio-reserved-ranges = <32 8>; }; @@ -759,7 +755,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e7774d32fb6d2288748ecec00bf525b2b3c40fbb..e6dccb199d7fb4c4a15294c3f22eb842e4c32ce6 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -36,11 +36,13 @@ clocks { xo_board: xo-board { compatible = "fixed-clock"; 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Fri, 29 Nov 2024 17:45:36 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:35 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:41 +0200 Subject: [PATCH v2 29/31] arm64: dts: qcom: sm8650: move board clocks to sm8650.dtsi file Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-29-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This is not optimal, as the clocks are a part of the SoC + PMICs design. Frequencies are common for the whole set of devices using the same SoC. Remove the split and move frequencies to the SoC DTSI file. Suggested-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 8 -------- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++ 4 files changed, 2 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index d0912735b54e5090f9f213c2c9341e03effbbbff..f509689af1c2e0dd6ea85edebe490538ff43964c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1112,10 +1112,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &swr0 { status = "okay"; @@ -1337,7 +1333,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 76ef43c10f77d8329ccf0a05c9d590a46372315f..9a7f98d922af887657b4b56b5e271cc4b590db2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -729,10 +729,6 @@ &sdhc_2 { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &swr0 { status = "okay"; @@ -884,7 +880,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&pmic_glink_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 71033fba21b56bc63620dca3e453c14191739675..4943127e27a15af72f6d3f281550b1d8ac0ab77c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1040,10 +1040,6 @@ &remoteproc_mpss { status = "okay"; }; -&sleep_clk { - clock-frequency = <32764>; -}; - &spi4 { status = "okay"; @@ -1320,7 +1316,3 @@ &usb_dp_qmpphy { &usb_dp_qmpphy_out { remote-endpoint = <&redriver_ss_in>; }; - -&xo_board { - clock-frequency = <76800000>; -}; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 25e47505adcb790d09f1d2726386438487255824..cda249f767e5f1766134c62a8e5f312ed17e17d5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -38,11 +38,13 @@ clocks { xo_board: xo-board { compatible = "fixed-clock"; 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Fri, 29 Nov 2024 17:45:39 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:38 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:42 +0200 Subject: [PATCH v2 30/31] arm64: dts: qcom: sdm670: move board clocks to sdm670.dtsi file Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-30-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1867; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=LwSpKOq1GqZouqzSTW+vvDI2/fjTuTTRV2CIEe3lHrs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm33NmIQwFBxIPvKGEcX3mja1XLN8tpDXTi3Z hYENw+jxtWJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9wAKCRCLPIo+Aiko 1cOBCACpjdhJHKSJDtiOo+gFZ+54Dvs+BgIb46W8od5CZ8yPgwOpGjtQhSljfkfFG1rvRo47o0d aTUmkReCJ/jfuTUkXArISpuA03yjh7UlAuk6SjAXd601nXgq2Z+cjv0kJ1iUncaGmGmAzxvG/5h 9+BXzkIeO+XjKLIvzPZdgBoSI++Ovkq8UOVdf8I9OwadN2h7lcrS20h2HD6Jq/03Wp4qENulECB BKbqrjiEsxKWqRgw0kUhUedUwvYsbwuLEsyiOzXcToQc9/Ru3rwWoa5tiBRZP8qliC2f82U4Uom 7HDiv+NfOhr1U7evafpfct/L67h+0cMfUlI0YMapoiTCnaEE X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The SDM670 devices define XO and clocks completely in the board files, despite sdm670.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the sdm670.dtsi file. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 14 -------------- arch/arm64/boot/dts/qcom/sdm670.dtsi | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index 176b0119fe6d45d7d3fa584f1825f4e4e681c2e7..44b708c8a4e4ef5ee1d9110bba372d230fdd5b4b 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -49,20 +49,6 @@ framebuffer@9c000000 { }; }; - clocks { - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; - }; - - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; - }; - gpio-keys { compatible = "gpio-keys"; autorepeat; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index c93dd06c0b7d6444aefd0e24201cea999dcb23a4..c4fd7598d1ca8d8baf4c3da0e20cb191f7883f0a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -28,6 +28,20 @@ / { chosen { }; + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; From patchwork Sat Nov 30 01:44:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13889075 Received: from mail-lj1-f172.google.com (mail-lj1-f172.google.com [209.85.208.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB8ED14AD17 for ; Sat, 30 Nov 2024 01:45:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732931145; cv=none; b=SkHf5WSE7Hz9Jp0pyYhIX9t1u7VZHI1q3Gs9nbACHbYkKFPP1CNH7jmxhKmEWY/fKy7tFV6GjzU2G5OGskuc4XVOxXggGDhTVSG7uXzGok4rm/dEtJhrQZcvdtbjwexe+S6zf95uIbJX46tG1751Rf5fsflY8CJje/JOeOtDrsc= ARC-Message-Signature: i=1; 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Fri, 29 Nov 2024 17:45:41 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-53df64a0742sm631946e87.261.2024.11.29.17.45.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Nov 2024 17:45:40 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 30 Nov 2024 03:44:43 +0200 Subject: [PATCH v2 31/31] arm64: dts: qcom: q[dr]u1000: move board clocks to qdu1000.dtsi file Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241130-fix-board-clocks-v2-31-b9a35858657e@linaro.org> References: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> In-Reply-To: <20241130-fix-board-clocks-v2-0-b9a35858657e@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Leo Yan , Joseph Gates , Georgi Djakov , Shawn Guo , Stephan Gerhold , Zac Crosby , =?utf-8?q?Bastian_K=C3=B6cher?= , Andy Gross , Jeremy McNicoll , Rohit Agarwal , Melody Olvera , Bhupesh Sharma , cros-qcom-dts-watchers@chromium.org, Stephen Boyd , Rajendra Nayak , Martin Botka , Jonathan Marek , Vinod Koul , Tengfei Fan , Fenglin Wu , Neil Armstrong , Abel Vesa , Alexandru Marc Serdeliuc , Vladimir Zapolskiy , Sibi Sankar , Bryan O'Donoghue , Jun Nie , James Willcox , Max Chen , Vincent Knecht , Benjamin Li , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2729; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=x2bm9LjU8gDnzSnTK9zY7r1UhakQ0COQvQ8bOcHGsI4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnSm33CNF2WLfr+WyfRFgu7ex2UM/+DSb3LnUtb LJomsgij+yJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ0pt9wAKCRCLPIo+Aiko 1VDcB/4v+V/Goy6Wzyd/paUJP74PVHkMTI8FJ7fNP21eqaQlNPPR9QGHNffiJlsz70VbOlVmzG6 VkTkPWJPxy1kUN5h8nqpLdVsV9IcNzzo0Wu0C0eKmN9N2Nfpo/Z4Yp+faKAV1VWP+V7fabcTbtl zqyvB2eoxajn0XUrze0pWdrZgr5ERMYce2VmfOnh7thb2zoqoiebZZ7IxFC2uhvZBQxBpzMgRgI YwNcq2mOC8rA6nCmYhU0ywTf4LBbsUbYwRPeM03PxuiMFPQxXTZ3Y4J9IoMqL8ywq8kooe8272r jGVhDHXLIqNbj0GNGc5xswRm/hh+bCMfl99O+wPMNcfi7fXo X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A The QDU1000 and QRU1000 devices define XO and clocks completely in the board files, despite qdu1000.dtsi file referencing them directly. Follow the example of other platforms and move clock definitions to the qdu1000.dtsi file. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 14 -------------- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/qru1000-idp.dts | 14 -------------- 3 files changed, 14 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index c73eda75faf8206181764df4d1ea32f96c9cfcd0..a36a56f03c2d112c6afdae1272b81edff890fca1 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -22,20 +22,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - clocks { - xo_board: xo-board-clk { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - ppvar_sys: ppvar-sys-regulator { compatible = "regulator-fixed"; regulator-name = "ppvar_sys"; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 47c0dd31aaf2e42d6d85411956207b2509a605b0..30fa8f5f992ff5b440db9871a254b60acddbac94 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -21,6 +21,20 @@ / { chosen: chosen { }; + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 52ce51e56e2fdc51c05fb637ed4b1922801ff94b..f35e3111f516ca1ab59011f8a4145d3e21e0a221 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -22,20 +22,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - clocks { - xo_board: xo-board-clk { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - clock-frequency = <32764>; - #clock-cells = <0>; - }; - }; - ppvar_sys: ppvar-sys-regulator { compatible = "regulator-fixed"; regulator-name = "ppvar_sys";