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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 01/54] fpu: handle raising Invalid for infzero in pick_nan_muladd Date: Mon, 2 Dec 2024 13:12:54 +0000 Message-Id: <20241202131347.498124-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org For IEEE fused multiply-add, the (0 * inf) + NaN case should raise Invalid for the multiplication of 0 by infinity. Currently we handle this in the per-architecture ifdef ladder in pickNaNMulAdd(). However, since this isn't really architecture specific we can hoist it up to the generic code. For the cases where the infzero test in pickNaNMulAdd was returning 2, we can delete the check entirely and allow the code to fall into the normal pick-a-NaN handling, because this will return 2 anyway (input 'c' being the only NaN in this case). For the cases where infzero was returning 3 to indicate "return the default NaN", we must retain that "return 3". For Arm, this looks like it might be a behaviour change because we used to set float_flag_invalid | float_flag_invalid_imz only if C is a quiet NaN. However, it is not, because Arm target code never looks at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we already raised float_flag_invalid via the "abc_mask & float_cmask_snan" check in pick_nan_muladd. For any target architecture using the "default implementation" at the bottom of the ifdef, this is a behaviour change but will be fixing a bug (where we failed to raise the Invalid exception for (0 * inf + QNaN). The architectures using the default case are: * hppa * i386 * sh4 * tricore The x86, Tricore and SH4 CPU architecture manuals are clear that this should have raised Invalid; HPPA is a bit vaguer but still seems clear enough. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 13 +++++++------ fpu/softfloat-specialize.c.inc | 29 +---------------------------- 2 files changed, 8 insertions(+), 34 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index cc6e06b9761..d63cd957a19 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -66,19 +66,20 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, int ab_mask, int abc_mask) { int which; + bool infzero = (ab_mask == float_cmask_infzero); if (unlikely(abc_mask & float_cmask_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, - ab_mask == float_cmask_infzero, s); + if (infzero) { + /* This is (0 * inf) + NaN or (inf * 0) + NaN */ + float_raise(float_flag_invalid | float_flag_invalid_imz, s); + } + + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); if (s->default_nan_mode || which == 3) { - /* - * Note that this check is after pickNaNMulAdd so that function - * has an opportunity to set the Invalid flag for infzero. - */ parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9bca03c4aed..c557c41b2af 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -480,7 +480,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * the default NaN */ if (infzero && is_qnan(c_cls)) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -507,7 +506,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * case sets InvalidOp and returns the default NaN */ if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } /* Prefer sNaN over qNaN, in the a, b, c order. */ @@ -529,10 +527,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -553,10 +547,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } + /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -576,10 +567,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * to return an input NaN if we have one (ie c) rather than generating * a default NaN */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB @@ -592,14 +579,9 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_RISCV) - /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - } return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); return 3; } @@ -617,11 +599,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } #elif defined(TARGET_SPARC) - /* For (inf,0,nan) return c. */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } /* Prefer SNaN over QNaN, order C, B, A. */ if (is_snan(c_cls)) { return 2; @@ -641,10 +618,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns * an input NaN if we have one (ie c). */ - if (infzero) { - float_raise(float_flag_invalid | float_flag_invalid_imz, status); - return 2; - } if (status->use_first_nan) { if (is_nan(a_cls)) { return 0; From patchwork Mon Dec 2 13:12:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D2B0D7831A for ; Mon, 2 Dec 2024 13:16:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6GI-00021C-A9; Mon, 02 Dec 2024 08:14:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6FR-0001k4-QY for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:13:59 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6FN-000369-Oq for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:13:56 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-434a9f2da82so36525585e9.2 for ; Mon, 02 Dec 2024 05:13:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145232; x=1733750032; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uI1GHeNAVBACaAOyrekRei9EE5yyDUO5Im1pzl3+9DM=; b=D5ei9pNmV7f8pzXMOmDq9lUhWciw8XltwFGlVWzD1liSNfwrQ5dtmoSBw/2uCp5t+h o4INDhFC3PFgMY7nQZbc7/3qla0543760H46P3jxQKA3P858nOkcpxDcYdErBkKwgqPv EIogSm4hJiUyRkCH3cnIqpzzvTX8tDcj44z6efJeDFJ++dfB1YH3FzPbATYDi3iN872C jle3Ne5Sa4lXQxhW6V1Fius+ba3+uj0IihYDoC3xL+MDChGfmK4yqegtiIm/rFjQ3p3W ueVWw67bdD5Z3gZZ44YofF/hBwQW72gcSxjWlS0BScWuGku5588SqCrto6EBegdHtsnr 7ngQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145232; x=1733750032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uI1GHeNAVBACaAOyrekRei9EE5yyDUO5Im1pzl3+9DM=; b=DSfSQZwRme5qxNKyXYZzyA0Fkqg9RvoJWpAjY/d5os909ptnhuOFTarWCspVktV3jH iIgE11Jjx17+8ndfEBvfkI941V7OwAHRRNRHQgwLPQIRifx0+CxA3UrD1u+3w5L0IP6t HlL7HenQXjuDaowUm2EOYNVf6oVeXp6HkoU0p5I5jbxDnSke8gjLnffL1I5TNk8o0OU3 mWL00bY7tFLtEMl6IxK8h9PSXowsVpnp42O6vf6xOKbojm3fge5n8/57v4uDjvsW1FRu +vrCVIykW/9KswACo99lGEr1hGR3hhtwIF/7IL7qv448b91QgcwBTLuHNUinfk3BfrqM Canw== X-Gm-Message-State: AOJu0YyY0I0LFxWRUCKG+stG//BSVD+pU3EMdXiWtCc97QE2R82/IJMY dv0g+zFx006Sm1jT62cVJWpKe7zjbfdX5UBqojZId9ZdLSZmFlxbARZ/WMDBFHS22eQJZl7Bja1 g X-Gm-Gg: ASbGncvR8AfhIUZe7VoVgH1VoPfWxajqbf4GhlVWTVQy8evXLZptLxfZnqse60HHxWN qRNMDRZvDHM0oHXLcU+bCQ3OeIVH5v1Kd251E49mivgJZvA4pbXr2Rbg936VfeVutHJKaVBjbvq Vrwtwc1063/v0w4xrUHOOw8TTlLffwzNRTT+eFdzhEyx1H4G2LAvuj+uSholjWokFOxfL3UdoaP 7Ua9s/ulFDdGT4lafsZIEz/sfqB9xtsde53ppLvX++O80Z76Z4hGnY= X-Google-Smtp-Source: AGHT+IE3HY3Zmx7VHI2U1o+7kzmrqBCN6P/KD891ThH3cDUW8P24XUquBX9h9pjzJ8Nvf6/yFJ2y/g== X-Received: by 2002:a05:600c:4fd6:b0:434:a781:f5d2 with SMTP id 5b1f17b1804b1-434a9db8483mr197860975e9.5.1733145232101; Mon, 02 Dec 2024 05:13:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 02/54] fpu: Check for default_nan_mode before calling pickNaNMulAdd Date: Mon, 2 Dec 2024 13:12:55 +0000 Message-Id: <20241202131347.498124-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org If the target sets default_nan_mode then we're always going to return the default NaN, and pickNaNMulAdd() no longer has any side effects. For consistency with pickNaN(), check for default_nan_mode before calling pickNaNMulAdd(). When we convert pickNaNMulAdd() to allow runtime selection of the NaN propagation rule, this means we won't have to make the targets which use default_nan_mode also set a propagation rule. Since RiscV always uses default_nan_mode, this allows us to remove its ifdef case from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 8 ++++++-- fpu/softfloat-specialize.c.inc | 9 +++++++-- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index d63cd957a19..aac1f9cd28c 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -77,9 +77,13 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, float_raise(float_flag_invalid | float_flag_invalid_imz, s); } - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + if (s->default_nan_mode) { + which = 3; + } else { + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + } - if (s->default_nan_mode || which == 3) { + if (which == 3) { parts_default_nan(a, s); return a; } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c557c41b2af..81a67eb67b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,13 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + /* + * We guarantee not to require the target to tell us how to + * pick a NaN if we're always returning the default NaN. + * But if we're not in default-NaN mode then the target must + * specify. + */ + assert(!status->default_nan_mode); #if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN @@ -578,8 +585,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { return 1; } -#elif defined(TARGET_RISCV) - return 3; /* default NaN */ #elif defined(TARGET_S390X) if (infzero) { return 3; From patchwork Mon Dec 2 13:12:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9AC41D7831B for ; Mon, 2 Dec 2024 13:15:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6GL-00024H-Br; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 03/54] softfloat: Allow runtime choice of inf * 0 + NaN result Date: Mon, 2 Dec 2024 13:12:56 +0000 Message-Id: <20241202131347.498124-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IEEE 758 does not define a fixed rule for what NaN to return in the case of a fused multiply-add of inf * 0 + NaN. Different architectures thus do different things: * some return the default NaN * some return the input NaN * Arm returns the default NaN if the input NaN is quiet, and the input NaN if it is signalling We want to make this logic be runtime selected rather than hardcoded into the binary, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. Note that four architectures both use the muladd softfloat functions and did not have a branch of the ifdef ladder to specify their behaviour (and so were ending up with the "default" case, probably wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set default_nan_mode, and so will never get into pickNaNMulAdd(). For HPPA and i386 we retain the same behaviour as the old default-case, which is to not ever return the default NaN. This might not be correct but it is not a behaviour change. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: float_infzeronan_dnan_never shouldn't be the same value as float_infzeronan_none --- include/fpu/softfloat-helpers.h | 11 ++++ include/fpu/softfloat-types.h | 23 +++++++++ fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++----------- 3 files changed, 95 insertions(+), 30 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 453188de70b..0bf44dc6087 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, + float_status *status) +{ + status->float_infzeronan_rule = rule; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -137,6 +143,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) +{ + return status->float_infzeronan_rule; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 8f39691dfd0..47bb22c4e25 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -207,6 +207,28 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * Rule for result of fused multiply-add 0 * Inf + NaN. + * This must be a NaN, but implementations differ on whether this + * is the input NaN or the default NaN. + * + * You don't need to set this if default_nan_mode is enabled. + * When not in default-NaN mode, it is an error for the target + * not to set the rule in float_status if it uses muladd, and we + * will assert if we need to handle an input NaN and no rule was + * selected. + */ +typedef enum __attribute__((__packed__)) { + /* No propagation rule specified */ + float_infzeronan_none = 0, + /* Result is never the default NaN (so always the input NaN) */ + float_infzeronan_dnan_never, + /* Result is always the default NaN */ + float_infzeronan_dnan_always, + /* Result is the default NaN if the input NaN is quiet */ + float_infzeronan_dnan_if_qnan, +} FloatInfZeroNaNRule; + /* * Floating Point Status. Individual architectures may maintain * several versions of float_status for different functions. The @@ -219,6 +241,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ bool flush_to_zero; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 81a67eb67b5..f5b422e07b5 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,8 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { + FloatInfZeroNaNRule rule = status->float_infzeronan_rule; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -482,14 +484,68 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * specify. */ assert(!status->default_nan_mode); + + if (rule == float_infzeronan_none) { + /* + * Temporarily fall back to ifdef ladder + */ #if defined(TARGET_ARM) - /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns - * the default NaN - */ - if (infzero && is_qnan(c_cls)) { - return 3; + /* + * For ARM, the (inf,zero,qnan) case returns the default NaN, + * but (inf,zero,snan) returns the input NaN. + */ + rule = float_infzeronan_dnan_if_qnan; +#elif defined(TARGET_MIPS) + if (snan_bit_is_one(status)) { + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN + */ + rule = float_infzeronan_dnan_always; + } else { + /* + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + rule = float_infzeronan_dnan_never; + } +#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ + defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ + defined(TARGET_I386) || defined(TARGET_LOONGARCH) + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + rule = float_infzeronan_dnan_never; +#elif defined(TARGET_S390X) + rule = float_infzeronan_dnan_always; +#endif } + if (infzero) { + /* + * Inf * 0 + NaN -- some implementations return the default NaN here, + * and some return the input NaN. + */ + switch (rule) { + case float_infzeronan_dnan_never: + return 2; + case float_infzeronan_dnan_always: + return 3; + case float_infzeronan_dnan_if_qnan: + return is_qnan(c_cls) ? 3 : 2; + default: + g_assert_not_reached(); + } + } + +#if defined(TARGET_ARM) + /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ @@ -508,13 +564,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } #elif defined(TARGET_MIPS) if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - if (infzero) { - return 3; - } /* Prefer sNaN over qNaN, in the a, b, c order. */ if (is_snan(a_cls)) { return 0; @@ -530,10 +579,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 2; } } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -550,11 +595,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } #elif defined(TARGET_LOONGARCH64) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - /* Prefer sNaN over qNaN, in the c, a, b order. */ if (is_snan(c_cls)) { return 2; @@ -570,11 +610,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, return 1; } #elif defined(TARGET_PPC) - /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 04/54] tests/fp: Explicitly set inf-zero-nan rule Date: Mon, 2 Dec 2024 13:12:57 +0000 Message-Id: <20241202131347.498124-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Explicitly set a rule in the softfloat tests for the inf-zero-nan muladd special case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_infzeronan_dnan_if_qnan. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- tests/fp/fp-bench.c | 5 +++++ tests/fp/fp-test.c | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 75c07d5d1f1..fde64836194 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -488,7 +488,12 @@ static void run_bench(void) { bench_func_t f; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 5f6f25c8821..251c278ede9 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -935,7 +935,12 @@ void run_test(void) { unsigned int i; + /* + * These implementation-defined choices for various things IEEE + * doesn't specify match those used by the Arm architecture. + */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); verCases_maxErrorCount = n_max_errors; From patchwork Mon Dec 2 13:12:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C671CD7831A for ; Mon, 2 Dec 2024 13:17:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6IC-00045T-Qx; Mon, 02 Dec 2024 08:16:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Fv-0001nn-Ja for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:32 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6FT-00038X-P7 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:04 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-385e1fcb0e1so1178672f8f.2 for ; Mon, 02 Dec 2024 05:13:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145237; x=1733750037; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X86TKVmBDvN75raroOS5cqB5k378L/9aSAueAeunYPY=; b=xSTlkBXm0qr+JsuVwvnOKeMTwIvKiGUoF4Y98fLU/Am7p5w/vXO9XQpwj7D5KoEUOW yRs1TE3/rf0UHbCuh9gUg2XaAbm9l8VOTnL6wRYlmM4HqjzbOYeM8pumpfQduqNt2CVo EjmcaZGzO9golB5tBlhP16xQcfef2DFKPejDzOOhr1rKmQMvGrQUU+ng64n1ZU36oo2v QjR9XVoXKpG5XgfRilUdlkevRh1RQmoI62k3s1RKrJkdaMCgURukjK1qigNakLCVpneg l65LyXzI9LDYjEd+llFSsE2InqFpUI19lJ10P4ZBFFkQ9YhA3J2ID9DCgLBubuNNr5gQ TXdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145237; x=1733750037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X86TKVmBDvN75raroOS5cqB5k378L/9aSAueAeunYPY=; b=FRuFAwU6Vna698l3lNu9bjsXRga6l/zw9DfpFL4+s9BRB6y4H+js9rXE3zhO9qztQV dSPLgGAeSKw4ikKpSJI1pmOU/FuBdxHUor6ZPbR1MqS5TnqVCoGdi1VQzaWtFkfXdCCE 5tSTABpUvO+j8apIZXnwf3wkVCpr2caAKZGNOJmRV5GYQnpFPzkIap74Tgk2j/8nxX4c 4KE2/NRnxSI6LAnen3U2DwNOKi6FVXHVYzWNYDoU5cK5bRsiFsjDO/cpHnVwb3ed322t uWOx4ZGQsDUz9Hvm6SYZOlAjnF5nBQ00QsSaGiVQzRga4BrTbZDCKJjx6uiaxylsjFgE l6uQ== X-Gm-Message-State: AOJu0YxwZFmPedMJa86lTCe8XU3D7PUk1IwVlmJENVjAk+I6tFO0DP1M gHZnDwtjDvxZvszl0wJCC6bsuCKtyXx9HnsyxA8TKp/TIxuxsQlAYpAjRCWOJvRgTMElomxXkPK T X-Gm-Gg: ASbGnctkwdYNaBs+aZL/NJkoZjgZKuLz5yjlp8Awa/eh/O0g/7CVySDnWf3QG+l4CYr Yzmu/qmcvY/RTkzTbzFVahQTULZhjFd2IOI3kXCXni7BHxmPv/Pndr6aE0iWDwGu+1e+P15a5aK HeJ/DIDkXg5XAwBfB5e1Q1b2ytjWv5aeYmF1bAbKqyLlWJ/K2T7JImoSFjeaxe0p3+E2nyfcu9K bcmIILfZ8WzEIXnTgU5fzIhtaC15ArmIxzutGwhvA4E6mubvkrlVhY= X-Google-Smtp-Source: AGHT+IFdQQWgR/bNLUdTgu3F5FTRNJTdAqhmVVBqbLbMiui/GUGucj15DDJzu/49uD8zVv4Y52wGZQ== X-Received: by 2002:a5d:47af:0:b0:385:ef39:6cd5 with SMTP id ffacd0b85a97d-385ef396e98mr4114344f8f.1.1733145236576; Mon, 02 Dec 2024 05:13:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 05/54] target/arm: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:12:58 +0000 Message-Id: <20241202131347.498124-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..ead39793985 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,11 +173,14 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, + * and the input NaN if it is signalling */ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f5b422e07b5..b3ffa54f368 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,13 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_ARM) - /* - * For ARM, the (inf,zero,qnan) case returns the default NaN, - * but (inf,zero,snan) returns the input NaN. - */ - rule = float_infzeronan_dnan_if_qnan; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { /* * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) From patchwork Mon Dec 2 13:12:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 160C8D7831E for ; Mon, 2 Dec 2024 13:24:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6OF-0002Po-4M; Mon, 02 Dec 2024 08:23:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gb-0002Kx-8l for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 06/54] target/s390: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:12:59 +0000 Message-Id: <20241202131347.498124-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for s390, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 514c70f3010..d5941b5b9df 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_infzeronan_rule(float_infzeronan_dnan_always, + &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b3ffa54f368..db914ddbb1c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -516,8 +516,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * a default NaN */ rule = float_infzeronan_dnan_never; -#elif defined(TARGET_S390X) - rule = float_infzeronan_dnan_always; #endif } From patchwork Mon Dec 2 13:13:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890610 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C0453D7831B for ; Mon, 2 Dec 2024 13:16:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Ha-0003Yb-Le; Mon, 02 Dec 2024 08:16:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Fw-0001nq-KX for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:32 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6Fn-0003Af-2p for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:24 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-385e5db74d3so1326535f8f.0 for ; Mon, 02 Dec 2024 05:14:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145240; x=1733750040; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HfpQEPdfErqnjNX6r5VLZdc7V0ZgOPNgi8c10TCw4Tg=; b=X7A1roEwuJIJdXCeDNcZiuaX3BjjFszTFtIWYu5CI5OnZdMgHlVyKcFhqP0kn9kEzo AfF6PNmqtYATLIn7ggUJJsS6zaxqgKn5KV+J42h7JBuy/YN34QIiHm49+3yKWalHNfNM GExd7hkWKjzRpcB4IG9PLIHy5GbLH+gm5yKdCSQ+Zwn4aedX+qnScFJ2aZ6qpmP3gTwa ItSMfKRCZ2hFevyfIov0Dh3RnNnlT/e+NsoSZFm3nDn3w30JW60v9THe36UID3pkSXoz o2tCKGthsNTqRDcy8G4NAsd1PdIc+V0vNtECjgBgfezgPE10o/6fDVapCNGBYEtvj3G1 NAgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145240; x=1733750040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HfpQEPdfErqnjNX6r5VLZdc7V0ZgOPNgi8c10TCw4Tg=; b=bRYTCTW2rRJs4KWWLylwr2NPbt/oEoMVZ9G2APFfdKDfKyV5ObK//AVZxMiEwtZGF0 wlQ3U7I/xecQdCkA5VJp1vDbRu6jhOKIywWfggxIckGTtn72RNbXedVbpmBVmNPG7twP fpq5/fvEKQBFNQOd4JK9YHa6tuL2pi7cmYo9K2KG9H1mWiHrb5OldWXJx3v40AkVYJvT SJjtojoG6k+nyDSgEf9aF1LXwSPNZBe7ceLGwlIpyhrb8bTPMPSkzXmjXodU/pxAJO+i C5/wEYOCBXaC+4vcky3PDD+rOs1PK0xEQT7yt5jCESpMSo/kWsg4yEjSmn6STfuv2wGz 72Tg== X-Gm-Message-State: AOJu0Yw5EQ52fsTm0vEmLhi7J1bH/6GHQ688Onf3mkEnbzUsK2fjfNol ve3oK8eXvLYsnxbGkArjLX9tzTsHUhm6E8kjHYqOzqa1MZEeYwnwK6Zd/1mJ87KOBtMzXrvaJOR K X-Gm-Gg: ASbGncuncpEk/Ra7RWpwvXWDDVDs+oTDEtJWLZaXwUma42i4xEbNaPxku6Dvt2LdyrP du8bttSDXpmBGOHl8OZl43iyFfZwm04vXa0zRWo5g9H+NHTkJDqQbDUdARMUG33BV+PRz6/1Mhw CX0/+XdzHmEfw9Hz8aGrnqnOU8zktFZh0pCU/06uwJF5IiS0mY1M4Eo4xA3JqJfBQb2bHh0prcg DiTrP9447cA6DzVg7QSfp38ekjYml22J34RMZ1lsBkCWgRVeIStqnc= X-Google-Smtp-Source: AGHT+IH1SwiyqgNnO1jb8Mg4+qV0wNNNfAhUqYCw2B1qbD7zW+iE5bOTeMcRWbkK/6Xj+0nABql66Q== X-Received: by 2002:a05:6000:184e:b0:382:6f2:df7a with SMTP id ffacd0b85a97d-385c6ec117emr19208264f8f.34.1733145238862; Mon, 02 Dec 2024 05:13:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 07/54] target/ppc: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:00 +0000 Message-Id: <20241202131347.498124-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the PPC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c25..f18908a643a 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,13 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer + * to return an input NaN if we have one (ie c) rather than generating + * a default NaN + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db914ddbb1c..2023b2bd632 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -503,18 +503,13 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ rule = float_infzeronan_dnan_never; } -#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \ +#elif defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' */ - /* - * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer - * to return an input NaN if we have one (ie c) rather than generating - * a default NaN - */ rule = float_infzeronan_dnan_never; #endif } From patchwork Mon Dec 2 13:13:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22342D78323 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.13.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:13:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 08/54] target/mips: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:01 +0000 Message-Id: <20241202131347.498124-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the MIPS target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 9 +++++++++ target/mips/msa.c | 4 ++++ fpu/softfloat-specialize.c.inc | 16 +--------------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 7c3c7897b45..be66f2f813a 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -28,6 +28,7 @@ static inline void restore_flush_mode(CPUMIPSState *env) static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); + FloatInfZeroNaNRule izn_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -35,6 +36,14 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); + /* + * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) + * case sets InvalidOp and returns the default NaN. + * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c'. + */ + izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; + set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index 9dffc428f5c..cc152db27f9 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -74,4 +74,8 @@ void msa_reset(CPUMIPSState *env) /* set proper signanling bit meaning ("1" means "quiet") */ set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + + /* Inf * 0 + NaN returns the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, + &env->active_tc.msa_fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 2023b2bd632..db9a466e05b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,21 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* - * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) - * case sets InvalidOp and returns the default NaN - */ - rule = float_infzeronan_dnan_always; - } else { - /* - * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ - rule = float_infzeronan_dnan_never; - } -#elif defined(TARGET_SPARC) || \ +#if defined(TARGET_SPARC) || \ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* From patchwork Mon Dec 2 13:13:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AF61D78321 for ; Mon, 2 Dec 2024 13:46:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Ud-0001wM-Dq; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 09/54] target/sparc: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:02 +0000 Message-Id: <20241202131347.498124-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de73..61f2d3fbf23 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index db9a466e05b..7e57e85348b 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,8 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_SPARC) || \ - defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Mon Dec 2 13:13:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 68E16D78322 for ; Mon, 2 Dec 2024 13:45:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Yd-0001Ak-Ck; Mon, 02 Dec 2024 08:33:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6HB-0003Iu-Cg for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:49 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GZ-0003CZ-1r for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:38 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-434acf1f9abso38904465e9.2 for ; Mon, 02 Dec 2024 05:14:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145249; x=1733750049; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uAvUlUwIT6mon/4ZVWSLpgO6VDhWersS5LUlGU6M2Ag=; b=hRopcZuPcswnNGhkXpoSRR8R5Y3zE99SgaCXyQGfyZWKsSOiPjWu1mMXz89sHoy/6G JTa9SEPc+rQLp8fQJ3aNp5pm5nCpVWPbyLht7HCAPG6WEr1OssdGWRPOun7Uqnbdi5wO WyuYdoomVrgBGp/iMi0DR3Eq2+E5G5LQVMHS8kecF5lVt4zCJtbX0EEqC9ZfSijWy+c4 5+tpxbC/yhiSDf7uKHkJwT5vj7U4qgSVdZVkpqaEToskNJmrXIq1bcQGei5wxxyxXt1B 6rFa6k9Sei0ktXJk25ufIzQVIiED03PRXKqacqFGKBuuD2q/5eF5HBaH9aBTJ4vmJ7An C3iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145249; x=1733750049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uAvUlUwIT6mon/4ZVWSLpgO6VDhWersS5LUlGU6M2Ag=; b=juuxeZHHRHrh9m8xfdART51JfopRtpAK01y5ooe/v7N6O2ftZibrtgtolqFTrc6vON uM3EpjEha7UHCV96Cbk+NSHunkspTZyAAg6AfIbcBnhJmnu+mS2t0LfmPkhCpNEg06uc uQSl5gM7fMSv+xLECDv8+T4obhKvbsLabtGDOQ/GvBs1IckV7Dusd74FcBQvO8O26hks TCwVlY6GsSlLefr8KXUl4CgNMl3tEFMhMolrZKAE46WWTj9H9f/ChKNa+RJLpQ5FUjb4 kbfNcI2PJmq3bgaNigIO9Aedez8dbVpucZ2dnnlIxIg/u8jhgQY1nLw1bqr2YOVt2GeY 7iEw== X-Gm-Message-State: AOJu0YybnCTuv3lKw1uncPub9R62XdVhQNmnDEWnBw7z193gD10Aq+UX q1SScs8DhXnn24xVc3f/j7gjlGWyHD/eFVkLehqEcETZmdhAI8dXXvng7IJDYDFQJgNMla+b6jO m X-Gm-Gg: ASbGncuxTHQ0xkaQsTGxGlXOeW4/Qkz9G3mHb6HDTud24bDKtNnyxrlmtxD4Z+ZkJ5/ 23UEay804Hdy5Psrmokri+bLDHy3m9p8lEqKk/uoK+v9lfxRsOHBr4BhrX9QDolYSVEO6xqyF0C mu8IbDTaPEUjMo1vWHn0q5t+9p2AaYbfOf/wHezjGidCDqORbuZR+mu7qza5j9zEIksRdB3m2Hb Cba2In3V81TNxKs8njpJEa2jby6GJXZJdtEFj9fD6ZC9bMmk4+wOBY= X-Google-Smtp-Source: AGHT+IE5iv5s3mrYdQc2+fXd2f07qSrhY020mcYzc/+Y1BJ5GlK97WEz6OPBovtSk3AryeNH6ag8Ug== X-Received: by 2002:a05:6000:4710:b0:385:e013:73f0 with SMTP id ffacd0b85a97d-385e0137516mr12146642f8f.59.1733145248867; Mon, 02 Dec 2024 05:14:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 10/54] target/xtensa: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:03 +0000 Message-Id: <20241202131347.498124-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the xtensa target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6f9039abaee..3163b758235 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -133,6 +133,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) reset_mmu(env); cs->halted = env->runstall; #endif + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 7e57e85348b..3062d19402d 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,7 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \ +#if defined(TARGET_HPPA) || \ defined(TARGET_I386) || defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) From patchwork Mon Dec 2 13:13:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890630 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74FC2D7831B for ; Mon, 2 Dec 2024 13:28:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6N3-0000sA-Gh; Mon, 02 Dec 2024 08:21:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GR-0002GW-Fe for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:02 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GL-0003Cq-9o for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:58 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385d6e36de7so3706040f8f.0 for ; Mon, 02 Dec 2024 05:14:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145250; x=1733750050; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iLWBUHvjOah3un3/57/rPBpB/Wh0uSx2UDmLN935xs0=; b=Z+s9kM6o4IBZk836N4o9ecJvAypQIOlWG/105jsJUpLKV1Rld8ejoM+QtqvDoeICts Y9H7IJi/6EZ+YAXOj52YJyO+2FInYs2FmAEbhvkgAyX/toedAbAWbiCC6O8gRk6ps4EU wYggH4FXSoVpTSHEF18RnWTvuO1E87o/e8X2VI3nTeEo4G31Q43//pWQrSDkb2jVqDWe qdLQsDmYe1rNiRbMtyQTVig6lrvDZNpDWgpoZ5e9vMTQPDXUF+gafPeGLb06/ENAA0FY //w9SypIbO0TtODNr0mK5qK4kUqKKPtgjhvwT/66qBjy7wlZ8T+TticMXAFvUj8Q0t60 kSOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145250; x=1733750050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iLWBUHvjOah3un3/57/rPBpB/Wh0uSx2UDmLN935xs0=; b=Szn1mckTmFb0mvkipwVrE0CJaqFROJ0NLTI/Q3YHz79cit3zjlB/k8UL4Z3Sf9rSap DYbZho2AFTYofxJ0BuYF7CzUQiL8DtuoXeNIp8oTGZ5xJ/6v3FH2E9SYuRGVnl/alzL6 9JU2R1E1D34H7C1rjkLxBwzsAW49/9Pd5hjUIt0S60cEEvSMXOHC8iw7ijOXWyionLC4 p4mX/D3ulpBx/gm1eElgasI4ekq7mBxryyy/SXNRVVgz4XAWMBxR5eS3xLANprUGrzlw kuaWDW47d/3QR7+Yg9Xvj6OSssJTe4cvDbaCDKd2qdoKFlzYKd+AGw8RuFcCNIX5xuCC KZCQ== X-Gm-Message-State: AOJu0YxUBzCZAcM7c23kgI4WOurp4MDE8vMqiHe3EAPfTCrR9ixegbKV iGSs8TVTM0vHN/EdnauGtgDrcYV3Rf5JBghxBR4gJLZFnvz87qjGXfiETWDJmMEaOnQom6/wJSY B X-Gm-Gg: ASbGncuMBujYvhxbv/Qjr6m2++WgtwIYgCyBrDwEQQR+A3yViF3hpa45MYOBaU+RjI5 cHUmXWQJa84KO9BESD7rLSgGQOTToam80bVl1BwzmyNmKkdEEhMW3PKKuxH9W7wheDUXMT9f+Wo YfTNob/2mGSE+uzLOaMb2m/G0GZW6SguAA4U78M74Tu4O+8D2/llFWYzF77+SrAjHeEsP3xJMZx kPW7lnQd4slY205M6ffvcU4GeDeN8QSFb+yXp1vyMM8LGh3UIPJcD4= X-Google-Smtp-Source: AGHT+IF0Hwpzg6dNKKvHLMYzIyDSn83uORY7RarpqFUSX/f91/tb9XChu0z+5QbApuX4pt02PA7YMw== X-Received: by 2002:a5d:6f12:0:b0:385:f996:1b8e with SMTP id ffacd0b85a97d-385f9961e8emr1313251f8f.16.1733145250043; Mon, 02 Dec 2024 05:14:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 11/54] target/x86: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:04 +0000 Message-Id: <20241202131347.498124-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: Update the comment to give the info from the x86 spec rather than a TODO comment saying we need to check it... --- target/i386/tcg/fpu_helper.c | 7 +++++++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb2977..a98b4f67ff0 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status); set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status); + /* + * Only SSE has multiply-add instructions. In the SDM Section 14.5.2 + * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is + * specified -- for 0 * inf + NaN the input NaN is selected, and if + * there are multiple input NaNs athey are selected in the order a, b, c. + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3062d19402d..ad4f7096d09 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, * Temporarily fall back to ifdef ladder */ #if defined(TARGET_HPPA) || \ - defined(TARGET_I386) || defined(TARGET_LOONGARCH) + defined(TARGET_LOONGARCH) /* * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) * case sets InvalidOp and returns the input value 'c' From patchwork Mon Dec 2 13:13:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890632 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60DAAD7831F for ; Mon, 2 Dec 2024 13:28:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Sh-0006eH-7C; Mon, 02 Dec 2024 08:27:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GV-0002Ht-5K for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:07 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GL-0003DH-Dy for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:01 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385e27c75f4so1479620f8f.2 for ; Mon, 02 Dec 2024 05:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145251; x=1733750051; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hfWcIGFElRwNWX99Qr3KLu7RlocWXtaK9gnVDhRhWYA=; b=rYQ36UQvq20BFoIwyg6hoYkYGV8DeYO09OMqwHm8ugzvZa+nEmEIBID3q/LizzDC/w 4gd/zq2lCO0KOfhCDU0cc0F1GTHbL4kemj877E8buveriIBx6wfyFd+HJrBkIt26KWC9 O4LVUwDblY9DH446hR9UnHbKMmjrFXpX65whF9DimMD5kFErOUjDd/3REnTvrzuyg6i1 M4SJjUWn4IwP44HQ+pTeLtyIvwbKjxSqDD5BCYPipW8L5ldYobnhbQS0+ooEzPK16ZGP eVfksAbkapwhlkIE/wq+pFaQqBWOvb3CMUUcDUES9VumGyuq/3sjCcV3WYU3cZc5ugVX aoNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145251; x=1733750051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hfWcIGFElRwNWX99Qr3KLu7RlocWXtaK9gnVDhRhWYA=; b=g3wOjQ0a+qPWv6aO35/02+8+TxCQz9nILylKw1PHVZA66/SpfIx42ipBWHM6wDXPMl GLDdWQPWeCW6UJ7gJ6EPuTx145lNeSbbcctx7MuWKaPFlCVH4ezroOnINQ6NMpOPQ0Xy NCBcsgQ5LqbCsnc6XOg78EZhun2menNq0BBBITPi6q/A/uLVO1BJceZZTYxJTx7jif0b 1E5obqZNnH5csrVy68vwvYmnqZ4vGVsuKl6w4akbvLr5ZWO96vksSfegkfOfR6lZ4k1p FgyTsd6rDvvGWeG9rZizNbUjnmkG5dEG+EtzkLYY6pLBgAIul/WBHUoV82Y1+Pzhv60y YfAA== X-Gm-Message-State: AOJu0Yy2KvUJbIyNAK3X9Pj4F0rAkao1kDwjobDmuSK+BnI0KwyGLOES f/lDOXVSIrQ/QRROx3oe1oQrN6P6PU257Jefu5ZXhjvtJhozdPJYEujveSPnE05UfP9dHScsUgV 0 X-Gm-Gg: ASbGncuek4A+gOBgaRBjeRjgUGZ0mjsjiWNKciHgHL1IpH4aG91R597JMX/uKMsOFek gvPNDsCCvDLkY1Nsrxkl5mnMQEV5TTvyr49kYS3ZQ+uTUVjGkLPHcXUZKX+2B1dCgbBjdS5jot5 JVw3ShCx/X40AXxf53ZmISAfBpFKgKCkj4mMfRY3V5nRQInKXZ5NPZcqoVNzvWflMsJovgZjOnN J7mNoVkRR4OJNZpWmTmn/WI1lTbLkpzFCDWzI5MlEIeBJDTm8cywYU= X-Google-Smtp-Source: AGHT+IFl5ZKDcFMgGIc5LeK51D4mmt2uCTorCPud1MxCTo9j54Y0ZSTaNWqE25haKOFhN7LIYZOF9w== X-Received: by 2002:a5d:6485:0:b0:385:e176:4420 with SMTP id ffacd0b85a97d-385e1764637mr9309692f8f.10.1733145251088; Mon, 02 Dec 2024 05:14:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 12/54] target/loongarch: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:05 +0000 Message-Id: <20241202131347.498124-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 5 +++++ fpu/softfloat-specialize.c.inc | 7 +------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 21bc3b04a96..6a2c4b5b1db 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -32,6 +32,11 @@ void restore_fp_status(CPULoongArchState *env) &env->fp_status); set_flush_to_zero(0, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) + * case sets InvalidOp and returns the input value 'c' + */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ad4f7096d09..05dec2fcb4c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,12 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_HPPA) || \ - defined(TARGET_LOONGARCH) - /* - * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan) - * case sets InvalidOp and returns the input value 'c' - */ +#if defined(TARGET_HPPA) rule = float_infzeronan_dnan_never; #endif } From patchwork Mon Dec 2 13:13:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B0B0D7831B for ; Mon, 2 Dec 2024 13:17:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6IO-0004ka-0J; Mon, 02 Dec 2024 08:17:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6G0-0001p7-MG for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:35 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6Fs-0003Df-Hc for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:28 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4349fb56260so36520205e9.3 for ; Mon, 02 Dec 2024 05:14:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145252; x=1733750052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r8XgmjddIhM612jj3JENDu5XxtMOP1j+6PXpvtg3rDM=; b=uoX88bBcq9kEFizw5H8wDZ6CehpaAS3bTR+Lht6sps3Rt6IDxBkdL3l544fcK+hpKu e/k6UlhfNe1zlEHryRoweUclPn1CxVPezbi7QlCJUjEtml9VzkZtg0LSzKu7/CyBs16b 52J6V0/XS8tMlnczkQWuHW4NiaDuSuYr4o3unpHMxh8FP8x8fmKRLVrJKA0aI0VKiEQg BxPJNsNXHtNkzPhhz9JrdpQXPQxd6COvTvn7CTEVB3D1AtduK4eZI9YgaTUfSoXj2Ifw w+MFrV3BVHaRdwyYPMWT94WZk8PIydcdQZI4Uq17ceAlORbFWgbwIk8uasknKFpiW/K+ 23jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145252; x=1733750052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8XgmjddIhM612jj3JENDu5XxtMOP1j+6PXpvtg3rDM=; b=ZCQSOGSnc7YGXLd7DW3OqNLiOeYI8Npn9rGqmlTLs/2ehTXpjLcj0qdoavjt26mIaa 1BEyr4ERidzC8m0BHzCMnq5WJwqUem7lIQbyqZeIW7fIkVfa6G/NIvxT8l1UWTnVDNDY eChFWrX1mWpWe9/JpWj+XTwO6Q2oyFx5JXkhSXd0HjkpwCoG0CIXjj91f2uLNWR/3qYU wIEHKTCkXZywzWYx9GUWk9pP4xtxbL82Cdd0vQzTqhqlRVXe6wwFc7RlCN2GaOjTbGP6 Pl9OShs6DETh03GHFZIcRi5qQJ6sdLF362b7FcZlBGi4YkbdQtR2zqbKqjIO1igLojKY S5QA== X-Gm-Message-State: AOJu0Yyt5P8NgvkGS/x/6GBOdy2fFpNbzV8+xxfr8MTldicvkRwpK2BM WAJ28AGdnHxhQax6OeJINVaDnXHMEiHzQmftXs+rl6Z1JdQGDG2H56PqQjgmrXi4bPHelpQJq9q U X-Gm-Gg: ASbGnctZBFD6hovNpLrGwLFJh45ctA7+CxpDqJLEw7kmwuS0viDAPfd7ANsOX12WFHK EiLxt0VPvCzBJ37QeIFnNk7YtUDz7CpnhQ3HkjOM1nh1ZDeZexdHnkMvKzh6nfYcCh9oKAk0iuR Q+neuU/Qf4gA2hLN990Aatt+3Gky+ZkhrawlDCUQixUb/fV+f44CX6RMHQxZGU2d8tnncDibLpB U5TPLmjAtq29rjcZFv2DcOla/BzlW6cuVCt1cy5uxbUorZZYOZN9Ps= X-Google-Smtp-Source: AGHT+IFGAqP9oBoobvwRTVsxyHV68P3Uq4eNLluzGyHDJ84r6ieo+CCHSPp2emlfRlyYJlsQ5T8PFA== X-Received: by 2002:a05:6000:1fac:b0:382:49f9:74bb with SMTP id ffacd0b85a97d-385c6ebaecbmr21012001f8f.35.1733145252416; Mon, 02 Dec 2024 05:14:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 13/54] target/hppa: Set FloatInfZeroNaNRule explicitly Date: Mon, 2 Dec 2024 13:13:06 +0000 Message-Id: <20241202131347.498124-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 13 +------------ 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 0e44074ba82..393cae33bf9 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* For inf * 0 + NaN, return the input NaN */ + set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 05dec2fcb4c..3e4ec938b25 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,8 +475,6 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, float_status *status) { - FloatInfZeroNaNRule rule = status->float_infzeronan_rule; - /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -485,21 +483,12 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, */ assert(!status->default_nan_mode); - if (rule == float_infzeronan_none) { - /* - * Temporarily fall back to ifdef ladder - */ -#if defined(TARGET_HPPA) - rule = float_infzeronan_dnan_never; -#endif - } - if (infzero) { /* * Inf * 0 + NaN -- some implementations return the default NaN here, * and some return the input NaN. */ - switch (rule) { + switch (status->float_infzeronan_rule) { case float_infzeronan_dnan_never: return 2; case float_infzeronan_dnan_always: From patchwork Mon Dec 2 13:13:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890617 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADE47D7831A for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 14/54] softfloat: Pass have_snan to pickNaNMulAdd Date: Mon, 2 Dec 2024 13:13:07 +0000 Message-Id: <20241202131347.498124-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The new implementation of pickNaNMulAdd() will find it convenient to know whether at least one of the three arguments to the muladd was a signaling NaN. We already calculate that in the caller, so pass it in as a new bool have_snan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-parts.c.inc | 5 +++-- fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index aac1f9cd28c..655b7d9da51 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -67,8 +67,9 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, { int which; bool infzero = (ab_mask == float_cmask_infzero); + bool have_snan = (abc_mask & float_cmask_snan); - if (unlikely(abc_mask & float_cmask_snan)) { + if (unlikely(have_snan)) { float_raise(float_flag_invalid | float_flag_invalid_snan, s); } @@ -80,7 +81,7 @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b, if (s->default_nan_mode) { which = 3; } else { - which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s); + which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s); } if (which == 3) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3e4ec938b25..a769c71f545 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -473,7 +473,7 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, - bool infzero, float_status *status) + bool infzero, bool have_snan, float_status *status) { /* * We guarantee not to require the target to tell us how to From patchwork Mon Dec 2 13:13:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 674EDD78322 for ; Mon, 2 Dec 2024 13:40:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6WE-0005SO-2E; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 15/54] softfloat: Allow runtime choice of NaN propagation for muladd Date: Mon, 2 Dec 2024 13:13:08 +0000 Message-Id: <20241202131347.498124-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 3-operand fused multiply-add operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the binary because pickNaNMulAdd() has an ifdef ladder for different targets. We want to make the propagation rule instead be selectable at runtime, because: * this will let us have multiple targets in one QEMU binary * the Arm FEAT_AFP architectural feature includes letting the guest select a NaN propagation rule at runtime In this commit we add an enum for the propagation rule, the field in float_status, and the corresponding getters and setters. We change pickNaNMulAdd to honour this, but because all targets still leave this field at its default 0 value, the fallback logic will pick the rule type with the old ifdef ladder. It's valid not to set a propagation rule if default_nan_mode is enabled, because in that case there's no need to pick a NaN; all the callers of pickNaNMulAdd() catch this case and skip calling it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 11 +++ include/fpu/softfloat-types.h | 55 +++++++++++ fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------ 3 files changed, 107 insertions(+), 126 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 0bf44dc6087..cf06b4e16bf 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -81,6 +81,12 @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule, status->float_2nan_prop_rule = rule; } +static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule, + float_status *status) +{ + status->float_3nan_prop_rule = rule; +} + static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, float_status *status) { @@ -143,6 +149,11 @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status) return status->float_2nan_prop_rule; } +static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status) +{ + return status->float_3nan_prop_rule; +} + static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status) { return status->float_infzeronan_rule; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 47bb22c4e25..d9f0797edaf 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -80,6 +80,8 @@ this code that are retained. #ifndef SOFTFLOAT_TYPES_H #define SOFTFLOAT_TYPES_H +#include "hw/registerfields.h" + /* * Software IEC/IEEE floating-point types. */ @@ -207,6 +209,58 @@ typedef enum __attribute__((__packed__)) { float_2nan_prop_x87, } Float2NaNPropRule; +/* + * 3-input NaN propagation rule, for fused multiply-add. Individual + * architectures have different rules for which input NaN is + * propagated to the output when there is more than one NaN on the + * input. + * + * If default_nan_mode is enabled then it is valid not to set a NaN + * propagation rule, because the softfloat code guarantees not to try + * to pick a NaN to propagate in default NaN mode. When not in + * default-NaN mode, it is an error for the target not to set the rule + * in float_status if it uses a muladd, and we will assert if we need + * to handle an input NaN and no rule was selected. + * + * The naming scheme for Float3NaNPropRule values is: + * float_3nan_prop_s_abc: + * = "Prefer SNaN over QNaN, then operand A over B over C" + * float_3nan_prop_abc: + * = "Prefer A over B over C regardless of SNaN vs QNAN" + * + * For QEMU, the multiply-add operation is A * B + C. + */ + +/* + * We set the Float3NaNPropRule enum values up so we can select the + * right value in pickNaNMulAdd in a data driven way. + */ +FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */ +FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */ +FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */ +FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */ + +#define PROPRULE(X, Y, Z) \ + ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT)) + +typedef enum __attribute__((__packed__)) { + float_3nan_prop_none = 0, /* No propagation rule specified */ + float_3nan_prop_abc = PROPRULE(0, 1, 2), + float_3nan_prop_acb = PROPRULE(0, 2, 1), + float_3nan_prop_bac = PROPRULE(1, 0, 2), + float_3nan_prop_bca = PROPRULE(1, 2, 0), + float_3nan_prop_cab = PROPRULE(2, 0, 1), + float_3nan_prop_cba = PROPRULE(2, 1, 0), + float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK, + float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK, + float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK, + float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK, +} Float3NaNPropRule; + +#undef PROPRULE + /* * Rule for result of fused multiply-add 0 * Inf + NaN. * This must be a NaN, but implementations differ on whether this @@ -241,6 +295,7 @@ typedef struct float_status { FloatRoundMode float_rounding_mode; FloatX80RoundPrec floatx80_rounding_precision; Float2NaNPropRule float_2nan_prop_rule; + Float3NaNPropRule float_3nan_prop_rule; FloatInfZeroNaNRule float_infzeronan_rule; bool tininess_before_rounding; /* should denormalised results go to zero and set the inexact flag? */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index a769c71f545..b4f3f0efa82 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -475,6 +475,10 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, bool infzero, bool have_snan, float_status *status) { + FloatClass cls[3] = { a_cls, b_cls, c_cls }; + Float3NaNPropRule rule = status->float_3nan_prop_rule; + int which; + /* * We guarantee not to require the target to tell us how to * pick a NaN if we're always returning the default NaN. @@ -500,145 +504,56 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } + if (rule == float_3nan_prop_none) { #if defined(TARGET_ARM) - - /* This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. - */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + /* + * This looks different from the ARM ARM pseudocode, because the ARM ARM + * puts the operands to a fused mac operation (a*b)+c in the order c,a,b + */ + rule = float_3nan_prop_s_cab; #elif defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; + if (snan_bit_is_one(status)) { + rule = float_3nan_prop_s_abc; } else { - return 2; + rule = float_3nan_prop_s_cab; } - } else { - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } - } #elif defined(TARGET_LOONGARCH64) - /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else { - return 1; - } + rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) - /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(c_cls)) { - return 2; - } else { - return 1; - } + /* + * If fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + */ + rule = float_3nan_prop_acb; #elif defined(TARGET_S390X) - if (is_snan(a_cls)) { - return 0; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(c_cls)) { - return 2; - } else if (is_qnan(a_cls)) { - return 0; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 2; - } + rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) - /* Prefer SNaN over QNaN, order C, B, A. */ - if (is_snan(c_cls)) { - return 2; - } else if (is_snan(b_cls)) { - return 1; - } else if (is_snan(a_cls)) { - return 0; - } else if (is_qnan(c_cls)) { - return 2; - } else if (is_qnan(b_cls)) { - return 1; - } else { - return 0; - } + rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) - /* - * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns - * an input NaN if we have one (ie c). - */ - if (status->use_first_nan) { - if (is_nan(a_cls)) { - return 0; - } else if (is_nan(b_cls)) { - return 1; + if (status->use_first_nan) { + rule = float_3nan_prop_abc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 16/54] tests/fp: Explicitly set 3-NaN propagation rule Date: Mon, 2 Dec 2024 13:13:09 +0000 Message-Id: <20241202131347.498124-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test.c | 1 + 2 files changed, 2 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index fde64836194..39d80c9038f 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -493,6 +493,7 @@ static void run_bench(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); f = bench_funcs[operation][precision]; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index 251c278ede9..f290d523ab1 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -940,6 +940,7 @@ void run_test(void) * doesn't specify match those used by the Arm architecture. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Mon Dec 2 13:13:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B351D7831B for ; Mon, 2 Dec 2024 13:29:10 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Tp-0007PG-Cx; Mon, 02 Dec 2024 08:28:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Go-0002gd-E7 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:27 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GX-0003F9-TW for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:20 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-434a45f05feso53395565e9.3 for ; Mon, 02 Dec 2024 05:14:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145258; x=1733750058; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Xzjo6YdgDduUN5CW5xi57KmQUyStE6Nvif1Jh7XAts=; b=ahiOZbe06EmPSuPcGXwQhqFef0Eu+i8SCB/Ljpbe87FrZrjqz24s5nok8C9A+NfDS/ U/YELyk2mcvT5rlNwcTI8R1F2xV/NIwhMc5VSCOnFTLz2Q6AarGMVeP54zzBHoJeUUF0 zZcIieJRHsZGql0R54tuJkFVsN6oZ4P+uHr8Pz+n0Qv9/RmdGd92HyfhBjdb0VURShPR XmjPpTGDiS6QFFmPJ/T54CM75FpHmFzv7pbJE9ppwBmbP5unxSBW0NHviP4xk4bNY0dz PjDbX9BOOMe799sPx0morxahNsnk7gnkmeAFX1lB5Z7NpmB/jg7J4aQKBG7XCaghWlOg HJnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145258; x=1733750058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Xzjo6YdgDduUN5CW5xi57KmQUyStE6Nvif1Jh7XAts=; b=FU7gmLPFSpYwvfLyryKVBN396dQDnjxa3Q/YJOFgz9LMu7OunUeMS+H2MGNEz+CLq0 iruwHcQEC5c8zYnFx6Yta/uT+Sqc35+hla8OUkXub6JKbr6ZhCi/3qG3hVh1mot5v7M2 DV8q/R+aLnIXx4Au8A9I/u/SwLXCFBGiQXQ47qIQj78NCeYND+rkgK+0ZNZbrEJz/IHa WefWrRP4C3pdm5aLywBhHL87VIDKr0P03A/5DltYrdJUkE13JA9U1UiY7rBWJ7R/a6kO JvRoYP9cYs41BWAJhlkOubo7wH9oVQCusXE1vVKL2ZEbgDXV0cV3rPG2LRt8fO3lis0l DAiQ== X-Gm-Message-State: AOJu0Yz1eoXBdi8m1FkGu+YdVGyhbPf5oSZarXVHx76HJmdLoOaLKFkF U0i0rBoqpxbWr1Pn0wlsT8Ve9MCuGxHOPtLe0anrsd6+wHg+C6BSU2N1b3+mhP+cwoAzyRApWB9 b X-Gm-Gg: ASbGncsWGKvjLFwSrMXzsKp6bnwseUXhKku7zrJddyzMhKx3LEz5wM0uklrtCeYllbN qVYuaeIYA+HLlbhD7Vi8bLijmz+Jg+/oTaSvwbckbCX/fuUyO2nc+a4EoJmVsVWa9muFUAbp63x mLQYthMIMi+zNQ6LR05iMi0u1hSxFUGmO3RvB6KVs8QT+7vrVXjJ2cMuylMD0MOV0ojQeHyemGM IMI+bSBiOM7dqPava/vGNxS+MMcziXQsCFWPOpLUQ0p7HeYsb6379M= X-Google-Smtp-Source: AGHT+IGVRwQv64xZT/ys+pYM7FLew3XpNvoLwo0JpRjreFc4Elcn+x+eqDZ6C7lHAc4rYFvS+ozJRw== X-Received: by 2002:a05:600c:4f85:b0:431:4f29:9539 with SMTP id 5b1f17b1804b1-434a9dfbb05mr223665295e9.32.1733145256407; Mon, 02 Dec 2024 05:14:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 17/54] target/arm: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:10 +0000 Message-Id: <20241202131347.498124-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 5 +++++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ead39793985..c81f6df3fca 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,6 +173,10 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 3-input NaN propagation prefers SNaN over QNaN, and then + * operand C over A over B (see FPProcessNaNs3() pseudocode, + * but note that for QEMU muladd is a * b + c, whereas for + * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling */ @@ -180,6 +184,7 @@ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b4f3f0efa82..3a2d0444475 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_ARM) - /* - * This looks different from the ARM ARM pseudocode, because the ARM ARM - * puts the operands to a fused mac operation (a*b)+c in the order c,a,b - */ - rule = float_3nan_prop_s_cab; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { rule = float_3nan_prop_s_abc; } else { From patchwork Mon Dec 2 13:13:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88EC5D7831A for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 18/54] target/loongarch: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:11 +0000 Message-Id: <20241202131347.498124-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 6a2c4b5b1db..37a48599366 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -37,6 +37,7 @@ void restore_fp_status(CPULoongArchState *env) * case sets InvalidOp and returns the input value 'c' */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 3a2d0444475..d610f460026 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_LOONGARCH64) - rule = float_3nan_prop_s_cab; #elif defined(TARGET_PPC) /* * If fRA is a NaN return it; otherwise if fRB is a NaN return it; From patchwork Mon Dec 2 13:13:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A4B30D78320 for ; Mon, 2 Dec 2024 13:38:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6YT-0000OV-CE; Mon, 02 Dec 2024 08:33:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gz-0002z6-P6 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003Gw-Nu for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-434ab938e37so26677425e9.0 for ; Mon, 02 Dec 2024 05:14:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145265; x=1733750065; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D7hgTTAcAvvo63kNZS2ll5arN5VoViH9sR+6kv3WAC0=; b=iydRV8ew3QGAeyT4E0h018WIL+xrxgWgij9lczJcgUM50zSjUIi3Yr3Hsueahc1sri y90B8hwo3DSZTl/hts5SdwTnV5Ct23KUdfTEQS34WsujziCevXsoxCMXuz3op8yTCl6Q J1UvdYTWRwNlK+dCkkXgRbhJd5xDTOriTbhnEMOHcKFOhs0WJdm2MjfmMqkOm0q6bROb DTGPxNdw1Fq7gxGTZdPrynHOQ/ofKvpO5YltKR8ot7+0FQ5sPoNMIMfQh0ivYzvZi54t iHS0ShtXBzDLD5f9PVkvYKnKQSCtsULylXRYh3/TuzmcaCymJvJCMM/jB+mm3YcnL14g TjAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145265; x=1733750065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D7hgTTAcAvvo63kNZS2ll5arN5VoViH9sR+6kv3WAC0=; b=WNv9ZZl4JNxL8Y30xyvyofO7uolYmhodBOrcIC/UhcKAHgRV+lI1bLWwbk8zgap+Dv cHx+B8DItNC1DGtNnhISCgW95/txplBTMjqFeM5MNWzKWk+9TcgL5ekXR3Yem3t6Q5G0 zI19cT5WcR3wsuhB6YLhKgh1Tbgl0W/EW9GB5X1WJ1nirhsjcfvw/69IeqztzFd1sGk9 3VXHcTi/otkdVczZOLbup1WXrzmIu0d8BGBNRmZLYy+wfjyGTnMddGQYbqOVQ1cvkA1r 3k2UYWDPkRZqnedtxg4Wr/tDO5iK8Z05EdhVCzLOv3j0Xne7YHyYxODtI3g1q7gRNPcg d10A== X-Gm-Message-State: AOJu0Yx7b64ulCOuBvUg24Fl6EWgtexSHFbRpRkAGYbDbzvylpsNtyMD 7HTC/FYioCiKzsVarxk3/2eJ3qkaV2RC/uovu7uYHCVOuURN4et/O/j4vuvJ2MH8bMZabCTK6qu j X-Gm-Gg: ASbGncugjsjOaFsTcjaC8SYMKAJRWQqi33LVnl022BQ6fSI/QYpVPZAZv/cNeMTP4Rr XgtdaR5HOTO0K+JRL62mpY6nCNcZ4vq9bzrcpICuW7Tpq38Dc8IJXWGHPoR11w2cxgZ0NlyEO3c ga+8HG4fqQX4wDFwIo9Fu1po8aGE0CjbIF9a79v+F3P1wdtSKbU/cCiBOnp3vJ00tMcqZUYx6pM yS4llh7pbT3EcTuIlcxTpYuWJRtRFengF+xvTPqbkhpg1s27VgQN3M= X-Google-Smtp-Source: AGHT+IEemo/kgleI2mLyCGQ61C0ZarnpS72GAYORVMtATpCawhtbXLGDqOMXKJ50Nry8KpGTlsLeDQ== X-Received: by 2002:a05:6000:4020:b0:382:6f3:a20f with SMTP id ffacd0b85a97d-385c6eb7c84mr16653095f8f.11.1733145259733; Mon, 02 Dec 2024 05:14:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 19/54] target/ppc: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:12 +0000 Message-Id: <20241202131347.498124-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for PPC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 6 ------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f18908a643a..eb9d7b13701 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7270,6 +7270,14 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); + /* + * NaN propagation for fused multiply-add: + * if fRA is a NaN return it; otherwise if fRB is a NaN return it; + * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB + * whereas QEMU labels the operands as (a * b) + c. + */ + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); + set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); /* * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d610f460026..173b9eadb57 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,12 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_PPC) - /* - * If fRA is a NaN return it; otherwise if fRB is a NaN return it; - * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB - */ - rule = float_3nan_prop_acb; #elif defined(TARGET_S390X) rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) From patchwork Mon Dec 2 13:13:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2AE9FD78320 for ; Mon, 2 Dec 2024 13:31:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UL-0000BJ-7l; Mon, 02 Dec 2024 08:29:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Go-0002gS-Cd for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:27 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GX-0003HE-Tl for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:20 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-385e96a285eso879507f8f.3 for ; Mon, 02 Dec 2024 05:14:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145266; x=1733750066; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RVdc4tZyi1UviPeSEA9C0j58Iz1J5UUJq0KN40I4wsc=; b=yzxLQQFh5ZAoRMP+QJ1WOdNdShuHCb63ny70ztlOgIjkhnHbpt47gTWKmDHWFPP54w rYwDp9wBFzmhg2X8aWu5t/jJ1Q4TjGHiA+cLha7itEs2NqY/7BmUKsjqRXQ5dJlCDF4a ZYFDKm61j4hDotovagmPQ9PwUNoJE1Nsm5m8QzDzw6bAG5ONtUfIH96Nxthj1Cr/Ojyj 3N7kjGZvOnuc6ARRCUzUis2xpH6H9rN4pctboLCM+kGgARwoGdACUhToegNo/Mh8s2cl ViOy2sg95X/8nRsWWbr17iKfhpT2BUTUKWwGXwE4t0ECJDxLk0w68lg7f5WnM/qOSHVI /sHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145266; x=1733750066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RVdc4tZyi1UviPeSEA9C0j58Iz1J5UUJq0KN40I4wsc=; b=R3H/YO7i6+sZA922g7fDuWHc7UWIYNVZNKDNeeD1hdcsl9jjZKkFu67rh8rw64nl6a tz3i0+YKEbVYIwOSegIS7X4mNix1fIzN7wO7hAfBxJDe1vDsjcidcz7NrRtTBUImh1Xp NYtSM3vpdzF91dYYb72KeZ9t6BApFtcKiNZy3kfYZepXKhkRRaa/5tWET/h/jQeqZFHp Cn6azXMFP48aQP+U/L04m347qCMjwifC5oEIwIdgkTk0u0/ES+USnxemaEPhcENMSYqt D58aNhHTMrIxTjK/yRWomgs769FrYU5OGEtt5epBSMHAF4OT/icasU1u+9vGkvIRqeId IVww== X-Gm-Message-State: AOJu0YzED4BdwYRJKUrCVBXjvus+uVJP/5PEsq1clwfEKXuTxODvlAm8 4OkbfoEbtye/1oXBRdtot9nT3f7YXeU8z6ByyCgs6cMkYvgJ0iq6feG+KT+YCiC8/ySPNrLbAkw / X-Gm-Gg: ASbGncusMfjX8bgWtBEtZKxEHbyg5ifDrrmzUw0MrPfiTqVEb64Aw1a0ZzrNu4L1yjW qpRUX9TE27GjhjbQ6lP/+ScbwjSJ7BC8WAh3PeDr2Mtcw8bjCxeS3bdGqYTqM3sBt/C+syfI9bU TVf1wXnJHK9Rgwzbt/e+RLB9bz8cJi8LZgeRKXklPsrlHI1qIeynQ/dHmwLtOnFrLTWbmQ+zZ2A Pl/wRuWAHxnQTPT7nIn3BiI7SjrDnJMwqVKMLA2/5k2+sSqT/mrxK4= X-Google-Smtp-Source: AGHT+IFX1etwkjarTt46ZlKph01y4djx8VmdliUA9Wg/W51R9iVpkNjJ7oK3rgJgCn5gIz9g28Kmog== X-Received: by 2002:a05:6000:1566:b0:382:4f70:10cf with SMTP id ffacd0b85a97d-385c6ebba5cmr20127579f8f.20.1733145265729; Mon, 02 Dec 2024 05:14:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 20/54] target/s390x: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:13 +0000 Message-Id: <20241202131347.498124-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d5941b5b9df..e74055bad79 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -206,6 +206,7 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_detect_tininess(float_tininess_before_rounding, &env->fpu_status); set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status); + set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); /* fall through */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 173b9eadb57..8a36280df1a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_S390X) - rule = float_3nan_prop_s_abc; #elif defined(TARGET_SPARC) rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) From patchwork Mon Dec 2 13:13:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE009D7831F for ; Mon, 2 Dec 2024 13:30:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UD-0008Pw-Oz; Mon, 02 Dec 2024 08:29:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gk-0002Zg-5p for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:22 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GS-0003HZ-Tj for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:10 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-385ddcfc97bso2608735f8f.1 for ; Mon, 02 Dec 2024 05:14:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145267; x=1733750067; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=buw3vsQorwZwaR50k4S9PXYAF2rd+6sbEuYUjFK5KVQ=; b=q344wjlfB1syk2rTk4pJiuBHFfBB2Lr1jBeBCPA3syz1s5a57MzcPeWEce/kqWNDij 3wt3nT+pPZ/txGt0YyQGHMcgDa6Y4x2gM5vCBWRbGuavUdBXn7xiv3oZqXTU7XUoDmJR RbZfa5YUIEN4vq9V+e8xQ2UpKjdJgk/oIMtS2CEBSP74uvHiZRz3qY39qjvyb8TTO/Ex X+6C6WQFo2zUDCEAbzc2nhRYLKnIGaFHfkA+ltRr+ZS0SYrCmaIk5yVORC44OEAWg/As Mkl0kChUs4QhI9f/qBM2BNFeVfQ2OjoyATgITf0O/yCkqc4lOsCdHdYrlrDikKarX1Dk Tkcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145267; x=1733750067; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=buw3vsQorwZwaR50k4S9PXYAF2rd+6sbEuYUjFK5KVQ=; b=OXNj5VFSq3oLYwkuBxNFUhAhTaqta4D8CC6mi2bbvaXR4zEa91zIYYNTvKgYgIpYHT OKodpmkERtl4Lfnpw0Ll8DZI8tw+dTSX747TB+CBxTmaxHNJzynm4Ggdy7fxAZCYtTud tO1FtmGPvAJbEXLp7p398/HccIHGT1qtVYTPlYdjeT9LMwh9KZsJ+k4JDoaJvdyBMsfN F6SfoZmzzIMrulx1Cl+KtQbklsGMlXra7UgGiVSdbWdvthzV6cKEOQ4QvqiRszCipsNO +O9feNu63fNZHvKVK42XrFzWCX1+IAOmEBBdpDE04t0Vncrro8kXkJpeY1Whf09RItJH wDRA== X-Gm-Message-State: AOJu0YwAdQyzLn47Poq6jHSxQoq0Jkp1zauRA6q20PLq97awHxgwEyww JA3ACY4g3zxMlwI/wXmIOT9XW1EckVWhhVf2j4cMG166ZgOeKCSYPZsHhGMqHJNB81i43AJyqE2 V X-Gm-Gg: ASbGnct1ew6UnzOX7dKgZW9FI2CKm9UpFpu4O+hM9QIZ6da3BvyuBeFcVIAW6AHcS/u vrm5k7TlyyxhLBv71RBaEKO2BJ8ludFGrV0vFyH9iiNO8nmBGQkX2J3Pc95CQE/5V9FbXRBCluW 95li1d2/ujoVbi6Wp7jbShTw1heBZgQMQTH1hlzGqxGKr+G8wVdpIVbNrym2RGOpU7roAqMq4aU pJGTzaxdBAHr8CVefnmIoptYdC4oO5bplI+zxGumUL8Ut/KtJalgeY= X-Google-Smtp-Source: AGHT+IHx8PwM6AIzlpEzsxr8J+LyWnE7HUOX8ZkDkwcjSfEuU/Kwyf4EVLl7tEc4KnIW1/2mwf+TIw== X-Received: by 2002:a5d:47cb:0:b0:382:22c6:7bcb with SMTP id ffacd0b85a97d-385c6eb4c32mr20727841f8f.3.1733145266761; Mon, 02 Dec 2024 05:14:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 21/54] target/sparc: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:14 +0000 Message-Id: <20241202131347.498124-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 61f2d3fbf23..0f2997a85e6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -814,6 +814,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) * the CPU state struct so it won't get zeroed on reset. */ set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status); + /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */ + set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 8a36280df1a..c4d8d085a98 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -511,8 +511,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } else { rule = float_3nan_prop_s_cab; } -#elif defined(TARGET_SPARC) - rule = float_3nan_prop_s_cba; #elif defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; From patchwork Mon Dec 2 13:13:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 196AED7831B for ; Mon, 2 Dec 2024 13:29:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Tz-0007qb-IQ; Mon, 02 Dec 2024 08:28:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Go-0002gV-Dj for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:27 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GX-0003IZ-4q for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:19 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-385deda28b3so1803652f8f.0 for ; Mon, 02 Dec 2024 05:14:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145270; x=1733750070; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=74ZFmjtVXHtNex2HC0gYU65u2vZGTycqwogjuvw6ju4=; b=Gc9PmP/YovdJH4HWXy/98SFsqTHUDTsErfG9ScmxULAZ6FzByalju071nyMMiJ9JvE vGT8VpF08IPCsCUeIv2djbsHk/tUicPCkE/g6jy7zVUIktUKVO9n8ASRSgdHuFMDBTo3 VHeBIyETCwGLT5Ys4fhMkFsea6XVYr1HdopibKNOIRy8/wSVByfcbZpxCvUADui+n3+R SWH5VOrvtU90ZDxr8GcTKc6l1u6gjDqh+5vai6NWYs7lco6/97wc6ChaMPVHI45C3sex 8I3IWL3s198P7WUHT4yuRafGxhU22FC7MKHjZznkwZ4rvCWLIlncrNtQxOWIhKgJAoGk lj1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145270; x=1733750070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=74ZFmjtVXHtNex2HC0gYU65u2vZGTycqwogjuvw6ju4=; b=FAzkU/a+IMuXSId2TjC5CspfTYyeRgU3Cw7zg0fqSRASJuGR/MbB6rN8xnnse5D4qk 9EdAiWfYshDhEF1gsQjEzVkn/Q2dv4mNNSBKVqhI0GXdVOz3Ij3xMkPVYWIvzul7oiiO 7Hodg09DNKqHR0xbHWSOmt14d79C8a8raFTlsCRhKm3gA3iQmrKXo2r2gLxV7tpJPF44 k9mrpfujGorEvVzadwDtPl0znxP+GpnwGnl6hsaAOtTDVoannBpNs3eJqhVgKuN2DcRU YR3irgqaZmIHzuKvOP0+FmAUqlYO6b5VdjXAEywroKPhPW8dOpLUnh5Qt3t9XLIjJsW2 NM/Q== X-Gm-Message-State: AOJu0YzCzQk7Dh1bBu4RRikulN/ZMu4gpbeFrZmWpdjt3bhvq2DXtENE X3hZxju2Gm/gEI07uHFFshbsMH42GY6YShqbGQwFYfcri8CuYMBrOAW9xFjIYfIkLvImypAkcAz v X-Gm-Gg: ASbGnct7FC1Ph4tJ81tlz9IHZn5PA0JbEfd0GZ7jx0eV02cukirWuzhO7eJnt0j15nE dYRGXSZdUhiDRFQd4bfNx/HCLpMQvkQ1tLnPfbHx9IHwDT+gsBKX9bsR+gR9KBuiHkjE8KQQa+L X/ov6+I31AefFcjfmA95klgwH6/lEYb8T3VjQndQwOf4P+cvorZCSflY4nGe6wnSoLHH+BY0N3d KxoBYCUjPEV4XQJ2ZzPoO2zMe301LQ0qxAbCEwo4cRmBZ+KcZLnbwE= X-Google-Smtp-Source: AGHT+IFTXydxmNqzHUMrjLYeqi7UUKW4Cm6RESZeQThmbS95R5edyOboW/pND1+LCIW51N2TZjvQnA== X-Received: by 2002:a05:6000:156f:b0:385:f0c9:4b66 with SMTP id ffacd0b85a97d-385f0c94ea6mr4495634f8f.33.1733145267678; Mon, 02 Dec 2024 05:14:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 22/54] target/mips: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:15 +0000 Message-Id: <20241202131347.498124-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 4 ++++ target/mips/msa.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index be66f2f813a..8ca0ca7ea39 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -29,6 +29,7 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) { bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); FloatInfZeroNaNRule izn_rule; + Float3NaNPropRule nan3_rule; /* * With nan2008, SNaNs are silenced in the usual way. @@ -44,6 +45,9 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) */ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); + nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; + set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + } static inline void restore_fp_status(CPUMIPSState *env) diff --git a/target/mips/msa.c b/target/mips/msa.c index cc152db27f9..93a9a87d76d 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -66,6 +66,9 @@ void msa_reset(CPUMIPSState *env) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->active_tc.msa_fp_status); + set_float_3nan_prop_rule(float_3nan_prop_s_cab, + &env->active_tc.msa_fp_status); + /* clear float_status exception flags */ set_float_exception_flags(0, &env->active_tc.msa_fp_status); diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c4d8d085a98..28db409d22c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,13 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_MIPS) - if (snan_bit_is_one(status)) { - rule = float_3nan_prop_s_abc; - } else { - rule = float_3nan_prop_s_cab; - } -#elif defined(TARGET_XTENSA) +#if defined(TARGET_XTENSA) if (status->use_first_nan) { rule = float_3nan_prop_abc; } else { From patchwork Mon Dec 2 13:13:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890640 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C9C4D7831E for ; Mon, 2 Dec 2024 13:31:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UZ-0001VS-Nd; Mon, 02 Dec 2024 08:29:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Go-0002gR-B9 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:27 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GX-0003JE-VH for qemu-devel@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 23/54] target/xtensa: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:16 +0000 Message-Id: <20241202131347.498124-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 -------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index f2d212d05df..4b1b021d824 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -62,6 +62,8 @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); + set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, + &env->fp_status); } void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 28db409d22c..67428dab98a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -505,15 +505,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } if (rule == float_3nan_prop_none) { -#if defined(TARGET_XTENSA) - if (status->use_first_nan) { - rule = float_3nan_prop_abc; - } else { - rule = float_3nan_prop_cba; - } -#else rule = float_3nan_prop_abc; -#endif } assert(rule != float_3nan_prop_none); From patchwork Mon Dec 2 13:13:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890616 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EBF20D7831B for ; Mon, 2 Dec 2024 13:22:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6JK-0005fa-0K; Mon, 02 Dec 2024 08:18:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GE-0001xF-Iw for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:49 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6G1-0003Jd-Pd for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:35 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-4349e4e252dso39840835e9.0 for ; Mon, 02 Dec 2024 05:14:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145271; x=1733750071; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=73eMz7OCXkqR25Bej28Tzkpl+eCdRMSro7tB3M4lS/Q=; b=s+gdHeQoZ15txiKdOQ+6+WcoNGCzK8gDyqo/GHLuniHd2qnUFEQEiA/pTpxXJQHL/D SN/ipZE/YvQt4E+7zdvylK20Sq0euunwXbqK/wgePJlcCG/npqffKqBw+5np8IbqXeor Ocl2v9x7Pleyh1rSg+cQbi6polk3CEcb1fQFTIgFuuUX/ed37KYiOwIf+JpXLS5hcabB Vf0d4b8iVABIXD1rCgw9fbJCJpxYSaAsqWALKSrEFSU5O2/w9GaQZsIQNJN8c5VvVsdv 1xAvn8uaeccXWagXH99p7PcInOXf+RiB26DCLv1om1PNDiitysFG/hSjewM8/ZSkWC/2 Rq6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145271; x=1733750071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=73eMz7OCXkqR25Bej28Tzkpl+eCdRMSro7tB3M4lS/Q=; b=sKYseNUwdHsFNcMHRopXqMmrRp8wimB6rfZpAq2+fQMhudByNM7KOTVQY5DbkMifAl 2vbwA5c7BKBwS1ycQZu9no+wIsr+lLvn4lxi7giGxhmhEgcB3lV+sxXXqHKNDmPmvylz IMxMJJM+cflzlMmba4cyjudPLLBkx2KqSFHWrFH65T+tDS4fyvkKG9oyEvGADdJ5ua3E UEJTNADs9vNDz0CIkYCissz3qNtHXi0p4MbrDrOWIACjrfFn/W6FzyVVlSveFo3QYJE+ 3ZE9ipCftZOGzex7Al8FBMZ2yHoUhjlPlPvs2ktL7sob5zsDaO+hHNeN64u/BiXFp0wM /FFQ== X-Gm-Message-State: AOJu0YyAz/oiwYxYiZMO3pQLiR2AflQeLKaasK/0/Lxmao8msBiU7x8d g5AAQxC3jXWlxG4oLJvRkuzHI84atJyCsPwRjBdSFUgTDRkGnMLNaNfxWtpK/6hbcrfq/agt02V k X-Gm-Gg: ASbGncsi8uqZ3wNvopAB4iy3t0mtZXZccxyQC2LiK++vookr8v8I09t0OPbTgxP0HWr YuFHSD/7uoH2rGcypaqf2Yl1NmFqMx9DT/PMsZC5b4M3LYbsWYj+iPE5Oz06xWYebx12ovI/2KI bjN3xmlx7yls+hMj1iw6ooBVTZm3WfvcpYIjLtNngYFWkoE+r9zxRQxZ4/ubao5+Zlf6scH/E73 r6wsPiYHugoA6xie1dtNqY/3REGWFDajmTp3eRSVeUuiCKOArrAx/w= X-Google-Smtp-Source: AGHT+IG2/CSEfYg56kx1cobXlqN2iyYc1dWHh+2d87J+zwUjg8IA98GdHV2ZgCo25GDwnUjwcav3Ig== X-Received: by 2002:a05:600c:4708:b0:431:157a:986e with SMTP id 5b1f17b1804b1-434a9de43a6mr186298675e9.20.1733145271469; Mon, 02 Dec 2024 05:14:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 24/54] target/i386: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:17 +0000 Message-Id: <20241202131347.498124-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback; this is actually the correct per-the-spec handling for i386. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: drop comment saying NaN rule is wrong. --- target/i386/tcg/fpu_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index a98b4f67ff0..c8bc5b7cfb3 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -180,6 +180,7 @@ void cpu_init_fp_statuses(CPUX86State *env) * there are multiple input NaNs athey are selected in the order a, b, c. */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) From patchwork Mon Dec 2 13:13:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 409B4D7831B for ; Mon, 2 Dec 2024 13:22:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Ku-0006zM-0L; Mon, 02 Dec 2024 08:19:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GE-0001xQ-Jt for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:49 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6G1-0003KO-QD for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:37 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-434a2f3bae4so39689385e9.3 for ; Mon, 02 Dec 2024 05:14:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145272; x=1733750072; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e3mx5QSLs3F08ZGNoyI8psAl3Pzx9Z5IpdlAACesozc=; b=i2lfPV4xGjJzTBX14HOMqXC3JdSmMcQPhQSyGt/3MswppJ7lzAr9JYPE3+joGDEp58 Xr+4xKXHpyYuhB0Ic/73RfS89njqXQijf/lUsnQvA3Q+HNhPWL8wRG8FMZVngF4nk6yF wKXTn2/83FkbQzxnrAHmdu22E7maMshJjIh+w9vJjb00WSrCMwWXcKsSt3otb26HmML9 Jj8z9Cq95bnO0iODWGiSieMcMOeJrF2SipkJFekiqQqgfTKbOs3zjrMm2lGxt9S6+oxb EsLwyhjNpAYYIDvsFqzzVdKZzk/aA8FlEGTxGSsr6+4LRSawfARp27+U1AZsHy6aF6VU za1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145272; x=1733750072; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e3mx5QSLs3F08ZGNoyI8psAl3Pzx9Z5IpdlAACesozc=; b=Qwmg22t0+FcR1N1OUdonRs2tdYEaVlCB3eLd02M6v+iCW2UbYGPfrh3W+aaZqH5Lr8 C6OixIhd3CLSYsSOSKXu4XGKVq7Rl3Pal6P3vOuFb8tfeQEvCGJmcQQfl+SwVN4VFLmH 2XuZeTo1Duhxk9r9y9YnP5gRZPbN13OrtjarJjxTxmTCmeFmFrx1q4u8KiGtsGzQUDyP DoWCN+a2J4+RGWjE2WjYIsrVm7l4jQ6vkvgweX10XB/pbcCPguUZADTFm62HKfhlbNdR rrPbFwAZB9aiAwbY7mco6hMR021MNHb/y77lrQ4p2j8DtgC31DRjZ4moZBPfD0mWuhof dAVw== X-Gm-Message-State: AOJu0YzJsLGAx1vCfsvcDkSRWZuhw1X4xFYZoYY4ChWE+s8aV5I8btgS /4JROGozT5xBJ0D225o4hlkFen0iDqQqZFRkOJ3K/4xYiJXB1TcqEjw3EMNoxuWaOMKGIqYyTSH z X-Gm-Gg: ASbGncsgaHaxaWBcKoouqZgxiY9dZKT0woHXKTeDqwd6hP2l2wWkGka9e41SKXr3E9n pNcj+yWa79wtefc9Fa/nHyuCEbUEIyl6n/EeCNBfVTtN8nJz9yvC51ze+ZywD1t0pzmqZqNusH9 iLpP1QO0CRVPinGyjw1cu4IeAItsaibAVuT9PvxH9f2tOk1GXuTxiOawsoIoTK9DxJpboaLTHFO HUHXT01xluW4JB033oezKo5Pt6HBQXlY5lmgTYBnNM5y65uxsrz2X4= X-Google-Smtp-Source: AGHT+IHo5qXo80fvKVDN2QJ+mr7r2kre4mQEoU2bb76IiltLkjwknMLbk2u95ylvKm0zOC8wXnfN/g== X-Received: by 2002:a05:600c:154f:b0:434:a706:c0fd with SMTP id 5b1f17b1804b1-434a9db8386mr204248585e9.2.1733145272313; Mon, 02 Dec 2024 05:14:32 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 25/54] target/hppa: Set Float3NaNPropRule explicitly Date: Mon, 2 Dec 2024 13:13:18 +0000 Message-Id: <20241202131347.498124-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the ifdef fallback entirely now (allowing the "rule not set" case to fall into the default of the switch statement and assert). We add a TODO note that the HPPA rule is probably wrong; this is not a behavioural change for this refactoring. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 8 ++++++++ fpu/softfloat-specialize.c.inc | 4 ---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 393cae33bf9..69c4ce37835 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -55,6 +55,14 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) * HPPA does note implement a CPU reset method at all... */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); + /* + * TODO: The HPPA architecture reference only documents its NaN + * propagation rule for 2-operand operations. Testing on real hardware + * might be necessary to confirm whether this order for muladd is correct. + * Not preferring the SNaN is almost certainly incorrect as it diverges + * from the documented rules for 2-operand operations. + */ + set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); } diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 67428dab98a..5fbc953e71e 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -504,10 +504,6 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, } } - if (rule == float_3nan_prop_none) { - rule = float_3nan_prop_abc; - } - assert(rule != float_3nan_prop_none); if (have_snan && (rule & R_3NAN_SNAN_MASK)) { /* We have at least one SNaN input and should prefer it */ From patchwork Mon Dec 2 13:13:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1D464D7831B for ; Mon, 2 Dec 2024 13:24:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6OJ-0002kd-Kv; Mon, 02 Dec 2024 08:23:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GZ-0002Iq-EB for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:09 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GQ-0003LG-U5 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:07 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4349cc45219so38146825e9.3 for ; Mon, 02 Dec 2024 05:14:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145273; x=1733750073; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jZmEjYqAtBnicHjPyhH8ft0gcTQribvPLCBufh/En/c=; b=GU37X9LjbCvpcV6NrKLuGIywsSS2Fipi5dQ5KopTUxLchOTk1BCey2tn4v9t7fRTK2 pAdqTYog5LFfMH6olgyNzeib/oOE554znHJ5dN13v6+3maNawtDnfXiedasBXKucHp4d hxUQVlZQTs4AatGFLsDzXGMup8AWhNkDw9+ES4ddH0mRJ4aurapqd9ZMKEUQJBQqFWfa 4eULiXGfTsuLukVcq07RMwA3ka5dTCDGNzR0mgBZL0sxZ5ap3Z9gysVq7rkdOCt202ll eIi0TBmytPBnerQtvrIpqFasoKH6iTGQG2Z8m9bWlPzsVV7IgPEECiuOqE71Ex5ihypS qJ+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145273; x=1733750073; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jZmEjYqAtBnicHjPyhH8ft0gcTQribvPLCBufh/En/c=; b=Q/Xm2PTrEFbIE1g0LbFyIcNT53X4D56M5AMtB+cUvFG3yhzdoMIowx5p9PqMOvjy6a AWeil8VSUU/4MpdJgLq3tRwjiitVngNKbaHw4czFm5S1xqqLM3pm8eGl7NBld20KqEFM SpA/Uk1Zk0RssGhsDpILhhKSkH0JH7oydrcXD0EO/DyYwPjKck7WBUg8eESz2oG2PT0g +u4n2b+O/y8f9KGW7nXY6hgVD1AW1sVgvq9CWPODW8r/yORUtswBmJ9zV7Pz+IvFbv+y 5KGZtaJNEbarn85eA5xbiRsGEVPA/FbLVqeGGwYUgK76yktQoeCZv01LhPoMasfwNGkM MrSQ== X-Gm-Message-State: AOJu0Yy1LSXfI58nJlp3sfJQH4DU6d17iUKgn/i5JVftziSLsB8n1/3D QOpVrEJVF506Eg6pPs1HoC8Bw0sr/VDt9ai2i8Gy07+QlY+8Poci/bEIWYUttHJyGvvz9egzHXH / X-Gm-Gg: ASbGncsMreBR4jK5/GB4EqtssVE/Tf3BdecYf19IQV1Ic7jBcYBjucir5+3eHuoG72A 0YUYMLsMBrId8Eb6lB65ciwfDeqBa4AAKpNqF5zcZhCB4alEVYCCFKi1WBCYUIII/D2KvHvn6UN 4Vh8SO1uRRX4SOy5M6R/z1pbmd2KeWZmgjkOemXhN5erOOJKk1lgLMU9nij5IUAqL7M4oXcXA8f VQeot6JaYzulABpT13CgPCezuNrYlF+zUs3IeC8wiINJXlmfpdvDBk= X-Google-Smtp-Source: AGHT+IH/PALsVo0VAyGUiocqZee2rofdapY0wf4INzIl5OJmdj81XrthiF1qwqcuydvHdNVegxmu1A== X-Received: by 2002:a5d:588f:0:b0:382:51d7:39a8 with SMTP id ffacd0b85a97d-385c6ebdbdamr19785353f8f.27.1733145273268; Mon, 02 Dec 2024 05:14:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 26/54] fpu: Remove use_first_nan field from float_status Date: Mon, 2 Dec 2024 13:13:19 +0000 Message-Id: <20241202131347.498124-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan, because there is no longer any code that reads it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 5 ----- include/fpu/softfloat-types.h | 1 - target/xtensa/fpu_helper.c | 1 - 3 files changed, 7 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index cf06b4e16bf..10a6763532c 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -113,11 +113,6 @@ static inline void set_snan_bit_is_one(bool val, float_status *status) status->snan_bit_is_one = val; } -static inline void set_use_first_nan(bool val, float_status *status) -{ - status->use_first_nan = val; -} - static inline void set_no_signaling_nans(bool val, float_status *status) { status->no_signaling_nans = val; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index d9f0797edaf..84ba4ed20e6 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -309,7 +309,6 @@ typedef struct float_status { * softfloat-specialize.inc.c) */ bool snan_bit_is_one; - bool use_first_nan; bool no_signaling_nans; /* should overflowed results subtract re_bias to its exponent? */ bool rebias_overflow; diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index 4b1b021d824..53fc7cfd2af 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -59,7 +59,6 @@ static const struct { void xtensa_use_first_nan(CPUXtensaState *env, bool use_first) { - set_use_first_nan(use_first, &env->fp_status); set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba, &env->fp_status); set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba, From patchwork Mon Dec 2 13:13:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890628 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FA0DD7831B for ; Mon, 2 Dec 2024 13:25:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6N3-0000rA-GE; Mon, 02 Dec 2024 08:21:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GL-00024W-BO for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:53 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GD-0003MI-LJ for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:50 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-385e1f12c82so2553956f8f.2 for ; Mon, 02 Dec 2024 05:14:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145274; x=1733750074; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MX9sc7FmhfylUuxW0cA+BWl3jSlP2Yj9aquR2jby44k=; b=PHi2UVs8C6MXAy7NaLDRDBs3OB4EOMXzjDI36Pxn7O/b+WMdWTzdHT/0/czOmlvHAP hEiAbjgJJGZ3ZeIfvEdONM7wQduamapb6TpMstAr1rYKUHgsuqZb69lF1G9NZuskSr5j pD3XLtHPizADQtUarD38HGkdnh2/NMLqZ0tdjZHGj5D8XDeZ5lHcMBe+kOcckpfBl6Pg Xlf4jOFT/lqJMueF81F3+eoYhZeRFMwSITyfykuerKjWcLmuT/a2RYCWQjTpPfCB38Tc c/ubzRpLnnp1LZaa/XBfunsy4HOK5fcPeJNsIzhM0t+uXLz9UE0yKLRmgqqdp3em1vm5 Gy0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145274; x=1733750074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MX9sc7FmhfylUuxW0cA+BWl3jSlP2Yj9aquR2jby44k=; b=SCYdTJzqQ6JiBubRhCpJcdN2ee74mukY6+Mu4zetuAkiJNRL6IM+pMfE+h85BrmfVO qGfb08jGJOtI47xN440biCzt0bfYtYyPCRnvJlVrWxoz9NyNUkRLt5+DSVfOivTpE8JK qEoXyLzlOpsm7izcfFEaMrKbkuXZImOcaRIuDbeH9eqIZ5tae8hkqc68tuQzx4X61aQz wEl5bsiW9tD7KWb3fF47yfpQNirFevwXIU234mu8hcuGaigyHQYu4kpu7H9IExhsRESA zv8zwn1C3ugqazPvF3rSKlSd22OD5JGsWo/aWEl0Zb8RbhAIP3mTsKRgY01JLSGgNnOj iKIA== X-Gm-Message-State: AOJu0Yz04gGGkt2qjEyrjbp6rl7n+fVwQqY1wxnSuYbxGMquXkAiF1BA mic0Sih7/X9WG54jjsZj7sE8mwpIQIrkCDmGHGCAbPmL0XRU8ySduHH1ChtCeCyxsS6H34DbZk5 8 X-Gm-Gg: ASbGncvANOSTMBlDs97+gYnUeZuW3rYo/f5HeWOAbfJaAkLACFGNJEbAf7R3RFSw9N3 Du9N2ePt/vMDyvuZFsbfEur5wYZYmW4iMSsHB42bmjNkfVH88LnujrKUoRiKNce/cSpM1mpDM7H YXyAchbNK3TPdAUAayaEEaI/g+YmMn6ETHGKlUNYuSdLUyzTQWlm0WFZHSILZMCN821LMQzFgVw cLwnYDnWJnE9KTLX0OxOXLUal2vKWw5lU/icWh4GzdLSQV/KWpeehI= X-Google-Smtp-Source: AGHT+IHeY93QBLGrs0ffOfRyNKPIrpV6GdKIJfYknW2MMO399IIrOc891AWxF9xi3vFXcrfgQfo1EQ== X-Received: by 2002:a05:6000:4020:b0:382:40ad:44b2 with SMTP id ffacd0b85a97d-385c6ebba51mr25311409f8f.34.1733145274134; Mon, 02 Dec 2024 05:14:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 27/54] target/m68k: Don't pass NULL float_status to floatx80_default_nan() Date: Mon, 2 Dec 2024 13:13:20 +0000 Message-Id: <20241202131347.498124-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) to get the NaN bit pattern to reset the FPU registers. This works because it happens that our implementation of floatx80_default_nan() doesn't actually look at the float_status pointer except for TARGET_MIPS. However, this isn't guaranteed, and to be able to remove the ifdef in floatx80_default_nan() we're going to need a real float_status here. Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status earlier, and thus can pass it to floatx80_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 5fe335558aa..13b76e22488 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -76,7 +76,7 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) CPUState *cs = CPU(obj); M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj); CPUM68KState *env = cpu_env(cs); - floatx80 nan = floatx80_default_nan(NULL); + floatx80 nan; int i; if (mcc->parent_phases.hold) { @@ -89,10 +89,6 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) #else cpu_m68k_set_sr(env, SR_S | SR_I); #endif - for (i = 0; i < 8; i++) { - env->fregs[i].d = nan; - } - cpu_m68k_set_fpcr(env, 0); /* * M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS @@ -109,6 +105,12 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + + nan = floatx80_default_nan(&env->fp_status); + for (i = 0; i < 8; i++) { + env->fregs[i].d = nan; + } + cpu_m68k_set_fpcr(env, 0); env->fpsr = 0; /* TODO: We should set PC from the interrupt vector. */ From patchwork Mon Dec 2 13:13:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7660D78321 for ; Mon, 2 Dec 2024 13:45:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Vv-0004Ix-Hc; Mon, 02 Dec 2024 08:31:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gk-0002bl-Vr for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GU-0003Mc-PP for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:12 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-434ab938e37so26679275e9.0 for ; Mon, 02 Dec 2024 05:14:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145275; x=1733750075; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wdqAdxMo/Zjt+7gjYfOwzXdT/5QjRbRXYw8xftE2ZL0=; b=sgmIvl9uV5v2tKz5CA5wywE2NnKdE0T801pKtAK8ld+4ZLRW/ri+1PSzNcYGyGG7zW lQNSq3uyIbx5/ewdpQ7lGeSvXbKjXVuW5Iq+bTwC3eygMGd1HJweXe93BQW8rA7wpB7U aa+cdrDjawOrUOU40mBhdFAgxDsbwIYQYlpf48MEGewogoaqUkORk5p1ajAHmofUSeoK MeguhGtyW+quw1VOnN60+aXyCOMOqQirj8BIir6M/GsP0Q5ykfMItyrhz/BpFhA65of2 Ct/8LI4bCK5mrnAcfATO9pQyStHPFsU70S4IlYQ1YkTUOBfytuizwtRU9QSLfwJVst5j vwBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145275; x=1733750075; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wdqAdxMo/Zjt+7gjYfOwzXdT/5QjRbRXYw8xftE2ZL0=; b=DWcUOQ7EaAJCJEWHnG9CIyWmTFsJ4CqVxxSYfwnBiUkfmbtK/jNJ5FDLpvoYrBXuX9 24bR59BA/4Y2JHJMBYZmO2q1X77V/FjoOWHsH657hRHUq5rOIy073DOotJbSItSnHnQq y9llahmZGpY/o3KmSThXEtdfz8pIYhV6Lq9aMbOS6GQmVDenDgPU9DpxXT4t2GI7D2XB ItmqLF5Ek6TY+enaze/r9KhaL45BnstFm7FFXd8ONHciINEaxIKbK8h731D6fOgmBD3r nHAUqLLEHE8h+JKp0LSgih8lloKZer2Pk7Cw4nZqMwlhyGdieK2EtBMTQEqunblXdvk7 NS5A== X-Gm-Message-State: AOJu0YwgwK1dYUGFK8tX85OQZK8Kb0CXVxdnQ655jDfiipI2UfCfq7LD ROJbKzY8muzoKfG8fbwegY3u9zB6Eh8nUUbBBznLf2oIbIBxugsqcrnt+4N3eYFZEaycDwUbBsN Y X-Gm-Gg: ASbGncvOjCDWnLvUo32WzZGYt+NqWYoc81ahqyM40B1Y0cs4i2rqofc9hWAzYldIj+j t53yHOq1Y3XUr97rl/ZwzuhBLfDV49+ZuWz0y1/LOhki6DkDQ5FhwSUlPHCxXFoWaFXLKlimKDk lfO/bISo+gbwzfOJENo95Ki00RSAxcEU1AIPEtt9m7W8mvj89osEb28xYt/9xqSjymXvhHgeGtq q4E7OgHY0OjbLgOi93H2G70QFau8ISIBbrlyVvT2VsYna20dJ4uTVk= X-Google-Smtp-Source: AGHT+IHpLBkZrKDuWdn+SfRe1n4Bcn7GFrx0fDmm6XZ9hZ1GnazAJ/+blc2Smc6txIX9PHI2+r8AzQ== X-Received: by 2002:a05:6000:2806:b0:385:ec89:2f07 with SMTP id ffacd0b85a97d-385ec8930bamr3048801f8f.32.1733145275036; Mon, 02 Dec 2024 05:14:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 28/54] softfloat: Create floatx80 default NaN from parts64_default_nan Date: Mon, 2 Dec 2024 13:13:21 +0000 Message-Id: <20241202131347.498124-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We create our 128-bit default NaN by calling parts64_default_nan() and then adjusting the result. We can do the same trick for creating the floatx80 default NaN, which lets us drop a target ifdef. floatx80 is used only by: i386 m68k arm nwfpe old floating-point emulation emulation support (which is essentially dead, especially the parts involving floatx80) PPC (only in the xsrqpxp instruction, which just rounds an input value by converting to floatx80 and back, so will never generate the default NaN) The floatx80 default NaN as currently implemented is: m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1 i386: sign = 1, exp = 1...1, int = 1, frac = 10...0 These are the same as the parts64_default_nan for these architectures. This is technically a possible behaviour change for arm linux-user nwfpe emulation emulation, because the default NaN will now have the sign bit clear. But we were already generating a different floatx80 default NaN from the real kernel emulation we are supposedly following, which appears to use an all-bits-1 value: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267 This won't affect the only "real" use of the nwfpe emulation, which is ancient binaries that used it as part of the old floating point calling convention; that only uses loads and stores of 32 and 64 bit floats, not any of the floatx80 behaviour the original hardware had. We also get the nwfpe float64 default NaN value wrong: https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166 so if we ever cared about this obscure corner the right fix would be to correct that so nwfpe used its own default-NaN setting rather than the Arm VFP one. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5fbc953e71e..9f913ce20ab 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -227,17 +227,17 @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status) floatx80 floatx80_default_nan(float_status *status) { floatx80 r; + /* + * Extrapolate from the choices made by parts64_default_nan to fill + * in the floatx80 format. We assume that floatx80's explicit + * integer bit is always set (this is true for i386 and m68k, + * which are the only real users of this format). + */ + FloatParts64 p64; + parts64_default_nan(&p64, status); - /* None of the targets that have snan_bit_is_one use floatx80. */ - assert(!snan_bit_is_one(status)); -#if defined(TARGET_M68K) - r.low = UINT64_C(0xFFFFFFFFFFFFFFFF); - r.high = 0x7FFF; -#else - /* X86 */ - r.low = UINT64_C(0xC000000000000000); - r.high = 0xFFFF; -#endif + r.high = 0x7FFF | (p64.sign << 15); + r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac; return r; } From patchwork Mon Dec 2 13:13:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9B9ED7831F for ; Mon, 2 Dec 2024 13:38:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UT-0000mc-6A; Mon, 02 Dec 2024 08:29:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gl-0002cA-3v for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GW-0003N9-Tq for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:16 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-385e06af753so1546861f8f.2 for ; Mon, 02 Dec 2024 05:14:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145277; x=1733750077; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y0Xx5AyANaS6WVZhR0dQwQ3Dsfoy1K8k2mwf7TXf+0Q=; b=pn7j5F7MxljhAZcshslSRKChxuW/28uW28iSKscwQRhLg+R2SyiZuoQmoxEWMx6pRR uhIv1Qa7dKbK0EKq4lsnoofjRHHNxdOaKuBD3gqYn+7PZXFsAaFHrmgpbUhn5cH1TOdB ZWtKTGRSBOMTHgz941HE3I+cqtN/JzYyFIaCph1REBVxSvj4Ae2lkc6XxyT2ei94IqCM 52zbtyJs3nGUkrv/V6+hQMAEmx/iylGc0mbjVsOvUS4sUmDeIR1deMVf38zfPK3b9yQ9 2u2vwwHAWfbotBwTmegttbyoPZmY59jfsrV+W2GIAUKbKOU+HS0nyI5WIJVKOcoQHeK3 70wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145277; x=1733750077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y0Xx5AyANaS6WVZhR0dQwQ3Dsfoy1K8k2mwf7TXf+0Q=; b=spUu6StNBS8dYsY1xLvA1uSPzzncYQ/PZiijocBv/s/TA1njmGMo610+sYFtCKoUhK IV+omU0LVvA9ppI8tHwXeTNnA3SlSrVituUqa/8ilyhJplk23h6imgsE7xgHRMTzp7T8 H+6saVNWmNJUrGHWg1rCmDukWZVpM7uCyaPZsf0PYYrnG5WS2CUB8UJHLn1H1Ozyjafc nq+afNPEiMF0h3wh1usbxe8uEUvWaP/9A16+wFWyZtVqEThGZalFxlgoDJUPQpmAgeW8 WvhL6n2bdP0S0zstun261SqAE8udqhXSP2jgxC/jkIHDwjvNRzSPxdkGBJEC0tblQg/6 WCpw== X-Gm-Message-State: AOJu0YxGdLBUfnEVGS4OyLBZ6zELne2f4sIDafatHq9bp/zP256ojgQz k+2Db8Nk2JElGzToWwwZ6gTtbqTxnhHrM498sSlJSumwQn2+HrqajOdvaoDoefROkFfQiBu1Yms O X-Gm-Gg: ASbGncvRjVbcyrXDHDVyRZTh8Woo22CtCvnasE3WmXxR7MRtcs1Dmo+4C6evcsZ0X9r jjB8QjmKg/MhTBlmrkoYzoFbHOMm19r6cUmwvvc8FA3Bl1pjMd5WthVh8q0LWGO3GXloLyzVgos MfCHtqpHmPcZF6vJv43Y63oYliMRJCy4tB2oCp5Wyiaq8dHCdbqOsEGxde3U9qaHeTkixGoIWik 3AmBqTTyJ+M593IOp0t8xRzgPmkqP6qn1iyjMndNxofodc23xNQXA4= X-Google-Smtp-Source: AGHT+IF7/dDg8KXtRoJE3fE/ctSGSHBQI+1um0ZFXkjxt7vXDSSfH94Og34g1HVsiH7CtOchKtbbog== X-Received: by 2002:a5d:5f8d:0:b0:385:f2a2:50df with SMTP id ffacd0b85a97d-385f2a253a2mr3340910f8f.27.1733145275906; Mon, 02 Dec 2024 05:14:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 29/54] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers Date: Mon, 2 Dec 2024 13:13:22 +0000 Message-Id: <20241202131347.498124-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass a zero-initialized float_status struct to float32_is_quiet_nan() and float64_is_quiet_nan(), with the cryptic comment "for snan_bit_is_one". This pattern appears to have been copied from target/riscv, where it is used because the functions there do not have ready access to the CPU state struct. The comment presumably refers to the fact that the main reason the is_quiet_nan() functions want the float_state is because they want to know about the snan_bit_is_one config. In the loongarch helpers, though, we have the CPU state struct to hand. Use the usual env->fp_status here. This avoids our needing to track that we need to update the initializer of the local float_status structs when the core softfloat code adds new options for targets to configure their behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- It would be nice to get the riscv fclass_s etc also not to use a stunt float_status, but plumbing the env through would require fiddling with the macro magic, and in practice for the is_quiet_nan functions it works out OK. --- target/loongarch/tcg/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index 37a48599366..aea5e0fe5e6 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -359,8 +359,7 @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj) } else if (float32_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float32_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } @@ -378,8 +377,7 @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj) } else if (float64_is_zero_or_denormal(f)) { return sign ? 1 << 4 : 1 << 8; } else if (float64_is_any_nan(f)) { - float_status s = { }; /* for snan_bit_is_one */ - return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0; + return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0; } else { return sign ? 1 << 3 : 1 << 7; } From patchwork Mon Dec 2 13:13:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BEFDD78320 for ; Mon, 2 Dec 2024 13:37:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6YZ-0000tQ-Tf; Mon, 02 Dec 2024 08:33:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gv-0002lE-Kn for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003My-Ho for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:29 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-385dbf79881so1912366f8f.1 for ; Mon, 02 Dec 2024 05:14:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145277; x=1733750077; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qFtiFfBBznBZexAeUlFNfBbsHlolyVwbUxMya82sU1M=; b=atwcCUNsmOBDsC+M+FRdwBqZuSxxilKsxhyx5LOt69Q7s8YaHAoFxWhy/Bsr1nmR0b BrKqXH5OfJZ1cLtkBgomZ8FCTi5Eu9C/Wwx3qC/4vqtD/yyDKnzP7juQhqG3YxoYNSZM CeBXUeesd89xBO43byd1Gk2Wico5Y8WqX9AIMxuXeIg9J4YexPHZyXTZsHWdiefizjr6 /VExT/T4E1/tXt7p/wz9+qvmkHWWm305+pJ523HjHxI3Mlg+0IJiEcgVPDwqcUYLL4qz yoQQEb+ZDGozAHDnlMsrW+OJg8CZdWqvsuePIm2Zz0KPI31n7zEZOdPKwf2GKnmU3bM1 8RBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145277; x=1733750077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qFtiFfBBznBZexAeUlFNfBbsHlolyVwbUxMya82sU1M=; b=CfrnItUHRMUgjOTadW6KLrefFL+7wxD9DnrRhv4SlwOU7uVA8DzcT8cMbJDvhifjgp 2fKQjxTZiTl45d80fZguai3KL/oX39xXoLzF9PY13daL4mJvXri6eIeSmP/8uEAK375O 9ovuCVTnsdDHcajWQjTfzU/QnHqNsY9WkNXOnhvZDaTsLdYFNQN/89An9aIorN1CybHK UyRvr0bELTjs3jgBJ1lMTtmjua19jDIo0y5hLqde9ebqlo0pzQn8u+Z1t6jZXbbEQncV MAGpLtIuslzITZ/5LkTgcyJQoH4Wty7WdOTZNfWJFBuaf+a9UXzwz6+8wUjw6LsSBme0 wTjA== X-Gm-Message-State: AOJu0YwT4tm5wJloGQ9HTZaV3MaUD3ChbCc9VuzDetVkdCh0Lxoq5FSy 36dsVMygbDKeEVBVGPC/OAhmUQbXbG5w2JoK93m1IJPNJlA/lM1MA0LD9UEC2x42JDIMvi4bL86 7 X-Gm-Gg: ASbGncvF7Ervm/lKte+33xDeN2KmpM0+A+/vKl/fmz9YTNN2b40YI/iHlV/YG8vNCFG tW30wcuiyaGfq48Idb/QPzgfYgrIlNHcTVFbB21o9u0Z0N5iVpNrHpzFH+FfUH4FN8N9YudpZM1 40LdJIeJL+YOpgpzAyS6ji1R8q2J1N0K2WuAJEn/Q/JpX//kveD9PEZOidhTOUDGuTPt2642jT5 hUoaPYgiqnzyviTwl0imlp0LcFdjuYL1jylPB1QIGCfaBCXWm0A2RY= X-Google-Smtp-Source: AGHT+IGjX11e3JO3ZTyjG7BP/tYm806Bq6OhPURR2FI+K91cwS7FWrHu5iiVUqs5CI0AS29PsM5q0A== X-Received: by 2002:a5d:64ed:0:b0:382:444f:4eb0 with SMTP id ffacd0b85a97d-385cbd7c36fmr16352829f8f.13.1733145276812; Mon, 02 Dec 2024 05:14:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 30/54] target/m68k: In frem helper, initialize local float_status from env->fp_status Date: Mon, 2 Dec 2024 13:13:23 +0000 Message-Id: <20241202131347.498124-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the frem helper, we have a local float_status because we want to execute the floatx80_div() with a custom rounding mode. Instead of zero-initializing the local float_status and then having to set it up with the m68k standard behaviour (including the NaN propagation rule and copying the rounding precision from env->fp_status), initialize it as a complete copy of env->fp_status. This will avoid our having to add new code in this function for every new config knob we add to fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index a605162b71f..e3f4a188501 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -615,15 +615,13 @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1) fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status); if (!floatx80_is_any_nan(fp_rem)) { - float_status fp_status = { }; + /* Use local temporary fp_status to set different rounding mode */ + float_status fp_status = env->fp_status; uint32_t quotient; int sign; /* Calculate quotient directly using round to nearest mode */ - set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status); set_float_rounding_mode(float_round_nearest_even, &fp_status); - set_floatx80_rounding_precision( - get_floatx80_rounding_precision(&env->fp_status), &fp_status); fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status); sign = extractFloatx80Sign(fp_quot.d); From patchwork Mon Dec 2 13:13:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA45FD78322 for ; Mon, 2 Dec 2024 13:40:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Uf-0002Ac-Mn; Mon, 02 Dec 2024 08:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gq-0002ht-6X for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003NV-4z for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-385dfb168cbso1805752f8f.1 for ; Mon, 02 Dec 2024 05:14:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145278; x=1733750078; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F9P3Zyg8EWDd8Ipp5Pjnvse0G07D293rwdAJ1WyzXl4=; b=K3Uar6D9jDn935gVUS/K3XuqOaAeoIE9Y08KA8se4kghYofFPzypz9slIGW/2US56A ZrpK7Bc06XUuVWPlIOm6cyU609T90o2vM1aofBHBDbYovnokHZ+5wR3fpTdxr3Oqb2oz XM0CEignuPdU/54AZuIA/OEfg8FsNYngNh7hmDmLalUJiCQWAqe4JHx9xNNQoAsTE9jp P6yfzk8gp9ZxQ0WKj9DYCWxZlFcjaiaz1a/rwxTx86jjA2y6d/EACPXuSlXZz5Gv5pf3 /uZITmIizSGKkapFvFEsSpmuotbGjyO8O8302nWVqhJ24sRbmMdCSdHY66sCQNA1KjBj f6Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145278; x=1733750078; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F9P3Zyg8EWDd8Ipp5Pjnvse0G07D293rwdAJ1WyzXl4=; b=G3k4+LE4O84JIj18LHCVDQO13fZ2p04dpDryjkIYRTQaI5R5xAAOYLbbK5Ltd43u7O gbWXw3EO7bsjPFH790UA33DiO0xVXFoLcQUX+8A3AkmHgaFQTNGnC3cVd2OooYN1/CFv 8qmPzLGZLPOq/aepIGu+aO4yWu+SpXCPri48zrGQvcjgcS8P6jPheSAa0krY6Tk9sWNw QIfVBxYgEJ5zla1s6f08JS8+BDZK6KvarwxmQu/4R+UtjoGWFc42GO07W4j14drxT52V rtVex2hAKVz/HX+ftJFc2ouriMkZyLijOy3OdNbCbPLb7xAzetGAUyjKnOR18bEQfoCl +QJA== X-Gm-Message-State: AOJu0YzCZJ/1Ti1ROUapG8VqtjDEGdWabgiamZ3hg/n4RJuW19K6Spsx tAxrAESH9TrPGN3BGviSRhEr5hN7GVaLyAPEDz6nEHTHIFh8/eDa3QTAOKohbKhkJ62OhcnkpF7 n X-Gm-Gg: ASbGncuhr+YknIozkoe1UKauNvieSeb+c287oTDCQTjmFGNylqE1EKNO839urbwRpK1 zS+eT+1nkm1xb4Q5K/c9qI1FG82ZBWZFJNYBklD/HqIGYH0bnC104X/zrzR9XL96mkzNAO5hRG2 j4WkKvIZkzdrrIBFf/ipxgk8e9Vyg20XqS2JhgwoGtc+n2+uz8dhFSrKjElQTH+ABa0Cglpl6/w 53oseBm5Xe4AeZ35E1x4xmq9zPq0ESRlUJe9QDI1q8aTVJDXY05GjA= X-Google-Smtp-Source: AGHT+IFL61A+tairJzPOItayh6olQ1F+IieedrTB8+3a6uLQVDTHerrpGpRDJzdWMxXPxCl7i8SUAA== X-Received: by 2002:a05:6000:2d04:b0:385:e30a:394b with SMTP id ffacd0b85a97d-385e30a3bdcmr6032714f8f.16.1733145277754; Mon, 02 Dec 2024 05:14:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 31/54] target/m68k: Init local float_status from env fp_status in gdb get/set reg Date: Mon, 2 Dec 2024 13:13:24 +0000 Message-Id: <20241202131347.498124-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion from float64 to floatx80 using a scratch float_status, because we don't want the conversion to affect the CPU's floating point exception status. Currently we use a zero-initialized float_status. This will get steadily more awkward as we add config knobs to float_status that the target must initialize. Avoid having to add any of that configuration here by instead initializing our local float_status from the env->fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c0..beefeb7069c 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -36,7 +36,8 @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s)); } switch (n) { @@ -56,7 +57,8 @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) CPUM68KState *env = &cpu->env; if (n < 8) { - float_status s = {}; + /* Use scratch float_status so any exceptions don't change CPU state */ + float_status s = env->fp_status; env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s); return 8; } From patchwork Mon Dec 2 13:13:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6EFED78321 for ; Mon, 2 Dec 2024 13:45:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Xv-0007yG-5Q; Mon, 02 Dec 2024 08:33:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gz-0002xO-6V for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003O8-Kx for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:32 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-385de59c1a0so2908487f8f.2 for ; Mon, 02 Dec 2024 05:14:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145279; x=1733750079; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bcSQWPJxoEZ5kc/cEyAZreOowNhccL15M84TKXenqM8=; b=ufE9gu07u4hBlYTwM6ro/Qm9bYhR3BuzYPoAnfhh99VkBl42BZapp5Xb/L2947EmWB qiSPVHaTyy6uDmRJukQwkfQgObm6Ec1jIp6umBCCVxJ4AR0EOSGse/VU3kt0PZnHQVae paZqs6Uq9Z2PNAZm5usC/EDucOIu2UU/pK1t08npRA543/oikTQ6N5EH7ZFPISJHbl6M pdpMh0kH4yDLaIza4n/OwL3OFgkf3GuKYZ3sQ+fI+vQJuPEZtN3Csz4CFqdOO6hA/CoV qsCbDUxssjBBX+SI3KNlVaINKomfPSxeZ15+qsPFLJkRrBSLEdMWXQd134OuX1C4+9eB xYKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145279; x=1733750079; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bcSQWPJxoEZ5kc/cEyAZreOowNhccL15M84TKXenqM8=; b=FzJz3aOfTPAlut1zhSI8LBg1CQADHOFnhg3/TmIA5I5lwuRCBunS+q/bqP+6oisU9N YtbjEbhYPvoyg5Qmb2yXMAruadAzOzayQ8Z4ikmxiUNNSEHT1VvVA5+MNzUhhXocDZUJ CLxlFiW3mFueBDTOVcgGOximNq8WBPEWKO0uccCDmHOjI3HoOcRWwaXsB0gDXOSE6tWu OBTd4CQMPdF4H/nSDWITZo+NavWSDdn9HZSDJIqQP9McUdLn6QoM+8QKNbRtYbBrQQAs LIfYmr4VxwYYYbw7FzcZuqKJKz5mDEZsMpgkCxUPimHR3BEo8LcE+rxuMuF7+kTbBesl VbSA== X-Gm-Message-State: AOJu0Yy20NTX1/XoZK2NW7qrJCw/cxIrxlIKn/gAXaqI3934Qd54yZa2 Ok1XWgdTkxhdWqPcwmqFethMTt/LPzaJhKtvqIQzrt3U61D5BZzrdx+tEXsSHcOJsq2etUWlI7U A X-Gm-Gg: ASbGncuAlmQ5hTeU4wgq4CFHUMc55ZZ7zb8Jl7WlNUjTVtYL4qrDEnS9WtmOIt8PsOQ s35sco4CcqKVjB8ac90E6CpKyRG5y3xY6kapfiamFVlHG1KBtwm0dYf89qAqZi06CmFrPMqX5A8 yJfKHL8LQUwKYEQ4jJ0FamXqV+cYhYbHo/oqh0FiT/J9+z4PGL2UyU7hZYukyTOonVv2lktA/l4 L+X1JFT7JUO4htwbidAQHa4a/pLbIzT5pO7brrFybbGngTgfV3DFDY= X-Google-Smtp-Source: AGHT+IHr1vI+MOZbtPkNYb3mNUy7gWjvLx38mjS4L3RplG6H9NCgwOtAH784x77t7dH5oedV37mDOA== X-Received: by 2002:a5d:6d8e:0:b0:382:4b2a:4683 with SMTP id ffacd0b85a97d-385c6eb84c3mr21557497f8f.2.1733145278737; Mon, 02 Dec 2024 05:14:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 32/54] target/sparc: Initialize local scratch float_status from env->fp_status Date: Mon, 2 Dec 2024 13:13:25 +0000 Message-Id: <20241202131347.498124-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to explicitly initialize settings like the NaN propagation rule or others we might add to softfloat in future. To do this we need to pass the CPU env pointer in to the helper. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 134e519a377..1ae3f0c467d 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -51,8 +51,8 @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128) -DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32) -DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64) +DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64) DEF_HELPER_2(raise_exception, noreturn, env, int) DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index 6f9ccc008a0..236d27b19c1 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -490,13 +490,13 @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2) return finish_fcmp(env, r, GETPC()); } -uint32_t helper_flcmps(float32 src1, float32 src2) +uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2) { /* * FLCMP never raises an exception nor modifies any FSR fields. * Perform the comparison with a dummy fp environment. */ - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); @@ -518,9 +518,9 @@ uint32_t helper_flcmps(float32 src1, float32 src2) g_assert_not_reached(); } -uint32_t helper_flcmpd(float64 src1, float64 src2) +uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2) { - float_status discard = { }; + float_status discard = env->fp_status; FloatRelation r; set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cdd0a95c03d..322319a1288 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5584,7 +5584,7 @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a) src1 = gen_load_fpr_F(dc, a->rs1); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 33/54] target/ppc: Use env->fp_status in helper_compute_fprf functions Date: Mon, 2 Dec 2024 13:13:26 +0000 Message-Id: <20241202131347.498124-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the helper_compute_fprf functions, we pass a dummy float_status in to the is_signaling_nan() function. This is unnecessary, because we have convenient access to the CPU env pointer here and that is already set up with the correct values for the snan_bit_is_one and no_signaling_nans config settings. is_signaling_nan() doesn't ever update the fp_status with any exception flags, so there is no reason not to use env->fp_status here. Use env->fp_status instead of the dummy fp_status. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/fpu_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 230466a87f3..d93cfed17b4 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -155,8 +155,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \ } else if (tp##_is_infinity(arg)) { \ fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \ } else { \ - float_status dummy = { }; /* snan_bit_is_one = 0 */ \ - if (tp##_is_signaling_nan(arg, &dummy)) { \ + if (tp##_is_signaling_nan(arg, &env->fp_status)) { \ fprf = 0x00 << FPSCR_FPRF; \ } else { \ fprf = 0x11 << FPSCR_FPRF; \ From patchwork Mon Dec 2 13:13:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42D1ED78320 for ; Mon, 2 Dec 2024 13:34:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UY-0001Os-34; Mon, 02 Dec 2024 08:29:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gv-0002jQ-SQ for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003Ok-Fj for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:27 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-385eed29d17so794146f8f.0 for ; Mon, 02 Dec 2024 05:14:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145281; x=1733750081; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yKV708lbVufub1eS0i2nRrYGl0qdKJsRNu5HvpEXaMM=; b=limuPtMsqKdefUjQNTmRKUjAfc4lUDIGStfKIJHTgerxmEhPGku+ZFJKbNcPhIbX73 xN6/un/uRBj/4EN1xsQm6mZ/UYqZTW9IBIcxOGhRvyLaS2d9It2B+StnIBR+6he8Ew5J aeMPCkd+HkFP8XXsT4hh0i5CxSYHOuSLa58k2AEV8nWWlvdzJXIZDl/+zM56ahDdRerk ZXzDZAla1dLK7l4YEYOWy/InULIuXhmAzR4FNbmgSHW04saYOH6rP3mvqNzW9G/bOoYW 9JGsFv6lxHdFmy+TIh+5LyKZgTOj3Luq451N2kr9M8lORPeF9w4D4yxXoDXVhL4aiUml zorg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145281; x=1733750081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yKV708lbVufub1eS0i2nRrYGl0qdKJsRNu5HvpEXaMM=; b=AlT72e2kbkbCXISUxBJa4lveJfxfVlVcce+SmHwavJNDOYU/+oma5o2n+SsOJoOsWc A7CKINh7H/2rr9tdAwB7LFOHXlRCnD9Hhw8BpczBPh/+V4VaxmeSJLRgaah/Sbz0g2+U CU1Px2eiNrEJzhExyAGutf2v6TpJ7+LSUE4a3ncBak6WBSMklewQJTEGM6bciJuDFMZO EeVzyy3i1/VJJpDSDYiCpSIQGMsB/p4ce6vDtbUuoT6H25qtRLVp8xuCVV8H2hZlZKdc wn5guZPxOjx2Kos9rtk2NVTekTTdI+N8U/XzhfSdljL3gMHAvUwubmEA6zLIlyKkAriH z85g== X-Gm-Message-State: AOJu0YywJi1f6ZUYvZFL8sj2QRMufUusFm/huClgVt8wjzibGFVzoD7T GofiF82jSRQtnCWZC+B+k+R3lDXTuPrlQ6LkscQMmRbDLa9fUt/gNwQicwTAiMotcQsrwlQbwkB I X-Gm-Gg: ASbGncs/7csB+xz7prkPR4l+vZuxvyR9hcKovkJFNEfZpoM1XTZVarBUrxEF70VfPaw 5YNHOU8TYCuWnrNm+RcTPj3YFX58vYmR3d79pvx+g5LuyNRXcwTdIYbTnCxmTCnsTD/aktqDsi0 Jt/WgxJpj9LIHBplZrE90s50hOcNA2KWsbr8XJhQsL4y7tYXww73jWJLcyXKclUsEOBdadGYjXe FjUu6BcV6IYbVldTeFtJGUE2DKZ2TkgivSSES4I436oNdidg9Z3Gbw= X-Google-Smtp-Source: AGHT+IFELuFkVQJehEVSKgoZXY73udDUueU5hfLBaI5Ys4CGnWxhP2s0m/NuLhCYSvhKN/52NWLe5A== X-Received: by 2002:a05:6000:42ca:b0:385:f0dc:c9fd with SMTP id ffacd0b85a97d-385f0dccb93mr2451898f8f.27.1733145280733; Mon, 02 Dec 2024 05:14:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:40 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 34/54] fpu: Allow runtime choice of default NaN value Date: Mon, 2 Dec 2024 13:13:27 +0000 Message-Id: <20241202131347.498124-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit is different) Add a field to float_status to specify the default NaN value; fall back to the old ifdef behaviour if these are not set. The default NaN value is specified by setting a uint8_t to a pattern corresponding to the sign and upper fraction parts of the NaN; the lower bits of the fraction are set from bit 0 of the pattern. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/fpu/softfloat-helpers.h | 11 +++++++ include/fpu/softfloat-types.h | 10 ++++++ fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++------------- 3 files changed, 54 insertions(+), 22 deletions(-) diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h index 10a6763532c..dceee23c823 100644 --- a/include/fpu/softfloat-helpers.h +++ b/include/fpu/softfloat-helpers.h @@ -93,6 +93,12 @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule, status->float_infzeronan_rule = rule; } +static inline void set_float_default_nan_pattern(uint8_t dnan_pattern, + float_status *status) +{ + status->default_nan_pattern = dnan_pattern; +} + static inline void set_flush_to_zero(bool val, float_status *status) { status->flush_to_zero = val; @@ -154,6 +160,11 @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status return status->float_infzeronan_rule; } +static inline uint8_t get_float_default_nan_pattern(float_status *status) +{ + return status->default_nan_pattern; +} + static inline bool get_flush_to_zero(float_status *status) { return status->flush_to_zero; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 84ba4ed20e6..79ca44dcc30 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -303,6 +303,16 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ bool flush_inputs_to_zero; bool default_nan_mode; + /* + * The pattern to use for the default NaN. Here the high bit specifies + * the default NaN's sign bit, and bits 6..0 specify the high bits of the + * fractional part. The low bits of the fractional part are copies of bit 0. + * The exponent of the default NaN is (as for any NaN) always all 1s. + * Note that a value of 0 here is not a valid NaN. The target must set + * this to the correct non-zero value, or we will assert when trying to + * create a default NaN. + */ + uint8_t default_nan_pattern; /* * The flags below are not used on all specializations and may * constant fold away (see snan_bit_is_one()/no_signalling_nans() in diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 9f913ce20ab..b1ec534983c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -133,35 +133,46 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) { bool sign = 0; uint64_t frac; + uint8_t dnan_pattern = status->default_nan_pattern; + if (dnan_pattern == 0) { #if defined(TARGET_SPARC) || defined(TARGET_M68K) - /* !snan_bit_is_one, set all bits */ - frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ + /* Sign bit clear, all frac bits set */ + dnan_pattern = 0b01111111; +#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ || defined(TARGET_MICROBLAZE) - /* !snan_bit_is_one, set sign and msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - sign = 1; + /* Sign bit set, most significant frac bit set */ + dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) - /* snan_bit_is_one, set msb-1. */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); + /* Sign bit clear, msb-1 frac bit set */ + dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) - sign = 1; - frac = ~0ULL; + /* Sign bit set, all frac bits set. */ + dnan_pattern = 0b11111111; #else - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* set all bits other than msb */ - frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; - } else { - /* set msb */ - frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); - } + /* + * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, + * S390, SH4, TriCore, and Xtensa. Our other supported targets + * do not have floating-point. + */ + if (snan_bit_is_one(status)) { + /* sign bit clear, set all frac bits other than msb */ + dnan_pattern = 0b00111111; + } else { + /* sign bit clear, set frac msb */ + dnan_pattern = 0b01000000; + } #endif + } + assert(dnan_pattern != 0); + + sign = dnan_pattern >> 7; + /* + * Place default_nan_pattern [6:0] into bits [62:56], + * and replecate bit [0] down into [55:0] + */ + frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern); + frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1)); *p = (FloatParts64) { .cls = float_class_qnan, From patchwork Mon Dec 2 13:13:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D6BCD7831E for ; Mon, 2 Dec 2024 13:32:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UM-0000KD-1Y; Mon, 02 Dec 2024 08:29:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gk-0002ba-R5 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GU-0003Pw-Oz for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:13 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-385deda28b3so1803830f8f.0 for ; Mon, 02 Dec 2024 05:14:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145282; x=1733750082; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q4IQwxgZ7TI3dnLUr9pZJR/1M5zZVOxtymkRhBauZGw=; b=CSpOnLhuvj4kwUVJp24vBJYuYpF0EPgcpxPxaa1oUdWi9iaa64+ojm/S99MUc8QHTf lOVQQkusszuhuduHC79u2wmH/MDovhRx05YLxMS+4y3ZpBnBc5Z2MY/PI6wLTxKCx49Y AWAS2iXYKDLJYw/QRFhIpT5M+THngxFoUy+EtiuBE/Qxei0KEjfs4J6drnQ19AaccVgN ww9/r5E3vj+npmEiOYjBZUtKQcTqsK4kVa03PQxnpEUezA/PuPYYru2y7jatvFBWqEo2 /G77x5apnPVBG6DGEfyj2ngFtPW04fNtQoB9yvS26kL/gAkYZs1iaqHRGqrkNm/KPij1 EQ2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145282; x=1733750082; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q4IQwxgZ7TI3dnLUr9pZJR/1M5zZVOxtymkRhBauZGw=; b=nM9jeF7gaVPGCTyCoPM8PTwga7RBdT6z9ZJY9mK+XxnOBjWEMWTT5e+Ol7+/fTYnZg J/1/K29s7r1wcxMdXng6GBlakek/l8aLqVutX+fL8hfjGBdptjcPAB+/AON0uwylNyjT XxHn5nBkzSoVXgZuZVfN5qTGhWjK/K9WeiS3DVGXtcDsOvcA8Uce1roJSiLX4zLzF2ne uUHJQM79cdreEMaXStmRxw75BqKc8gjv/U9d2aWpquLiEcgdk505b7RSmUTrt1mMth39 9H5hZ/hqrauyh9MyUCgfoGa+ffuSwFQ/T4HzWXP69X6vCKqUeo6ld6FB/VH3BsN56P9+ ZISQ== X-Gm-Message-State: AOJu0YzWqsN1/vGBbeK2z/hMTDyb07s7+0tOM7lR43p3iZLhglnGMQq4 H9MhjjOAFK0ZWT2N5yXv1JacDcQZdddZeeRJxlw7eOt9AybJLsv0XnnhxGZbQdRIwmHlWlWak6t 5 X-Gm-Gg: ASbGnctrX4boBj344jn3z9EDc6EDd5wfYRyes8P4ReWZIo5FgpJiwEsrcTGSwuC9iub Hk9QkF9jhv6p8RnGEXPDDAA5UhIkTl6/7tSvDE/D//IePjs1avsgWRFlZU1QKPm4xmQtW7xBlpC KeEfRkXyg410XpsXbNoFMtPZm9h75x55tS8ttOqfEeYOyhkHcP/DKqSlIl33EtEPXkIgTm3l2bV 8ZoMb88s4XDHrQwUQ0rheaAI58zu98iD1kyzzODAAYW4Ob+lO9BnOw= X-Google-Smtp-Source: AGHT+IGBl63lSMExmDzDmz56Hi4ps6ZYUHjIAloYoP3kfaZz4pTVN4il5atAGH8qHrWm3IohWUeDQA== X-Received: by 2002:a5d:64c5:0:b0:385:f7b2:aadd with SMTP id ffacd0b85a97d-385f7b2add6mr1499818f8f.41.1733145281644; Mon, 02 Dec 2024 05:14:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 35/54] tests/fp: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:28 +0000 Message-Id: <20241202131347.498124-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for the tests/fp code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 1 + 3 files changed, 3 insertions(+) diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c index 39d80c9038f..eacb39b99cb 100644 --- a/tests/fp/fp-bench.c +++ b/tests/fp/fp-bench.c @@ -495,6 +495,7 @@ static void run_bench(void) set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status); + set_float_default_nan_pattern(0b01000000, &soft_status); f = bench_funcs[operation][precision]; g_assert(f); diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c index de702c4c80d..79f619cdea9 100644 --- a/tests/fp/fp-test-log2.c +++ b/tests/fp/fp-test-log2.c @@ -71,6 +71,7 @@ int main(int ac, char **av) int i; set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); + set_float_default_nan_pattern(0b01000000, &qsf); set_float_rounding_mode(float_round_nearest_even, &qsf); test.d = 0.0; diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c index f290d523ab1..c619e5dbf72 100644 --- a/tests/fp/fp-test.c +++ b/tests/fp/fp-test.c @@ -941,6 +941,7 @@ void run_test(void) */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf); + set_float_default_nan_pattern(0b01000000, &qsf); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf); genCases_setLevel(test_level); From patchwork Mon Dec 2 13:13:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 05897D78321 for ; Mon, 2 Dec 2024 13:41:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6WC-0005MT-17; Mon, 02 Dec 2024 08:31:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6HB-0003In-CG for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:49 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003QM-US for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:37 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-434a1639637so39752815e9.1 for ; Mon, 02 Dec 2024 05:14:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145283; x=1733750083; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eg5CLJnIGFMP+7pRukJjMkkCwPMh6g96Ep2h3Ltgz5o=; b=SHxdBlKI8lzA4bdclnx97YqShFw4jmFeVRkc/zNKmeT46cQx+gf2pKYwkF1u2FXCnQ YRRf46LVK4PSc31Dnx/yHqvCBAxr4Fcu/x0i9Kc5VXv9xH1I3SVB0biq7/UiHkp5SGw+ tegqU/XkeqwZ84h16maHbo+68tQx9jTMNlfRhdZeyPuLInilfzk8IKsVbEU/dGvGAL2t TUeMek1wjGS3NxGUp5HYv6y7M1A63gvxl4vq3RFdGQiA3cAUhPwTkwcXTLxjd5EjVeM6 mc3CnIJMnDfomHSdqs2jLCe7A1O4F2bca1dSboyJ1syh9xr4ViRDF05fDtDpHH9vywDp c5Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145283; x=1733750083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eg5CLJnIGFMP+7pRukJjMkkCwPMh6g96Ep2h3Ltgz5o=; b=aBfUC++Hb9qEr9U621eN6hpEhyn8jz78Qh9GL7/HS3czUX+Q84hx4MgV89eJ0GnDZ3 Q06pgl9pq5ZUBzmqVF+iILeQr/qB84e+lCbGkrfi8Jq3I3QIPluKG2RfgtPHNhDW4Yrt vGlMbHoi9meG+RQAeHVxY4+WPWASffoobde0+QoHcmP8JjYJE8w8DXlSLXptVB8W/q/A oB4DJWSlds7xjUeqNO1vbLAet2eFwI+PU7Bx+JEn+95LYcZuPFA3gxd+G72+sRPReBzw r3zabQV4rpnW7Xde+Yb0MiJdZtcsW+l0qPcQ1EUrIFz5RmZJnio64htoMy8TWNq75utT L1RA== X-Gm-Message-State: AOJu0Yz8t4HPiDj5Dt1ZieUjav4i1PzzKDwITxX04bbA7TkUY//XOGtv /hR5salh2pXTsbpY45YbeNNLf6yOCy6t+PnPkCQBAZOnF/5eWLWTcUzIkvfwsb4ktPwmu2agz/J 5 X-Gm-Gg: ASbGnctPkkHxfZ87L0S7q7YRcsYRxiHer9+JK8Nsx5GR8t+PijsZbvUsj2bcjOhlmWa Uan85b3XP3ToEQV8TpyH0VBLBSI1cU9RVPBTCviycQbUayjtejp+Yo3lSlPPYw/vNkwRFgiBBGE 4lCYQeTkrRz93BFpJvan0yIu3LUlAt2YagwNA6G5GIibbjm6vveQdGRcLTxFcfHTntAQWALvNlZ J1czAswliVLuwzgZl0qbarHCxY1n/JtAHPNrePKm6HWWhqGsn1/tQI= X-Google-Smtp-Source: AGHT+IGmlpAUQ7RrQZuvyRgb2/PxGBA8A9Osg4UR1KnKKv3AR4gZEx/FzXh11xp1F7xPsGgXaZ4/jQ== X-Received: by 2002:a05:6000:1865:b0:382:4a3b:5139 with SMTP id ffacd0b85a97d-385c6ef598emr19334141f8f.59.1733145282505; Mon, 02 Dec 2024 05:14:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 36/54] target/microblaze: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:29 +0000 Message-Id: <20241202131347.498124-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/microblaze/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c1..0e1e22d1e8e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -207,6 +207,8 @@ static void mb_cpu_reset_hold(Object *obj, ResetType type) * this architecture. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) /* start in user mode with interrupts enabled. */ diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b1ec534983c..d77404f0c47 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,8 +139,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) \ - || defined(TARGET_MICROBLAZE) +#elif defined(TARGET_I386) || defined(TARGET_X86_64) /* Sign bit set, most significant frac bit set */ dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) From patchwork Mon Dec 2 13:13:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E2A9D7831B for ; Mon, 2 Dec 2024 13:27:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6P7-0003j5-AQ; Mon, 02 Dec 2024 08:23:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gb-0002LQ-UU for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:16 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GQ-0003Qj-SW for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:09 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-385dbf79881so1912459f8f.1 for ; Mon, 02 Dec 2024 05:14:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145283; x=1733750083; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TSWsGbiJd5nUa8W+i0kSSd0cIwA3gG9T6rGPFTmCLJc=; b=WnjytF3NooAy6XpfmW7L2oLdbLXngZbkxTBTDzsTFiQ9KHcf0FG1TL9cUcamg7ERFF 3CK44fQMvE3c0ggWYjzCCJ9LeNcIW2Aht2r5814oStVZvWc0HuZsTTMl9S2ZIPIHIW+S pa/wwYO9Zn88mxZ26/c7I1IJlrzbl2DxZFpWHoCOxcrjQNFjkmCJzjHBayUcyWhF4QhK NZqPSFEyZnJZSdA6Y0BufzPDSktA+Kr7GSiWap4Tk10fGZ74XgahgvHUmA+pVh7cbJKP 40Bn7qscr8euYwGBiXGw/pdFqASeD6biQQ54gp/GCPBdnFC9fjpAwpd422T/VaOdw7IX /Qcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145283; x=1733750083; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TSWsGbiJd5nUa8W+i0kSSd0cIwA3gG9T6rGPFTmCLJc=; b=LAC7LZ59npCq92Bp8fCMKLcsakzIJ8/3eIRSOggq09rHvhHWjgDWsnQKdf6LfZoIG6 /pOHorCBN8qlBoukSc2BLEzLj8TK85R8AG3scSdn2nL8GfyzuzS/TLvbC9Ol8KRjDG2D bdmE65LrKvUYviXvSA6EbOQ7Do5kAufJzwJ7WvPYesokBHy/7m9FG1FTsvzKgrlhEyMn gVjzT20F/29PiHsFF+scN+nBCV905EmzPpo7Zz0EJpttgkKJ51CudnfJQhSbWt2o8qjK wNIb18HwFfop9xQmoVkzI3mPkjwtd8qusy1hExdKkP70S0WSFzvESbw7LSq4VM0Piw5i Wquw== X-Gm-Message-State: AOJu0Yx4+redSRBU/jV2FPU7h+MU/VUCMeumpE04CDsqJY5AkOc9X/sL KSIx3bx0LugQrNxcBGc2x8FH7czGNjQZvepsJe7oCUEzGJqf/lAMRXryzO3RFgFqcz62xjDJ/un N X-Gm-Gg: ASbGncv2GkhF4kbOSMBefu0VB/nXysL7yIlPfpNNwW6ZnGyV0RmrrPJDRCMjRCK84en jhRn6ev0OGhJzY8Wa/sWWNEopU7d6EkMprZHTDq2LlmJ9B2kOJUt4Kn2tKjbcBMF7D4rWKwBP0f J1JBLzdFHxTBtNTeNm/2APf7ep70v2QbHXb7Pq2voBuhe3/TyDwmbP8eCKCMOlXsX5pk3FnaoUg jGXRsoWwqlOTxdh9KP5iO35dJLPEqzvDWpwZlkaO/gH7qyjocwTBwo= X-Google-Smtp-Source: AGHT+IHzTpNXZ1PtLUb9+17YAW4kTnA3P4qTzfTKsM34d7nTquK7UvQdp/L/vYqNNTGHVlb3JeXnhA== X-Received: by 2002:a5d:5f92:0:b0:385:e90a:b7de with SMTP id ffacd0b85a97d-385e90abc06mr6148162f8f.5.1733145283390; Mon, 02 Dec 2024 05:14:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 37/54] target/i386: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:30 +0000 Message-Id: <20241202131347.498124-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 4 ++++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index c8bc5b7cfb3..e788fcd1b25 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -181,6 +181,10 @@ void cpu_init_fp_statuses(CPUX86State *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status); set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status); + /* Default NaN: sign bit set, most significant frac bit set */ + set_float_default_nan_pattern(0b11000000, &env->fp_status); + set_float_default_nan_pattern(0b11000000, &env->mmx_status); + set_float_default_nan_pattern(0b11000000, &env->sse_status); } static inline uint8_t save_exception_flags(CPUX86State *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index d77404f0c47..452fe378cd2 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_I386) || defined(TARGET_X86_64) - /* Sign bit set, most significant frac bit set */ - dnan_pattern = 0b11000000; #elif defined(TARGET_HPPA) /* Sign bit clear, msb-1 frac bit set */ dnan_pattern = 0b00100000; From patchwork Mon Dec 2 13:13:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890637 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 02E28D7831E for ; Mon, 2 Dec 2024 13:29:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Rz-0005q9-ST; Mon, 02 Dec 2024 08:27:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GV-0002Ho-2M for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:07 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GL-0003R0-CT for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:01 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-434ab938e37so26680735e9.0 for ; Mon, 02 Dec 2024 05:14:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145284; x=1733750084; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j3RxyO1FT5e89Qph7T+rokhc4ELopzGup08oCLW4wD4=; b=jorZy3HOYx2Ct7ZBr7GRmEY5qyA2sEHqp7uwZmyIbIKyywoXx/RD/Eoi9OegRtsTlU fzUFpNa9rAEgTELd3+azC2Si2+Ctvl7zn32LjEiurHpDIK7sJ/WsxZLlEVM5cU19uN64 LrWw70aAF3rmpJt4PfQsyCF/xkH7A5+YKM3k593Pdios8VchUO8HsyfRgJSvMTfFbzxX x8rThsJOuvfBgdw25c6R5LD0xvxfegGVQ3OyuxLEK1YCVaj0tzQIbmlGNjPZ4jvk4CpB 3lfH9nlJF82JwcC5X0Eg8b89/qSbvvytrPpvDeYcoNQ2YkRgnBIRfosOJAYj5+ZIFBDm bTvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145284; x=1733750084; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j3RxyO1FT5e89Qph7T+rokhc4ELopzGup08oCLW4wD4=; b=Uj+xZywQZnxPsDYC/kOrMjP/RS9tHLrUN9SfVX0jiCeBFTF56qsJfdDWEh7IIe/Z8c u5oL1JERXtY8vuIccrraYH5wo8QmK//ElogwB9e5xcNpC9qG8TBDyKmvoo3FlYwDhP90 aIadpFtfovBM67CavLemnc9Ee6sn5a3riqzOGH8om83DiCdH27ObemTpLht5zteaTYuB 4j/qJMqqpeB3MzARD/g8whgtCm8C/x/Lz1cfMfKBOywoHZs3rAShn1VaXYvAh2QEMclI ieqmW/sgfmy/xyUXTpuqTPr6eRVHYhzml1FQuVYMVVhQyWpLc1hQX5YnT0Bh2E5rLDml 0K5w== X-Gm-Message-State: AOJu0YxjqQq8UJ39YqzI4pLIbf5wSGtCPNhDQtaAWxQvXsIipdMVcJcr XjPwAhUYJQrNWoFuZF2XMEKCFo+UW3A7VkZEgUFB/Lk3xE/ak+yYdZK5zPrvDStcJaI2p1U8q0S x X-Gm-Gg: ASbGncuklCXQq6VHK0FiEWVkIfZQR3hdjRkcch8D//iXAaNnJ7KgyGBKxIRR7BR7JU5 NtMpUf5UnTpdD4vGRiiryH303sHfYux937eCiHdMr/5snZLtmVzgPnOtooTgRv/nQY2wdiu552n xF6auI0lGOOaaLQENwlKmgsyioc+9/XBwT5rxl/MMg/VPh2nETPpWPImHUCcx2Zu8xoH58onO58 1+TNKr6uQDJ6on8SU4L/hCkX4gs9Oq/Bq/70zAtCgQrMxdsPf3xeYs= X-Google-Smtp-Source: AGHT+IEA90ND8eTV2giPp+MwkpvqJJK38DP4tDMh/u88DHbZNoiGJzMtroz6wvzk5/iNtqmnHykbYA== X-Received: by 2002:a05:600c:4686:b0:434:882c:f740 with SMTP id 5b1f17b1804b1-434a9df79e2mr192275555e9.32.1733145284279; Mon, 02 Dec 2024 05:14:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 38/54] target/hppa: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:31 +0000 Message-Id: <20241202131347.498124-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 69c4ce37835..239c027ec52 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -65,6 +65,8 @@ void HELPER(loaded_fr0)(CPUHPPAState *env) set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN: sign bit clear, msb-1 frac bit set */ + set_float_default_nan_pattern(0b00100000, &env->fp_status); } void cpu_hppa_loaded_fr0(CPUHPPAState *env) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 452fe378cd2..b5ec1944d15 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -139,9 +139,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) #if defined(TARGET_SPARC) || defined(TARGET_M68K) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; -#elif defined(TARGET_HPPA) - /* Sign bit clear, msb-1 frac bit set */ - dnan_pattern = 0b00100000; #elif defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; From patchwork Mon Dec 2 13:13:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38C19D7831A for ; Mon, 2 Dec 2024 13:24:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6MV-0000G8-W1; Mon, 02 Dec 2024 08:21:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GR-0002Ga-He for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:02 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GL-0003RY-9f for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:14:58 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-385eed29d17so794206f8f.0 for ; Mon, 02 Dec 2024 05:14:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145285; x=1733750085; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6b67TuxIIuUbvFPYapA8HgByL1UEo/kP+YGdKuHFudM=; b=E9BQ0oLvz5/haQwK9hYar3Z1aHHkAyCDYZYse6aG5RITR1UaActeclATxPah2u3avw jjeEnWo5Vb8c2g+OoKlC9eq1d4I1WzZNETqWghnhHNJ0N+iGzyf5/DwT4Hyj3RN87s+8 HMq2m3JCVPebO65eK5r1e45EL0kHN6j/1LCFvRrdEfVNV8fybujp1g/j/zgyDqwgNHYT 0b9b3sDhYE2Szq2NtZzany7pqd5lnaP1C+0g/X2/GF5Xvpq+W0Dg99dUsKp57UnkLHf0 iaVRNLPUY/UUdOGNQ8KSZvUcehP0vugQ2NVCtOFcg4wezrUDWG1liryWZHNxE/ZnXDrk KcAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145285; x=1733750085; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6b67TuxIIuUbvFPYapA8HgByL1UEo/kP+YGdKuHFudM=; b=pzweqMWoAGeY/IEy6mJeTuCx9Jl1v96HkD0gzWAnOHZEUdk2tczQ8nWSJr8gjnJWKT sqmpgjaDsJNDKq3ilD4OhxLcpE4/edc1C2v/+RoDn2FvX7RTdCYxftkTi/tX2wK5twJ/ cFW1s88Ns8FUKhcG9CWcBEhueT+/0YNGdWL8NKIaGiiibZTGxd1EfFVsUsVG2JjxruKK 7dGcRmbAzJmRfnONfD4jWJhfhgaEUB9/YVRIijtRdQoo0GXpU4T9aS1Y9SzJ0rEE2DfI 2OJVNBIwoEYKX2IBRrmOc2jeRcyRukGocFC78L2D63q8f+IhpbxPw+3HQCaroU23dpON Iaxw== X-Gm-Message-State: AOJu0YziMiIvKakVnbl7xLOs0BeOO46KxSBX86RBt4lexrK9BiO2rlui 3zgtugOS+H3NC3DJDCicdeAp2BTAQKIh0tgGRTqlco/QIqrernlLBJedkkePCvrjH0t5lMCPCtC G X-Gm-Gg: ASbGnct/YeQ/og2FcrpjuF2bfFJ0O7z3o9wK6LQbyWqzZukmdRwdSEoaF1aOmqp+5XU Mg9Rd9pG1HjvAnwnw6SaVFbuXXtb5yFki1C9GCObOzorFmQ3PUSenE3mYIRfnLvycisDYPCfuN3 jERmLwwcrC/ezY1jF6dutWJZq4AQnr1+wXtwbfS/pskIBiK3rZ0shsJeEmVh4NaAz8t2TZMVa/V IqW5eXm3qthQzmEWGxNf2n9Uxr+z43MnZzgKdfiZHoUj7/u5mE8yjQ= X-Google-Smtp-Source: AGHT+IFPP/69/o/8stugJpVepC120rwI93xT8a4bCLYkdFLQeip4Au1UHJnxnRoTijQt5ciXEuHfUA== X-Received: by 2002:a05:6000:186f:b0:382:319f:3abd with SMTP id ffacd0b85a97d-385c6edd338mr21552950f8f.36.1733145285219; Mon, 02 Dec 2024 05:14:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 39/54] target/alpha: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:32 +0000 Message-Id: <20241202131347.498124-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for the alpha target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/alpha/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 5d75c941f7a..70f67e6fd4e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -199,6 +199,8 @@ static void alpha_cpu_initfn(Object *obj) * operand in Fa. That is float_2nan_prop_ba. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); #if defined(CONFIG_USER_ONLY) env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN; cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD From patchwork Mon Dec 2 13:13:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890641 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46FD2D7831E for ; Mon, 2 Dec 2024 13:31:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6PN-0003td-Sf; Mon, 02 Dec 2024 08:24:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GV-0002Hr-4U for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:07 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GL-0003SN-DG for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:01 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-434a45f05feso53403075e9.3 for ; Mon, 02 Dec 2024 05:14:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145286; x=1733750086; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=te7O3NG5V4E3qWDfy7w3qXeqH4l7GoDjlHVXASIpOuQ=; b=poWayr43yRPT4x/xZ3vjV421rAX1L3T7Xf+ivcTu5dyzbGSH3dbVRqJSwfFlNKa/V1 Zc/POjCe0UwaVseJVRkxeNRCAqkNyutD+CoEkVgbeXy6HUIgLF6biu4cvYKTHxQcvOE1 /KBWXHK3/RYWEGC9OrxgL9O7aLE+Nq/MaCKpdweDg/iqmVOtrN1XmeftVuBDDdR2AfmJ +rM/sXyeGNAdMdSTCPQzVslpDdk3lzP3JxTLrxf3878Z7b+sffIEmTSsPJMGrRGWDCTg +/EGO0fSglkl8xGTo9NA/s9AyivdSPSYZWDvmgZATuFVDzITuzAXjp/AU4M3Rt4UCzYj brzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145286; x=1733750086; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=te7O3NG5V4E3qWDfy7w3qXeqH4l7GoDjlHVXASIpOuQ=; b=Um1dc0pOHkcIu2o2d/nBU27a6Vw0GC5yd8G88HCSqAV+tEjjFnOwKhbBfkUoleR99t sZr+eqriFC2BPzwhFp7/Lea0tN/lAyA3Xny3c4REpIIjo96KCEcw6+ma+N7CnUAN9rDy t46PDfMPq85pccQTLpoBGheCjSTd4V2O/G83InSNYCBMKvJfoOCJE9KnVFAFtynMELo/ DAhDB+VwxYFhbA7OqUmEtPyGZjK90tU1D4nxp0W+sOkJf/YLbefOLZ7lTnZHM0clOO4S ycfcboepZpasym7VUrPxGGBh87YLVW9XBg7VA4bsbr3G6+QzEedCDA2NgEvoxPqbLdV8 s8iA== X-Gm-Message-State: AOJu0Yx7lVfIxuCFzIZFeG/ZAPORumptBBah/Mp+RZsdVPIGQfK09F1p p5J6Fbd88aKCyP+CWD7eUJW+itTw7tYWKfMgMyVEShK5xib+79ZfJsS1AIiTIuedOti9zFrxD7x v X-Gm-Gg: ASbGncsrg1uwFWvNmcXpfN7DtiVw880s7oC4OUnTXHn+XodsLh8q606wpOwvF5L4YTD /e6q0XRI5G099WNfUqUFAIMWIMTedTxESt6lcp1Q6CkPSkkXtT2+j1uKx3bGjkdCW0F/6D+3EQF EdIdcVBJO+RAjOdu0k8zSaVm9GUyCKIt7/dcz1XLJMXGBQ78v4DEZXmT7O9tYBsNp/UtJc0j7JD GDqZ4Vh5/GoRtuoXe2jDNmwZXgaZwVchFCmQMFovEWzRd7mg0MgUwM= X-Google-Smtp-Source: AGHT+IEf4KTr6rXhAChzMFWXIj3WaT/CW+XO0OVRZDhylwrcuGoh4UWwf4XfaI2ZSMeNI4wXvw5KjA== X-Received: by 2002:a05:600c:5021:b0:434:9fac:b157 with SMTP id 5b1f17b1804b1-434a9dc37aamr253794695e9.13.1733145286002; Mon, 02 Dec 2024 05:14:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 40/54] target/arm: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:33 +0000 Message-Id: <20241202131347.498124-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for the arm target. This includes setting it for the old linux-user nwfpe emulation. For nwfpe, our default doesn't match the real kernel, but we avoid making a behaviour change in this commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/arm/nwfpe/fpa11.c | 5 +++++ target/arm/cpu.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c index 8356beb52c6..0f1afbd91df 100644 --- a/linux-user/arm/nwfpe/fpa11.c +++ b/linux-user/arm/nwfpe/fpa11.c @@ -69,6 +69,11 @@ void resetFPA11(void) * this late date. */ set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status); + /* + * Use the same default NaN value as Arm VFP. This doesn't match + * the Linux kernel's nwfpe emulation, which uses an all-1s value. + */ + set_float_default_nan_pattern(0b01000000, &fpa11->fp_status); } void SetRoundingMode(const unsigned int opcode) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c81f6df3fca..4f7e18eb8e6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -179,6 +179,7 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, * the pseudocode function the arguments are in the order c, a, b. * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, * and the input NaN if it is signalling + * * Default NaN has sign bit clear, msb frac bit set */ static void arm_set_default_fp_behaviours(float_status *s) { @@ -186,6 +187,7 @@ static void arm_set_default_fp_behaviours(float_status *s) set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); + set_float_default_nan_pattern(0b01000000, s); } static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) From patchwork Mon Dec 2 13:13:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 121F9D78320 for ; Mon, 2 Dec 2024 13:33:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6WV-0006Ls-UG; Mon, 02 Dec 2024 08:31:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gu-0002jW-2r for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003Th-Gl for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:27 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-385e87b25f0so948997f8f.0 for ; Mon, 02 Dec 2024 05:14:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145287; x=1733750087; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mc9TdQ5B4JVTfGpbGlyL+6fSC7bsW93adDUcKdH34tw=; b=UnO6jmJa5KVxEjgL7NCcul8zA1vvh40JnoJ/vOvACxuZMJiCLtg9bwBmcoD/NsKupw F660wV2ualRAQps7a9zvCle07DUecmqgXjiiBUgS6p0ShWMGPqCvstyQ05W6qElw0jNc OetmvtppnUc2h8+z8zC1FrreudVVIPTo0LsurLpNUPjnjbSc9qt+m4ei3zr7ducP1gq7 3JyplxcgcFAf7QxqlTOTyfEnooM28mbFEOQYwKCD2Zy0OHRjAGtIQZWsybIhJ0rXqDyd 3Z9yoccZ9C8UuMwGfMtOs0ugGFq3eQrW5gg/1gxoaTcnI1eGOcoWh9nY6rtnA6XFePc6 eJaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145287; x=1733750087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mc9TdQ5B4JVTfGpbGlyL+6fSC7bsW93adDUcKdH34tw=; b=qyUGqwvViAT9GLl7tS4lZGsfqzqT+YY3R//c+Kwai6y+SclUHjBLYAggt8tC7HsNlf 4HCX294wfVkBKnnOlQ6fGuq5LHuidJSrWzrPYHPsHiqYGPEDvQvv3CBW7TOzwciYeyvb FnEIZlYdZ7ES2o1RBVVr1drerSh1kaR0WrkXIZQWcc+JYvF4FqU+r9iDMX1pQlMa+z/0 A+gbE872oeeZ4Pv860EllmOodIJCZ+GM/vIGuRRSa/TLAYd7ChZhkHZ3Ll0iR78qte0S MJQ/n5Bvy3lEHa6NwdOJ8GyASLuvigQh/SjnqE6n0fNCXijlcTyBVCO1V918HDsSs5VH ZRJQ== X-Gm-Message-State: AOJu0YzCMMLlRn4NY2S4qmOd85kgg1wOLwCSwcoEKeKTBKCNBqHRYiSI 7GnX+Vb2bhSNDEpZGrieCHA1L4o1uUD4/xWal6IVd33tQmNwAD2X4AKy15jtZa1+XJqePHU17Yx O X-Gm-Gg: ASbGncu8WehT4WdtSJ9tSsCblzJTtox6Bo9HXg6qiMNutWTRZQYy+w7/GitXmT0aK7L ipbMdrMbU/1SiRdQ8fPC7bZYP0Qs3oKexcrUXfK2UgGF+3F6BH/5xs1BQyfwDTCNWTusxGA5ZBY 1moxPpdb/aYaHMRzUUhP6O7RBCD0eucs7Mw49dFk1z7vqOIQr+Vf71r8lCXQEZWI/YQKAGzO0/l lW1Q5gFr30rjQOgtkaOZwqSQe1eipvi6IZgF8gPu7LQDZ0DZ+M+K0E= X-Google-Smtp-Source: AGHT+IE7TZ9HLEylyGxlNLd8UOKgZcyVAZG/YDCLYYUz45z1whmCbtIPbHtQM9QMqlWtZ+JyMGgcIQ== X-Received: by 2002:a5d:64c7:0:b0:385:f7e5:de88 with SMTP id ffacd0b85a97d-385f7e5dfe3mr1852046f8f.3.1733145286878; Mon, 02 Dec 2024 05:14:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 41/54] target/loongarch: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:34 +0000 Message-Id: <20241202131347.498124-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for loongarch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/loongarch/tcg/fpu_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c index aea5e0fe5e6..a83acf64b08 100644 --- a/target/loongarch/tcg/fpu_helper.c +++ b/target/loongarch/tcg/fpu_helper.c @@ -38,6 +38,8 @@ void restore_fp_status(CPULoongArchState *env) */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); + /* Default NaN: sign bit clear, msb frac bit set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } int ieee_ex_to_loongarch(int xcpt) From patchwork Mon Dec 2 13:13:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D7A4D7831B for ; Mon, 2 Dec 2024 13:28:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Su-0006pd-76; Mon, 02 Dec 2024 08:27:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gc-0002Lg-0K for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:16 -0500 Received: from mail-lf1-x12e.google.com ([2a00:1450:4864:20::12e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GR-0003Uf-LI for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:09 -0500 Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-53df19bf6a9so4796428e87.1 for ; Mon, 02 Dec 2024 05:14:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145289; x=1733750089; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7mmqERnKJTYNHU5Lv8qXJWCaRjH14PqNpgofF/931Yw=; b=iuKSdGLo3VJrEuzjp61CqULeyjxSFNo3t9kt8jMcSzdpvnDwrHeHiXT4sV1VtfbnLA B2YIq+reKf+ToL0DUypC5gTi9xge/FZCOK6/YNbX9IUXHlwM8R80PSmaG9uaBFh78JVD pY9ly6cGlLuJDLYHloBQ5F2i0E+Wnmz7rjU5PeAxejUarF3ZGnS5IRZ8v/idrd6fxkCJ nTjIDF/QLl32as+HLOeokbz8LoWG/ARmanQqp8XqHfsRN3kqEr3UEi7Irl9zVLzD6L80 OGDOq4JYSyV3DXBd6iwyk+ygAx2Wf1D7+OGir43V5Ka5z2ra7BClUDTg6mDVA9mjsqg0 lzRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145289; x=1733750089; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7mmqERnKJTYNHU5Lv8qXJWCaRjH14PqNpgofF/931Yw=; b=iifiVnf5FRjIxZ+rvXZCF/4GTPVd9+6eNlG4xpg5SIbR5RkJ7IwNgirkAITnQDaY9N pomSMjwTqr+VXd6Vhoz85ZueUFYpmmOXAygNEKslzhiLQ/6PUKKlLHfAE/wpORYg172K njy088IbA+14RIStl7g1H7qg0RFdYT9fjLWA72OJNA3qYnPDGMu2e+4SlWmguiBJRafr +yluGzpNMzNRoftwtWd/bCnw5mEwPjHFu1FitIQYXIl71aqqt1WwPhCyMuWrfEMURJ1i bvY6QzTBecNKuKIbkCyA9U8RWovTx4NBGxbrHHvhRvns50GxJv639cv41MuBExPlR7vM hdeA== X-Gm-Message-State: AOJu0YwqPEAxghi8P1JClXuVlkjYGN/GNyVaMBi9P/LyjpsjTrpI5uMz XP6oePNtaJtpGqcU9Jc4jVmHAK0kHVELIAND1BH5MVc+og64PFp4OumWjvT5U9M8m2c2Rt5AIsO C X-Gm-Gg: ASbGncveM9nIvnI9cmbzLbsCTQtw/Yt9bLTLSY4r3uHpEet6PvczODASAoWxpDoxbp7 vVkQ1x5zj4FCnNMQDO6lNwRQKih9lJrx7mey0JPuu2P2wi7XCuGuS8SI/icEh6rBrakVkA/I7/l +fqOmhuntNCfccn2F0asOhYO6W9nBUx/5fOHp8NvTMbf9auYxv1Kc0ez+NXJMiA78pZkHzMvG+I bzIQ9LszE0NOfxBLPRdqwA9ld3Ufj7OSpkB5MKpm7N3JEQM/tiLn28= X-Google-Smtp-Source: AGHT+IHoNh9oBV49L/bH9Rnq+59oW7g+9/k/G/yiTTjNWH4zraotaaGroDgjZj+LGtjioc8WBOrUTw== X-Received: by 2002:a05:6512:400f:b0:53d:a93c:649e with SMTP id 2adb3069b0e04-53df0109024mr13214815e87.35.1733145287794; Mon, 02 Dec 2024 05:14:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 42/54] target/m68k: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:35 +0000 Message-Id: <20241202131347.498124-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for m68k. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/m68k/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 13b76e22488..9de8ce67078 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -105,6 +105,8 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type) * preceding paragraph for nonsignaling NaNs. */ set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); + /* Default NaN: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); nan = floatx80_default_nan(&env->fp_status); for (i = 0; i < 8; i++) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index b5ec1944d15..ecb7a52ae7c 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,7 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) || defined(TARGET_M68K) +#if defined(TARGET_SPARC) /* Sign bit clear, all frac bits set */ dnan_pattern = 0b01111111; #elif defined(TARGET_HEXAGON) From patchwork Mon Dec 2 13:13:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4C61D78322 for ; Mon, 2 Dec 2024 13:40:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Uf-00029i-Mg; Mon, 02 Dec 2024 08:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gl-0002bv-1V for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GU-0003UD-P4 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:13 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-43494a20379so34266495e9.0 for ; Mon, 02 Dec 2024 05:14:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145288; x=1733750088; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vygoGC00xfYC/uInMNcn40F6CC96Rh4moS0oHLIBbXA=; b=ERypsltw8lLUWYHz7vw0lyBDboowStiR6nmRXWuIPpQ+8O9blOZayfrFU92SQdKhOK XPcqKEEZoTmggjFFPVJ9NwcdbGnnQQRf8HH6mhEiuOznoLCg5N+xHg/3Dgcwxs3TptqO CwS9nlGljXRNel0nBFl72DwKDYyimYLfjp9JHR6+71MD7BABz8mQTq334hmg1PAA0WF4 UW5OAYOWPQwh5affbp+yaTFh5rkzF5bySGrSn6o9gZd/SOC6GLiPnEmBxhn/jaW9cg2n yE5X4vQEpZffZsZfKAMLFFcIskce6Tf+54rcZeHrQNwhlIDpg65uSosL5CoNAczbovKN ciKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145288; x=1733750088; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vygoGC00xfYC/uInMNcn40F6CC96Rh4moS0oHLIBbXA=; b=qDhwGijfpFaqLCMfl/i7spEDJEq7gQCUWG5Q+thLPakjQ3wdKdRrgs4DDPHbrpxMFb sNNJvPrll4CTlf7OOIIgAG+hiJNtlTii9yh70bbRk6L5RJ9VJQI8y92Ihnuq5ml/QGec Z7TLr5NPDcc+P6jXJeQqVW6KoLHB5oI6FK8duy9zvzhghdnr8kxzv4XTrAq1l1/xNDpE vFQb2SDTAEb6EhbWR8oyPgFnwdF1eqHDlbu8KinvJwefTiI3l1P4vsBuTWbzh6PwJMWq T5S4Kfz8a6E9H1lsxGb2/8Z6CVCtwMxsViZHCoCdxqlMDetW/dtrSdxuC8p7moUMDzdR Q3zQ== X-Gm-Message-State: AOJu0Yxvr9MneN7ucOizSI0u9nnj0FGc98hPBQV/cEuQcwN0eAOKRz5E sgUc/6/zGx/zkBKkSsPjNpKu49PkpIM1Gejv/wATC8GJauWrLGc9BcBcbPSyXMJKwJpR6MdAcLB 7 X-Gm-Gg: ASbGncsn9mR9iV6naG8xAoV9j1ZYuaDiMErk1CR0d1gAxLrx+MAGbdXaVT4VOHOti3n oyMZhJ4ipznHfTWDhjTD7PWWHv2MiwjBhGx6hxiTM4dN/a+CyFBhDOcMDDwxHELft+lryQFFcZb cPs8/u6CrwmTqbpQRv8VqVUNn2j0yh0WqyIbtDlOylT9czdY27VY6VyXCRB5vxiWdcMSwvaZxLt ndC/A/rhWgD3bEVyzPU2jRkVdK8Ca5J9ZT+xOwngfwOqYHAB1p/E5Y= X-Google-Smtp-Source: AGHT+IHdUF2LtH6AI9ENX2DDk4Q1y9wiIXG/PfUs/1Qp2CqVtbJMKv9t9Hc11c+RWxXGdhxqR/Yb+w== X-Received: by 2002:a05:600c:4686:b0:434:a962:2a8c with SMTP id 5b1f17b1804b1-434a9df6af9mr189221625e9.22.1733145288636; Mon, 02 Dec 2024 05:14:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 43/54] target/mips: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:36 +0000 Message-Id: <20241202131347.498124-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/mips/fpu_helper.h | 7 +++++++ target/mips/msa.c | 3 +++ 2 files changed, 10 insertions(+) diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h index 8ca0ca7ea39..6ad1e466cfd 100644 --- a/target/mips/fpu_helper.h +++ b/target/mips/fpu_helper.h @@ -47,6 +47,13 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env) set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); + /* + * With nan2008, the default NaN value has the sign bit clear and the + * frac msb set; with the older mode, the sign bit is clear, and all + * frac bits except the msb are set. + */ + set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, + &env->active_fpu.fp_status); } diff --git a/target/mips/msa.c b/target/mips/msa.c index 93a9a87d76d..fc77bfc7b9a 100644 --- a/target/mips/msa.c +++ b/target/mips/msa.c @@ -81,4 +81,7 @@ void msa_reset(CPUMIPSState *env) /* Inf * 0 + NaN returns the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->active_tc.msa_fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, + &env->active_tc.msa_fp_status); } From patchwork Mon Dec 2 13:13:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890642 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B241D7831F for ; Mon, 2 Dec 2024 13:31:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Uk-0002iG-6A; Mon, 02 Dec 2024 08:29:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gx-0002sJ-Ep for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:32 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003VZ-Io for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-385dbf79881so1912572f8f.1 for ; Mon, 02 Dec 2024 05:14:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145291; x=1733750091; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1acc7zoNKrBVtOlWY+W2T5QYcrfhAL8i8cxJ7BeDz+0=; b=XQlqIJTLSmRQh5jxd6vNhueryo+DTAGiZl9wEIQk9Oxi/a5fpV8XwjZtTaiBNC26up lYqGiZ/7BXYxzG2iBwlH+evj3nEImv8e7aPz8drMxMwW/QmgpS2F+9aUrGY1qTb0lt1b szGIkqIhKkseYaQ6cHHXhCgJV8sJKY1qQk3wfX9OgROzgd52Ce6DTkwJj0oNLWbsw3Gz kngMJV94TEeV3qypcxlnbqZvGU35PBOnFHGAwWBcrAFWf36bD2wHtDTFxsDObqsyWjcm sqi0XeW+nnGl5i7dE2O7pgpE+8TrMh+6+t8fuNHLFPLsHiC84VU8VbiSQmHzQf6/bFEe na5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145291; x=1733750091; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1acc7zoNKrBVtOlWY+W2T5QYcrfhAL8i8cxJ7BeDz+0=; b=vN4IMGmFnEkdUbSERuFm1x0Ks7kUYdlDpcVMl4X0SqPkD96EFHlP+P7ypM+XUEgxJa 2VRpF+DKpQutEi6gKEXJ16mwaAIkwiEBw6f7eSEGtkA2NaMdMaZnbDszo3H4ot9nCSsY dOq+OiVyBbBN3Nix86+suNl1IG+jWbEvHvAJ2wqIw5PQw4ZbzUOrT43g7yueDrxaeJV0 CRoPOq7RZnE9SNTWUYdYIRXiVRb2KZYW6MVob2Nrf3WMpHBnEZrCL0pFuECB9Gxvbn+7 srLmccnoUoBTmMd1ZxoT9blhP6cK93x0pxWlKIO47JJMyPJGViH7w694fBRMwnnZ0fFb /1Hg== X-Gm-Message-State: AOJu0YyzFcBTtSMIU5V8b735VR9gxBGbx1l3U1tMuuOYsDYEtF5FA7Cx 3RQ9JQ3LO/LOVBNsASgRw8hexZAIb2PkrWHQCQ0gDXkNjYnTEZ4V+A70djjDxdu205vyprkBybV t X-Gm-Gg: ASbGncsYp5KAOTpE2nDIs28BToEcQcmbLtLXM8zOEBrS77xmSP1xBpaHPYeQCossONo DHbJjN72NqtxGEGjfkOk7ZpA+Ee42yhYrdXD0diAuqqCuVb2MqgYbgDOI3L7YAE16VnkBrx6eAj OKAHauUFL+AcWv/rs1mqimMdUx6vvufvB95Q/GUyvRU8hiSTrkHXDqPLo2+Ujr5DTw8SdUJeAE+ G8mTUwxYIUn3f78O3M2HxhGBDM8M2bksYAxaCnWOW3SC0Hp3pnsKws= X-Google-Smtp-Source: AGHT+IHNbge/vZMLc8RGd/dZFXD5GsVkV/6of92W3el18+GZwhG01NfV23T6gs101y0B+U0NJB/gsw== X-Received: by 2002:a05:6000:178d:b0:385:e03f:7553 with SMTP id ffacd0b85a97d-385e03f7608mr10721053f8f.9.1733145289443; Mon, 02 Dec 2024 05:14:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 44/54] target/openrisc: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:37 +0000 Message-Id: <20241202131347.498124-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for openrisc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/openrisc/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f26..3ccf85e95f0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -111,6 +111,8 @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type) */ set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); + /* Default NaN: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; From patchwork Mon Dec 2 13:13:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B40FAD78321 for ; Mon, 2 Dec 2024 13:42:55 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Y4-0008HM-Br; Mon, 02 Dec 2024 08:33:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gz-0002yY-Ky for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003W3-NX for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-434a742481aso34106115e9.3 for ; Mon, 02 Dec 2024 05:14:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145292; x=1733750092; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KxLOQbRoeGb10eLB+8NmOgmz26mWmDSAJp80nLJIeco=; b=l6ueompuCBChCqBxAH3yWgH31aO1Mu/HV1nV2PenVBkqFGLJg3jDxzvaRGQslwEa+Z KvI16I+WE63PQ6ltk24TE1r1haxnZBSuu08wmBjfrYOND7AFFG4M32Jw8TJg7y+yja6/ BdYMNHUL08Ny6bGME3xa05nt+tZq/MjBy4RcP8h0eIV6VRF9TCcfdc7roo1NclS0rbvc L1LhrwXYSb6DjEYkvKVfhjdcW6agoYx5EEMz4LqgscR7eQsClQEhPRjbU1gPvC5Zvx0b KxLCV8PxbfWHCYpY98m8tjqOqF+xzxsrffroBNdFYNkr/lv4MYz00dDRHFzF0fua6aor p3JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145292; x=1733750092; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KxLOQbRoeGb10eLB+8NmOgmz26mWmDSAJp80nLJIeco=; b=lDHCqO2Yj79Ce4aDmmPnwUaDW74c6bvffrTxQdOq5Z7G0/QtkrwiSif6mMKqJ9XF0m GmL6UvY9r0lWKqBArqjSrD8bz3I6KDtqMSLksiEERaC27YbrjHiUmrzrL3s9F2YcuVme mTR8jMWggMWeSAmh3/Dd9tvbHaNyOX55vYmeK+oQQSjXxbzq9yJy3cHN78bC69biYYuW d/KMOYPeqvjV/14a4rOXGc/ZMXfFKNeP+RQt+htf89d1h7+vfLUB/XU58ZoD9VS+xt5z vJSWwQe1CL0QV5QL9hZj8bul08/qvhuYsUd1345mq6u2oJ2yVFhJ7rzS7xfzQbR2SexU j9lw== X-Gm-Message-State: AOJu0YzW3hR68EZPS5knhnmZyPJyEfJzWF+Vs9oPxH33AfAcb08JsPxv Cu8kuoAtyfWbI2HKZjKzFyy4r7u7vWcizLmQmYHbpVFpj+NQE/LrTGLoO6sQpTfrHHsLI+mYyC8 0 X-Gm-Gg: ASbGncugNo0wsJw/JB+THZdANw6CytTKMN5PCvKoT+8xBn3eKKv048hwtQBPE4wh2aN L77f3cbfUmmp/FY9Oo2tfvVYe+VcQOBHL5wsAIYxaowpsMb0w4bsJpgGHAd8ze4mgw4OJpqonhI VJ5gNA76eWTBndR2QeAgOoHY1S3prAv1aeI/NXhpOJq4tbGOJWbWmUQxpOCSNZrVVO0GGRd6MIZ BT1WGY6B6+J6GmXzTyI5ZmlXSOOf7yu7KQ0UwfHTBGhhb9Z7uJSLr0= X-Google-Smtp-Source: AGHT+IFqGyUblDWhtWty5ZHlDTNTNN7T512u2FwInp5HYuDUlb8l4DtOyrrXP9g08yiDPar3bIjIAw== X-Received: by 2002:a05:6000:154c:b0:382:5aae:87c7 with SMTP id ffacd0b85a97d-385c6ec0b2emr18715172f8f.31.1733145291760; Mon, 02 Dec 2024 05:14:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 45/54] target/ppc: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:38 +0000 Message-Id: <20241202131347.498124-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for ppc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index eb9d7b13701..1253dbf622c 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7286,6 +7286,10 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type) set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); + /* Default NaN: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); + set_float_default_nan_pattern(0b01000000, &env->vec_status); + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr = &env->spr_cb[i]; From patchwork Mon Dec 2 13:13:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890636 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EDC4D7831B for ; Mon, 2 Dec 2024 13:29:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Te-0007BJ-8b; Mon, 02 Dec 2024 08:28:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0002IW-Ba for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:08 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GQ-0003Wo-R4 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:05 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-385df8815fcso1791969f8f.1 for ; Mon, 02 Dec 2024 05:14:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145293; x=1733750093; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Iti77Qpa/qys0505SaJu0EETHGjGdf7P6zBWbzXMDlw=; b=DcxT71KadiYrZA3OjC5S22Mpvd+hH7sBtNVtwdgprGBSojU0KUGqtCGEX07fCicFGA V4WUlVtRDFl5vUu7pRcb2CoCCv5LY50oGAhH1ugl+dgPcbr7eSQvsu7dPNnCbm4BSReb DpMwa7+MJOTBh7fISpnvgeQngMRezm0ayG/j4+qMXyUWQOePFlNHXh9DoEs43ZqQQEsL SwfhvP/r5JXElzCzoPq40clRR0w+fUDFVuxNqWegqb3XaWDKuDAaUNcyvPpcL3oztPYA GX+tf7J5pxJZsOF1ugBgY1T99iOTSdWSGPU3kPs4NyRNWhHUTSH9LYthAwFZHqIc9P12 gw3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145293; x=1733750093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Iti77Qpa/qys0505SaJu0EETHGjGdf7P6zBWbzXMDlw=; b=SFQxLcwfT0cCrOMDs7+oofhA1iMSd0yYqdF/OPI05iJPutkBzQs87cRa8Er+BcxriX oPBB/KbwxiCoFW+mRwFMXXwCLK7dOGSouCRRqpjvbvrkqdXHXxhx2+ZgpAwIqdMxm2hW q7WeHTpKlaXZmn11k7Dg+aI7PAgl4ZTZoDhyaUpX/0UacY6swWi7HS3vPlEHphvxhwnb jRLv52C6RdlTX0S9lXy6KdXstC+EIWcMRVRlRJSkjYyNe5v5EHixS8TY2/cyshpR+rm+ m0i0OKmqL8Xl2CoSMCE7VaMWTGaCNQ0yJbo/Z9sfTRBcCusH5IhvCmliKjjyY1nM8Rjg vHLg== X-Gm-Message-State: AOJu0YwGsonPuk5uEwZCzXPPyop7YSzoznTCklwD+/iuK8ATh6psQbsV EOw8r1WmNiGzNXziB1LbzMDofyyZk2lPwWrj/+93Z4vG7fbkWf0ngeoLosMJPOCMUeyqTNs5qI5 E X-Gm-Gg: ASbGnctiRJZ7zWjCj+8Wd22+GsCqpV2Ol2jxnEmvSiKqGvJvqr/dtyAYabriOWzeCk3 sN5uiN06awVTYVZHkGrA2JPIdLYsiWJeC9ieSIE5nQ/7NukypT4oPc+6FKS5wzdocD2obvtwqXs zLiFrVpGaFjZuF+QdqntuYil2bAWGZxX4J9sIpwDPUasEHXZKySd32AaRRVAMbXZ6x+CIh3Uc7x Ri7u14IvmoCW29EXfXVV3OOypaN5mewFHFKDO+TaiPix1+ca0GkspM= X-Google-Smtp-Source: AGHT+IE7hvtFuGrEg0mz+bBatZd0DfKZl20t+3wAaC7jG2Nq+5wvLqiyfB/3feAoQtSqJOeAf6PZeA== X-Received: by 2002:a5d:59ab:0:b0:385:f560:7911 with SMTP id ffacd0b85a97d-385f5607b0cmr2206242f8f.10.1733145292619; Mon, 02 Dec 2024 05:14:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Note that sh4 is one of the only three targets (the others being HPPA and sometimes MIPS) that has snan_bit_is_one set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sh4/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcfd..d5008859b8e 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -127,6 +127,8 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); + /* sign bit clear, set all frac bits other than msb */ + set_float_default_nan_pattern(0b00111111, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) From patchwork Mon Dec 2 13:13:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 31567D78320 for ; Mon, 2 Dec 2024 13:35:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6UT-0000kb-6O; Mon, 02 Dec 2024 08:29:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gl-0002bq-15 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GU-0003Xd-N2 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:11 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-385e1f3f2a6so1544152f8f.3 for ; Mon, 02 Dec 2024 05:14:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145294; x=1733750094; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wIjZFE7UkHdsOrQTCFo+cXQ64MiE8Y6c27yOZdc2SmU=; b=zJFYt/D0GEtQrN/ejpxfd6evkIstNP7XhktqFPB8YNbdjPT62SKUPA9wcn5GqGjl22 MlfwUxIr9nxl/HwK9WcpYuUKPXHAFI8cEbFpF8SvGuUsel2+QD7SZIWoT9Ufcya483Pb GyV5tuwW0ewMPi0UUa2CCb+e0io64ScZfKyv+Ltnyqlt37s+WQAxysamC+yCHUHozDoS uBfljId8BV4YVxFDSIY/yPNISCRu+TmMkkoxmKKQa9EXZi3Vv+TNhPGmNHpBRkVL2Etx 9MiaD4qVukAed2TOVvYi3VKcve3a/yE4WOploewWQPx2P5+J+l51nTnLksGCU/ijYHLV iplg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145294; x=1733750094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wIjZFE7UkHdsOrQTCFo+cXQ64MiE8Y6c27yOZdc2SmU=; b=CYLA0C2C3uz4gHebesLHe8icfUi64JIZ6XZXlQeehgD91ITBczqLodO1hpUSh5fnK5 hOlUJepmN5coYlNaR9qeAq/a8EC6XSZzdpV0/fAIjxZffarVxXSry9Knl6Gepkpo38aA jTaarujCkmmHKTQDLM0lDR2cgwHDDBqA5oCd9ctsN8pAL3vl+yRjagvE3P60lMjpYSKV uqJrk9U4is80xHWe/iBDcG0J4DtyoJ4URZRU0LMfmhENDbSk/NG/EwK9WSjxlCu8qsTH 1g0oOdsbMrUe5TzevFjnHv+/CM4wSoKzWw6huOVWdw3nTUH1pBOVsSxJlwcdUzrglgDC B7PQ== X-Gm-Message-State: AOJu0YwzAhcQvmBtW7N6Ad3kcHH+NEGkqyBOATofA2Jv3228RUzaK+R5 aloOfQmBksxArEEQuUPmWX96HFbJURYm3vDDYzGZu+7b9sVm31ELPYwiWkryUfjK1R/2tQglrcI R X-Gm-Gg: ASbGnctJGs33nFciOdJbSeXe/nossI9+YYq8dBGKxTXMWBVaS9cSGIecA3+f/D3h/1D ECCsrCLQobX9h7WWHKarnqq+ovJmscCyB8My11jxuFsNm1L4KaYvcM9aXpJTtSwtzPZyTvCiyVT 65YVrmFsq1QVtIlwUEkQrvSsQV4KfbKjFSJ/ZKoMVmS4pr3hYb9H0eBOI/2fR+OgSn/TxDXbviX rMj1/Kg/m/RY1GapUMpsl33CXJ8aCdMJK2yh9EDf91iRQCNj4yLAnE= X-Google-Smtp-Source: AGHT+IFnOp/qmDxoo8maoUW0HNCIhHY/AycOvqAK/YMRFl3NaZIfSnFpJn5BqDRmNnLF2XpRV+ImjA== X-Received: by 2002:a05:6000:1565:b0:385:f062:c2df with SMTP id ffacd0b85a97d-385f062c5d3mr3670273f8f.11.1733145293503; Mon, 02 Dec 2024 05:14:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 47/54] target/rx: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:40 +0000 Message-Id: <20241202131347.498124-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for rx. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/rx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f..69ec0bc7b3d 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -100,6 +100,8 @@ static void rx_cpu_reset_hold(Object *obj, ResetType type) * then prefer dest over source", which is float_2nan_prop_s_ab. */ set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) From patchwork Mon Dec 2 13:13:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F399BD78321 for ; Mon, 2 Dec 2024 13:34:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Ua-0001YK-Mf; Mon, 02 Dec 2024 08:29:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gl-0002c7-3T for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GX-0003YM-1m for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:17 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-385eb7ee7e2so757757f8f.3 for ; Mon, 02 Dec 2024 05:14:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145295; x=1733750095; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GcCmSt30lYdPKkQM5ubQPjbLlX8F5CbU10wVOuOifdc=; b=cBZvp4eV9TEsmZ74yRvBAdnusXyZRodVxTBZko2aXM7IfaTwnuhtUSIuM6p0DdU9/H eaH4tm/kucgSpiAcOlChL8uxmp11nfCNGypvjwBDpibAa1xEqHIoZ7ujYs57wJIBctoF bjR3QDi9c/JUgrCwi13c8rEO1BXJrNIPwklecJO+fZ1CZOzGhO+EieB05KbqjHeZ8ddz YmmoU2cVmWLNvxusjxxtWqpONn8n3ChjkwSG0PArhFqVU5K+BtVsZpnNvRDRDq/4c7Nz qO3mwFDyy03Jsl+JRQyXKaox/UN5PQWhgsAYPqQXERlTMqpMgGzW4LXXfaDAcIuJUQ50 pdAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145295; x=1733750095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GcCmSt30lYdPKkQM5ubQPjbLlX8F5CbU10wVOuOifdc=; b=cOHyBd9Wdgfx3FCsk6CT18xJgQsHSCca8SpJOgrdXCV4t9IchwAd8AM0sRgD8oxWUL lqe4lkll0NXWKZRSMRr/MvVbi5RkzcvALnRQigHsTg+5sKxi5K6JsWwmztxbrKbptKZi m5t8koMByMqR2/wYSKl2c4HxV8UOV5MzeYNBrDUtV2d9zmMyPks+CkYNu4TdHRuCaV7/ czusWZVJXndC/VKIoyUf4G2KFAtbtOqW4C5J9yBWWdsrKKaMdn45eoEJdS4//HJK6veg Hjus/qPUAuSVXMVSC1AijfRgQSm2tjSBUcg4VyLQGPY3O4Rza47D0DrHVYL8J4J0HKY8 nhfA== X-Gm-Message-State: AOJu0YzL1m3oxPf3JEApjZwkNMVK6RWxxwNladwDfCe1gDhCUGXTfi8i rdrZR0VaD7Ppa09bcZLSXOLcc3AS8VL7IFnZaDfX8+cBT0Gil9ZmHoRkqlRbYTqjFylOqlO2+dH E X-Gm-Gg: ASbGncvUbB7R3iXEsGDw5pHszHMHmpJ+7nfyzbfAqvSeVXB4faLi9U5EQGkmAWCK+VG GQ+t5aWRcz+9DzPkMxC/bw8Trc9L9n4WrEAr4EpDMU3KlYVaP2IGvSl76qc0lerBlrET8ajC4QX Tr29gLiPyyGno4PJcR72/3zYdbN+seT7JEzZFOJqYUEetqIJvEBg1RBBifN3rcbbb1e5mPxcA7K qRCWRVRKoMzenEofCM9BRAUxNOtDxD7fJDjXXRIL1Fd7gb8uZXWFYc= X-Google-Smtp-Source: AGHT+IEMWA8R+sjb0UDNLKxMw0MrwaLmHVv03KFNhEwVlZ/CFQlwS2cTAsuf1zTSP6YRWuLQN4g/Sw== X-Received: by 2002:a5d:47a7:0:b0:382:4f34:ef7f with SMTP id ffacd0b85a97d-385c6ec1011mr18645015f8f.31.1733145294496; Mon, 02 Dec 2024 05:14:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 48/54] target/s390x: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:41 +0000 Message-Id: <20241202131347.498124-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for s390x. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/s390x/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index e74055bad79..adb27504ad5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -209,6 +209,8 @@ static void s390_cpu_reset_hold(Object *obj, ResetType type) set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status); set_float_infzeronan_rule(float_infzeronan_dnan_always, &env->fpu_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fpu_status); /* fall through */ case RESET_TYPE_S390_CPU_NORMAL: env->psw.mask &= ~PSW_MASK_RI; From patchwork Mon Dec 2 13:13:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BA9BD78322 for ; Mon, 2 Dec 2024 13:41:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Yq-0002OM-Cl; Mon, 02 Dec 2024 08:34:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6H2-00033k-Vx for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:38 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003Yn-Ro for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:36 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-434a95095efso30379525e9.0 for ; Mon, 02 Dec 2024 05:14:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145295; x=1733750095; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2ViFvWD2hAYTuBKEMhbDqPcZsE6RzFHNeiujTaxjrOk=; b=x6KNhgX8kvER1ljhqy69G/UhuRsKSXvbgKTrxMjhP/EZeDBLeOlSuWRjsKlKDTiJyC xuUuIkatzKguJhHlv4E+yRBBObk+LUMN/XDd1BhurswOfQq4ICpFEuToLRIrfuFO170C QidWJRHsfY0szrUW9EZ7RjGmPDDwniGHsll4+Hsu1fn+2v0SJO0khcrzt8cbHPbu38zn dekRpnr/QqcQgDvuEXjy7NPjPO5ZEPL3rnWnh2iJS0TSajcePa7cstzrRB98fqMPbRlc xcoBp20ASijvyJhlJAikAXLrkkqB5iOSw0TkGZLMHlAr0B71oOsVcIHeQ48lVf0b6clL PvFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145295; x=1733750095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2ViFvWD2hAYTuBKEMhbDqPcZsE6RzFHNeiujTaxjrOk=; b=WlZuiarbDdpNF0VEYzapLojD3MECmsy0wfRL7CQzBAm0r/8koMCSU0GSVzgvLg+6B6 vHpQzHYy7XsEAab8rFG5XgwyAD5INhqNGWzOJQ3xnXaMjidyUdxEUHyBPMWUbvThjS8/ ygQSsT7cdfBMCU8qKwmY5KhNqvlxE2/OBXBOLlK5JCGxd3CRVnzUWg/+cX3iOIHp+dq7 mwW3AYhxrSIpeHS7Sq/NqPn8EI0ecuVx0Peml5wZlUJFQIZOU3TmlQUaaido03p0Wnzm GmLkqX3oJbBqvX7oArl9jvoTv0OhlV3wkeKpX59jLPBefCYEpwRHAZ6s3/fMWyn1+oKz pA0Q== X-Gm-Message-State: AOJu0YyCuiixdnUesSXgQJqpKVz/X9Xl/tQma8l2O/GS3V8pggPIH25q KrAbVuwvKV4sQL6p8gPs7EVsigkOjFIpSKxY35Zxm8dW6nPTDeEPjf3P81toKVrvxbmhsQ1v5np N X-Gm-Gg: ASbGnctNtAZ+kidOtrx3Pma5ZMdoBKx/0s1OXjm8VmrTkh0ju9QozyNywmuEOD2aQDm +vMSZYrrbmUPEJ9EHz9Tna5j0cHwAyIVZIHOJPHWs7wK9mAkAX8udfC4q9Mfqr3avlsRgkAMSAB WgJLH2AP4N02gGOOnuFm7+WF0NioDQDwchondnFZs6ixZoWneCb4NwpZixdDBl5MxZajeZ3mNRO eMgyJ0tcgXiE/SUXGEA8A7OvD8nLwtW3MA5qFpsKtQxKuiVic+fASc= X-Google-Smtp-Source: AGHT+IHyyRQ2lvLX2YA9SmELgzRKWHRiLqS12n5m43U7VAgYLq+/2bRqSLCD2YnKzj1RyoNLuWAQAA== X-Received: by 2002:a5d:6c6a:0:b0:382:485b:f976 with SMTP id ffacd0b85a97d-385cbd7c5c0mr16062827f8f.15.1733145295487; Mon, 02 Dec 2024 05:14:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 49/54] target/sparc: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:42 +0000 Message-Id: <20241202131347.498124-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 +---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 0f2997a85e6..6b66ecb3f59 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -818,6 +818,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status); /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); + /* Default NaN value: sign bit clear, all frac bits set */ + set_float_default_nan_pattern(0b01111111, &env->fp_status); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index ecb7a52ae7c..06185237d0f 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,7 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_SPARC) - /* Sign bit clear, all frac bits set */ - dnan_pattern = 0b01111111; -#elif defined(TARGET_HEXAGON) +#if defined(TARGET_HEXAGON) /* Sign bit set, all frac bits set. */ dnan_pattern = 0b11111111; #else From patchwork Mon Dec 2 13:13:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91EB0D78321 for ; Mon, 2 Dec 2024 13:39:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Yh-0001cn-8b; Mon, 02 Dec 2024 08:33:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gz-0002yI-A4 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003Z9-O2 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:32 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-434acf1f9abso38913225e9.2 for ; Mon, 02 Dec 2024 05:14:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145296; x=1733750096; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xP+uJ24vDri92uzeME3QktEyDQnUmbcE3e8V9D9jklU=; b=uoJr4Pxsuioj7APOYOVNhynhdlE+cBB2E9DQdD+OpLJVLJvM6dstHOenJbEn+pEAGa 4+xfWFrNl8D4g2+onxwdi8/Is8oUIH3IvlrQTxlJB2FtjeWvvCuOn9QXyFCS+lOjSNLG PK4M5oFggacKVeJCk5A/7UtSRaiyyAJZOQtcmIkCH8LZTE2M3xAcKDLk/xw5mIIFk2IP 9gWNfW9zDsFlnOgpvnaAJE2TNrNP7ZPw3w9okXGSCb7FHXYPsfwY7+Zw26CRj7y1uedX tg9dVfIDOjlZU31SvUwXCIO5XioXivmXH/ZTaEmb8kVgnEmalrI7636GE/AelOV5w4ko 9tpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145296; x=1733750096; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xP+uJ24vDri92uzeME3QktEyDQnUmbcE3e8V9D9jklU=; b=UR+RsZzDk1S8CtwGsNoQnVcV0Z/uOBSBKscqTym+PTfVftutyHODT8YWb0IHo6ShuP 67X1FPXYWOG8MG+zg2d93tn+oY8Ls7E9UaGF/4Vx0o2LFUi0EBWZU6l2MomfNLZph7cc PWbSCRfrij9Dwmny5zoPN9X6x6VPJWsHtkc2aQcyKsSOfqIvw8nHuNW9R/+XBxPyBH3Q SZa0DYO/RYLLPBoe3PvR8Xl81Ie/fRIL36TYpj3L+9c/CjNHayqHWmvugp21+XseLNlJ kJo8nyTsF5Q77cJtdZmU66+PZj1erb3mEALMnknjEqBZ2SmI1RBoXdORojTzyeWfDW9k 6+ew== X-Gm-Message-State: AOJu0YwOgvo5v2eL+yOR9gHEVfV3VZhcS8UJ3RgobFGMGKxhDSUUuWkM P3cri5t3r/Yxh59X+h2G+gAyLSHVi/J6ndxrs+cvtwK+Ix9qw6HrquFfh2/9F6gzWBZOa1RnOxA M X-Gm-Gg: ASbGncuV1WVqTl7ocCxuK9WY2HdJ/5TwrPSazUeZ8mNwdKM65oDu1g68VutlrDBcUG3 BvER6EK37KIJrv6H43X+8L0j/GOi7RuUyee3eXU2n7fb3pt/1T50u73sMyTjsi0xBD6kQYTTCfD /o8EG2cA/Xh9HQ6MNd5ycnPwKxmw89dKsaO6RmsGOskA99CxdkEZ690pVFfmdCuEGGiJPJl87HG Cb4T1g5yqbiXk6/wpm7SlX2jOndu/cBSQAx2fID2Y9aHKj2gF49kqQ= X-Google-Smtp-Source: AGHT+IEbVKa+1D0aSwF3c5B4FQEXLP0C054fxwlcC+LFvDe+s/IEpdCVQQDQPOKB40nkSfuA52KqeA== X-Received: by 2002:a05:6000:154e:b0:385:f44a:a3b with SMTP id ffacd0b85a97d-385f44a0eefmr2327929f8f.41.1733145296363; Mon, 02 Dec 2024 05:14:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 50/54] target/xtensa: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:43 +0000 Message-Id: <20241202131347.498124-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for xtensa. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 3163b758235..0d4d79b58b4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -136,6 +136,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type) /* For inf * 0 + NaN, return the input NaN */ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); set_no_signaling_nans(!dfpu, &env->fp_status); + /* Default NaN value: sign bit clear, set frac msb */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); xtensa_use_first_nan(env, !dfpu); } From patchwork Mon Dec 2 13:13:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB0B6D78321 for ; Mon, 2 Dec 2024 13:34:15 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Xy-000894-Fp; Mon, 02 Dec 2024 08:33:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gq-0002iA-DJ for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003a5-3y for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:23 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-37ed3bd6114so2866865f8f.2 for ; Mon, 02 Dec 2024 05:14:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145297; x=1733750097; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SF+s3/3GUKM6ErlG9DZAUNNlPEUN5YnIqVqgW7tQx0c=; b=Z+tZk3nSo22vKc0EMsaq6/13fVH2u0DY/zCRA6nkILH/acnqBEF+z1Y5GRsuSo7VWB MKtdu4dw5zdQrAM+M39rAtnSSHyudsugPmlcGyLgfHJrEImrBSiUaso0hWLheooJYFLB PX+eqzySgZscyZI0I7+WQWOfr+3WP0SsBaVcYHOXjaxp2Zjme4qP0nOZ0cM6xYoxBLY+ U4Kxp/kmI/OC1Bj+XKw7M18vc1O65GbXhW0qlAReeESkbh4wAGMhsigXAuGQSUGQELX/ ytAMF8495u6wACCOx40A34B28ud0DxYSZlbJ2E4bwQKFo93Ap8abYQPhouGxIgmTwxHG rq/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145297; x=1733750097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SF+s3/3GUKM6ErlG9DZAUNNlPEUN5YnIqVqgW7tQx0c=; b=oAQdvifOGu8CbfHZqG0Qq7y2LoIuXMfo/5k4RwERkHB8N8eHVHA3NNRBYyiylXC++v axK2nn1A/JbuA3LHEo3Wj2WyJGeNZdxVG/C3JdUR9E4A1xmg9m5lUUwYqFV1tRCFkMpI fbLMD087VFJA9aaPeBpBg+XZ89V6IFrir2DZwe9O4R1GGbOGnSmc+YpxmxLNHpuH45xG wip5Cxy6r2VH0FZomnBBnzWa+umdeyDsPvvN2AK5dNTfynmMogTH0jQO7hdMyIO2eogc H4VT2E7HpCKhZCpkM/3msUJLpjrcU+exwigiAmC41PWIhly8cMb1SuAVk/1g07117tzR Gwlw== X-Gm-Message-State: AOJu0Yx3av3iiYqWM2Auz53Yv2ZJmqAh2TCxYLKOXhlAg4bQzUackfV7 GkBZj/Uvra9K3jasQlETZq2S0/5SVCopNZz8kO6cHKn73HAERuz4gX6gE05t+rRmDQuLMxSP2sp Y X-Gm-Gg: ASbGncsBA59krX1l6bt5y4h+alqfeo91/3vfeYcc82/KFURBvhTysuo4IeSiWeyqcjO lp2d1Ce97n7fZ+ez+nJtxiNI5TmqKOtNiuA2N1KPTNmF2mesE6bT+J6e6nqQEmeTPdXlh8C1NL+ OqiXekzIgMz8K8cNf0cxPfpI8w69dEt4nbtDY3/VoJpT9f1+SRyYL0t2AuhQsPx4hNC06zahiR3 9JbUKOp3WiPS8Gs2uFpb5wyWcBcMqmFvsSuEPWJn8C/XwgHXXrkf30= X-Google-Smtp-Source: AGHT+IHZbR8myEJqrFSbtsWW3Ke9b1O77ziqMLQJzRs9zmdRAxpEkQbXVz1J5DH5fUiXKa5Y7BrB/Q== X-Received: by 2002:a05:6000:381:b0:382:5177:3a4f with SMTP id ffacd0b85a97d-385c6edc3ccmr16561180f8f.49.1733145297319; Mon, 02 Dec 2024 05:14:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 51/54] target/hexagon: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:44 +0000 Message-Id: <20241202131347.498124-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for hexagon. Remove the ifdef from parts64_default_nan(); the only remaining unconverted targets all use the default case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/hexagon/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 020038fc490..c9aa9408ec8 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -286,6 +286,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); + /* Default NaN value: sign bit set, all frac bits set */ + set_float_default_nan_pattern(0b11111111, &env->fp_status); } static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 06185237d0f..5954a6213b9 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -136,10 +136,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint8_t dnan_pattern = status->default_nan_pattern; if (dnan_pattern == 0) { -#if defined(TARGET_HEXAGON) - /* Sign bit set, all frac bits set. */ - dnan_pattern = 0b11111111; -#else /* * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. Our other supported targets @@ -152,7 +148,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) /* sign bit clear, set frac msb */ dnan_pattern = 0b01000000; } -#endif } assert(dnan_pattern != 0); From patchwork Mon Dec 2 13:13:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 52D9AD78322 for ; Mon, 2 Dec 2024 13:42:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Ye-0001Ja-Ce; Mon, 02 Dec 2024 08:33:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gz-0002yJ-A0 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:33 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003c4-NC for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:32 -0500 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-385d7f19f20so1783126f8f.1 for ; Mon, 02 Dec 2024 05:14:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145298; x=1733750098; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nt3T9iHPBG+FHbTn0HSdShbMUsPPH/sHv7Ur12KBxlg=; b=L8IwldFaHBni8J3drazU6wTZ3Hk40g4rU1C8KSS8P47zDdDNFUqhG9Nxv2ETN8GfKJ 75t5QZDGTub2L4sjkHF73AvXhWJyYPaD8taGBU50wlbOmbw9lGgwdeKI3bM/iOFEubje tqVmbWe+L9B5NRDr1u1pjfJ92YLGEFJjtzCFmHd3OZqUo3ibcpKPNSGyqIi3euNiGWRu nSAIU5ILoyslXL/AB1K4JkAxDE1TMV7vH6Kt9m/JX1D3ptbdmqASutDWTF7nS+3vzIqt LKd/rSgO+fcLy6b1soiDc3T4KxfucfQYfNRwKX08V13CDS8mS/e0obJkRL+HQ0wTZ4Lw ktsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145298; x=1733750098; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nt3T9iHPBG+FHbTn0HSdShbMUsPPH/sHv7Ur12KBxlg=; b=CdWl/zqoMPobEomtWC4al45F1kGuoybmRpwrCy+k1+uZmxMN2TuyQo/JQ6libDd7Uq 5OzdtLrtBvAaDeXC5zGHZu71AY3ySRHcny4OOksCb4CdKc0hJcnHhKz4uquSoVZ2Y/X4 E4n7YTTn/zjRHID8DR3DizbYkdQ2SDqUqXh/0r/7a31Zh6hR6gCaRFzG8gZOWZY+6GDX SZE0n/XQmGMYXW423tyxrFd3/uucT9FA8uvuZkFdQrsghi/4GsmcWzBYhoGTRov0loze yUrIPsd/Fa6EfKkePDf5nYo9Kd6SRobIanzKHs6mmWtyQQQ3I0Hn+sCujY1diy8VT8QF B9aQ== X-Gm-Message-State: AOJu0YxjkCRLaLDj9V4HN0rKB3t6KHU/iRX/Gu0MLFjsoF8AZ+k17HZL ma0iaNor+r0O+/afr2KWZ2NjMg6RHlsmQ4HTWrCG1ydTlbbYWVhPdx9ULZnhLp/K7LrxAfDnZJS d X-Gm-Gg: ASbGncvDroppP/LfEtmQBwppHEoUB66piDJNx0R5M3pb4qeM6mGro0PhPteTQfT1IFJ F+7yDrGz48Iyi0yNwCzziGvfTIDXihOsTwGN5co81yIQ/SDmjYkUBikAL1nUTPneOYKqaiCmHX/ X84HAfoBQc3WFm8kZCQZ43B1yW0ZMofIN1j+/4O7bJTXNLfwwzPHtiH8zjuj2DZhfNK9jFaAmhv iXca9REZ5ri4OckmuI5c5SaRPnC4mClO+ZsvlGOIABgbKM1p07xOYw= X-Google-Smtp-Source: AGHT+IE7hA5L/kdfOrXZwx6rchjyvu0rnQhZYrqgT7fhKReK3S5N/rvDY7kE0Sn6w9k2hiQ4e9zeaA== X-Received: by 2002:a5d:64a3:0:b0:385:f9db:3c4b with SMTP id ffacd0b85a97d-385f9db4370mr798479f8f.10.1733145298343; Mon, 02 Dec 2024 05:14:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 52/54] target/riscv: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:45 +0000 Message-Id: <20241202131347.498124-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for riscv. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b52..80b09952e78 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1022,6 +1022,8 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type) cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); + /* Default NaN value: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); env->vill = true; #ifndef CONFIG_USER_ONLY From patchwork Mon Dec 2 13:13:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 834E1D78320 for ; Mon, 2 Dec 2024 13:35:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6YY-0000lD-QK; Mon, 02 Dec 2024 08:33:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6Gx-0002sK-FT for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:32 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6GY-0003qI-J8 for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:30 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-385dece873cso1430390f8f.0 for ; Mon, 02 Dec 2024 05:15:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145305; x=1733750105; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Lx4u5nyS6FnIACOhuZuILUeF3tfNByeD1RldfY5AhvM=; b=VtK8m5iuX/NM8saGP8+olK+nfTfGAOGLczn0LSMGSRj+WJANRBoe9z3xnTW9w9PX5B 0LNA5EmNp8Wt6JAggzZAV0S2jBWKYt6dZsjjhUUxjwwhxHHjNCYND0mtlc/v35yiZ4xL NIbPW7FDBxe0MsjxUwJbHQmzcrGeEqdfi+fuzZWIBq/iW8QB9PO52rETZrO+w4zM7HeK sl+9FW2SeyWAJ5ISkG+I3rimmzpk4Pcvvj8kih+jx3eMZW1vgvBTxJ8+ijrdRYqLBmwX UFoX5eLFjS1KGG7IHTPPNk/oAEAQfG6hFm1EZnbkC+tODNbrnx7/6Zs7eMp0WMAgxXUL 9LCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145305; x=1733750105; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lx4u5nyS6FnIACOhuZuILUeF3tfNByeD1RldfY5AhvM=; b=vExc6Q+ADCuXav0SIMvICGsZYXu4YIqOLSGjnRQwvpvKV0Q3mFfE1jV5Ug2J3Umfyu VKNryszrBYlmF3kD1j7/MZPQSrNXgQEBkRbv4r7YWeyMEtG1i9WIzi5lMiQVTAbFRnxc MDRDv4ajKUXf3kh0opXg5he+pKJtKBoZi9J/UFwfuJlMdyWUjXM3DrmVeigRh2Sbis9J zlGCaRv1vOhB2ifCwZwYWIXbV1Q8HKPYqQjGNdqqjS9+OoTWQN7tZgpqvR1wTFskbQ1y ntdJDwLW+MSvF/6ZPZbab7E5X0w/hFhnVpvohKe7/Fycm0D7mk6zXnNeu8gKFCYilbfp HxRw== X-Gm-Message-State: AOJu0YyDiIzjCvmARiaArPdQLNSdrZmFKMvyA3SK+7LCjKHW04dUjcKM +41gBC4fda5gyFOkxLWkdB9Vj6gA+sBsAOyWfKE8MTeO5wA29T8ZW89d/8pgEO+8yeBt2fD+7bh K X-Gm-Gg: ASbGncud9/kCJe9bs3Ee8PPyDM+be3VgRxT7fgKI7d8PLQUaj0Rvnjwhjwpe3WF5Buu C7DLmZvpXe/OQvkx5Tm/zoKsyCE73Q6oZvDqFULFk02iMilVzDFJxawMQgEj6Vt+qEYZPaVWyDy uL3NxrEUuX9u6EtPy2wZuKuWvohIDDkUxyox+j/PIe7MAk82q6gMU4RYf+dUeFnXoVx2OFytdaP uP629sYEtEaQHkgVjVhWPSQLh092nBvSBxO+q7PbVRoxccZOs19cJo= X-Google-Smtp-Source: AGHT+IE2VGJAnehuVMFVcXwJwWYUFFGthX624YluXZHUiteB7VGRqCKZnI4ZvOYVRTx+MYrc/9o62g== X-Received: by 2002:a05:6000:a01:b0:385:edd1:2245 with SMTP id ffacd0b85a97d-385edd123c6mr4738904f8f.30.1733145299323; Mon, 02 Dec 2024 05:14:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:14:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 53/54] target/tricore: Set default NaN pattern explicitly Date: Mon, 2 Dec 2024 13:13:46 +0000 Message-Id: <20241202131347.498124-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the default NaN pattern explicitly for tricore. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/tricore/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77c..e8b0ec51611 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -117,6 +117,8 @@ void fpu_set_state(CPUTriCoreState *env) set_flush_to_zero(1, &env->fp_status); set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status); set_default_nan_mode(1, &env->fp_status); + /* Default NaN pattern: sign bit clear, frac msb set */ + set_float_default_nan_pattern(0b01000000, &env->fp_status); } uint32_t psw_read(CPUTriCoreState *env) From patchwork Mon Dec 2 13:13:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13890668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39FD7D78321 for ; Mon, 2 Dec 2024 13:40:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tI6Yu-0002dS-LM; Mon, 02 Dec 2024 08:34:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tI6HB-0003Iv-CA for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:49 -0500 Received: from mail-lj1-x236.google.com ([2a00:1450:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tI6Ga-0003rD-2M for qemu-devel@nongnu.org; Mon, 02 Dec 2024 08:15:40 -0500 Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2ffd6af012eso50644091fa.2 for ; Mon, 02 Dec 2024 05:15:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733145306; x=1733750106; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3+p59mil36Jx5sXbuX/nuYCVFK4hOA1MfgGjeXhWnZ8=; b=COGpc1P5T2J984nvpF754D+jXTsAkTONxHk/yRRvs1X5Xk3g1i8l00b0mIfXKOr6QK w96wi5r2B9ZCgw8WdVzHYOdgZPYAGKv07oJfg63hF7BWPM7bfvi+IYnNQZAX4iHLM598 H0yEOgqIIWtTYi8+cXdHkRzHsZNFViy2C7DJO4vzqNghNX4lqQUQBgUgSnhWXoWRtXSh 9a7F/DkRxlK3b/uYFWpSu2kBpgZz/AmeUNq6dm0O/EZqZbsw6gDTRkHKH1sucwNhXbW7 vMFvHvRobF8nd5V8q2rHWrPo1h6+iqWVjlrcfDyDvA9kaIdk3VX5TpIO6jzAHVvzaRG9 1r3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733145306; x=1733750106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3+p59mil36Jx5sXbuX/nuYCVFK4hOA1MfgGjeXhWnZ8=; b=oD0WQMViGOMQkYcXgnqrKY0dCHrl5I8W6FXmjW0FmaRIT4iuAe8+PVPmccT3wuqRcM PdqZKfulQd0rkq5O9+aRR32o87ECtjVJVooR0nSGpcHe/d01YwukCHEzPwvjX/9WtknX //qY4lkMOg7bbc3NoQzuRQ8ZEJfFbSWh5mOe4ODm3hj7PVDvR0tpQztCsGhGSuzWGPZj /jeqWOv33D+qx/FFNmynukXAE+KlAghu+OLaDbnTNeA5xcKBOedfJWIXluN6yXhTq7Yo LzcbunBGRex3J+UsVuvVa4YDo00FfYMEpAX0SEVpuiN27ekdXpubQgrio8GmnilSXJV2 fKug== X-Gm-Message-State: AOJu0YzB2nSrSkSlwYLG+Kl/gllEKM2oLTOL+lfCWadGPdh02M+xtj09 fitAbMjBmy4uuVsILJAlbVa0QovRnc1Dl/O/Vhl7/fqX4FtVUe5kf9vGNnArOGh4Fym2MU/Mp78 C X-Gm-Gg: ASbGnctpZLohWPodnKCOSO4ld//vnuiZXB95oxJ872/+s1KKpol+8se+k7/xfrey3Qm d4oJVd/QezNe1oGwIBDtM0upIGAoPx47yjyqtY+ArA95RmPk3B4vMkNtphak0fHvf3tB5tGPfWr cd2axCSsE7GfkzCEIuv2i39X1cYFDIirAZhni59UbRyLISfN8d9N6X+d/fKK1jYm2sbAMBHA+pJ Jur1T4f0EYOWU5Fw7hGu6kmy/wnk4ImFOdWDWnAWK5LJ3hWOzX3UB4= X-Google-Smtp-Source: AGHT+IHphx87kWVxOi7U2XvnsxZQjFZxWWWkqumFQb2lLvHXTj2payivvRcQYH/MGvdQ+/OF8DxViQ== X-Received: by 2002:a05:6512:224f:b0:53d:d3f1:13aa with SMTP id 2adb3069b0e04-53df00d1177mr12216593e87.20.1733145305814; Mon, 02 Dec 2024 05:15:05 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385dea1e4ebsm10160157f8f.1.2024.12.02.05.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2024 05:15:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH v2 for-10.0 54/54] fpu: Remove default handling for dnan_pattern Date: Mon, 2 Dec 2024 13:13:47 +0000 Message-Id: <20241202131347.498124-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241202131347.498124-1-peter.maydell@linaro.org> References: <20241202131347.498124-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that all our targets have bene converted to explicitly specify their pattern for the default NaN value we can remove the remaining fallback code in parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- fpu/softfloat-specialize.c.inc | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index 5954a6213b9..e075c47889a 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -135,20 +135,6 @@ static void parts64_default_nan(FloatParts64 *p, float_status *status) uint64_t frac; uint8_t dnan_pattern = status->default_nan_pattern; - if (dnan_pattern == 0) { - /* - * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, - * S390, SH4, TriCore, and Xtensa. Our other supported targets - * do not have floating-point. - */ - if (snan_bit_is_one(status)) { - /* sign bit clear, set all frac bits other than msb */ - dnan_pattern = 0b00111111; - } else { - /* sign bit clear, set frac msb */ - dnan_pattern = 0b01000000; - } - } assert(dnan_pattern != 0); sign = dnan_pattern >> 7;