From patchwork Tue Dec 3 03:31:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891665 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BC011FC3; Tue, 3 Dec 2024 03:32:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196749; cv=none; b=g+6eYYNYhDKNa/7/IfbK6M8M98suo4KXdNlA+Ak5jcCEy6WtBFNLeOX4s1Hs9TUTphNs8L0xRl9jc/HYIbQndverqrJCSNQf8IeSVh0r21NEDs4vlsV+b09gBRsu9BnBtiLelxVZSip65WAOOjzRkYN38nXMFrDxvxguSVtLPO4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196749; c=relaxed/simple; bh=Wc3cnVwQNfQLJ9bbuGhzSSJFTzHRGdE5UAbMwFKKjjo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=hn7hZK5h0+FShJFl7Nhn6kgZe2l0MGHAtuALynAHSNDv6pv+f92qhXV5XwTKQsqnf8OQf6UIFBfeS6J/jDTdJ7G+nTTP6CMqHUobHeJq5EmQiPBtQoYcMItOTP2vUfOvMD+X29AaIfztvemvqWZc7NEevL70ZpjGxmDfkD2xj3A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=QjSEQAOY; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="QjSEQAOY" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2J7huQ000834; Tue, 3 Dec 2024 03:32:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= q+/VEcu7485AIiWnGGkcoGwamNFxW5YujbP2wZ4RsSs=; b=QjSEQAOYJklNjhNE VPT4y9AKgBl7XbnBBCSxCzuzGnTDW4viJd01mey2LEkJo/7mmbr3acg+fLiC3hrt //Wv/4rtJBJ/VxSZe+bXTReeM3ZOqKG7PKGI+lY3Hsh2kiJXj2+vueOeRwBWbdgG i0WdOUoqiHXguUKpvR91ZESs6Mg9EiOW2PDSczn8vYP5mluUdyb6oPeWbJpFjuFN nKRIFsuRz+0yu4tC17+ms5VhX678nQQGbercnJ4hjG4mDk8A1i9UWO2GuSmUlcMp ABqOCd2tPu+WJpDeM8Ed6dgyBOXXG3dSvvhm1a8PknXUSrG93kalTgKb6aReHx42 oAGl1Q== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437t1gerv5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Dec 2024 03:32:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WDtk003564 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:13 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:12 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:39 -0800 Subject: [PATCH 1/4] dt-bindings: display: msm: dp-controller: document pixel clock stream Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-1-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733196732; l=1325; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=Wc3cnVwQNfQLJ9bbuGhzSSJFTzHRGdE5UAbMwFKKjjo=; b=Bb1l1WQLAjnOWYsL6BUXGEq5O+rUIc6lr8E+cGxLucHIdLXONyE1NpTDF0Y+3VdlwcBg8BKYN XObLkYinHcSD2qMxmdTl4tRe71t8IJEmwqG8gTRQDiZYgLpgGHgkE+z X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kurS0t8mD_469EJxwOUNwkGKY6ecwK4y X-Proofpoint-ORIG-GUID: kurS0t8mD_469EJxwOUNwkGKY6ecwK4y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 mlxlogscore=936 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030028 Display port controller on some MSM chipsets are capable of supporting multiple streams. In order to distinguish the streams better, describe the current pixel clock better to emphasize that it drives the stream 0. Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index a212f335d5ff..35ae2630c2b3 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -55,7 +55,7 @@ properties: - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock clock-names: items: @@ -68,7 +68,7 @@ properties: assigned-clocks: items: - description: link clock source - - description: pixel clock source + - description: stream 0 pixel clock source assigned-clock-parents: items: From patchwork Tue Dec 3 03:31:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891661 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B7B52905; Tue, 3 Dec 2024 03:32:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196747; cv=none; b=j4lLDR7I2RpcHORfK4QBaNDgxPCQS1B2NrUaM4edsP9R1Jz8KOUYDEppeB/raGh2m54tBohPVCBIEo3pzBOiF+vPEiHqZ0FRiiVvjY51vOOmtBUqHYSlHL5hUOSaR9dKivxZCyCMCKQgrI2cC/LEi8oOoGDa49OTg/ngWcdjGow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196747; c=relaxed/simple; bh=Dnz2MIm8SmWMs9ZGfYdkV/nwuzJYw4mTki88O/spmUw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=jTqf4WqY+SbvGcM8enPvsqMY1VzhC9QF5Nu4W137S4Po72XQHG3QoXEc+hqfyuY8b1R8etjXLtNieHVLANhRLqd2t8rdkjNSvj03FVn1OHPJnP9wVve0lvz13+5atGs6d3RCmL3YpDlJTQU1zktqxwPWdLfZkKc3twrPrkIq8Ss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ifYRLAeG; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ifYRLAeG" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2JKN7L012144; Tue, 3 Dec 2024 03:32:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= BF32fOsHN9zSwDtan+OuWrXodpgcdAaDEa9ofc8VbT0=; b=ifYRLAeGo0inIguu QE8cdEHWW55roKYlngjICkkpFd5t0FTzqgdphJT4dnKnRwwcaJL5MaS7c1TzkvEB Px6O2jANe9VQTVYGouRY1ksJayAYgFqU0kOhsOL+tI4UFUBDwkyLApGRQZ938LPQ XMInaATAl145Srht6u09ruaTLcDlB42sNul1/i6FZP3N6yRDH6Rq8pb2xHD6z755 14bCaFfg2oCDJaNCiMmtJdGLLMpqhMhg8JJrFleoj/ehUsM1dckRnqX/ULuyVNpU YFOhcFkdcKQw5bOdGQp6zons+C4sbsXkElwurv3XiMOs56NG+FT6AUIRXOFKHu8q qioH7A== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437v07pkv8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Dec 2024 03:32:14 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WEpe028939 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:14 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:13 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:40 -0800 Subject: [PATCH 2/4] dt-bindings: display: msm: dp-controller: document clock parents better Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-2-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733196732; l=971; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=Dnz2MIm8SmWMs9ZGfYdkV/nwuzJYw4mTki88O/spmUw=; b=fqZT9W7Mik5Wi2cKmF8qOSQhMZ+BebmG1BvsGr/fBkDjZQEDwzcv5pFFcoVfY3JdJzBWQDe/a 51H+KHLRDMvAC3gppwBjA8mGVgHWll5BHNeoLl39p1Kk9Vmhh5bfaAD X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8EQ0XUzDO3hQ9K60D7hJXxgTB-yjxsVg X-Proofpoint-GUID: 8EQ0XUzDO3hQ9K60D7hJXxgTB-yjxsVg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 adultscore=0 mlxlogscore=928 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 mlxscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030028 Document the assigned-clock-parents better for the DP controller node to indicate its functionality better. Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 35ae2630c2b3..9fe2bf0484d8 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -72,8 +72,8 @@ properties: assigned-clock-parents: items: - - description: phy 0 parent - - description: phy 1 parent + - description: Link clock PLL output provided by PHY block + - description: Stream 0 pixel clock PLL output provided by PHY block phys: maxItems: 1 From patchwork Tue Dec 3 03:31:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891663 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CDDB36AEC; Tue, 3 Dec 2024 03:32:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196748; cv=none; b=FFZt69ecIZnUEzaLKs01hHK53DTQBRxBevTyXYBIG3LlDeDWhLvkuj7oB4Dgv692GgSB4axIjkKPlvdk2KRu03GyjLlZVZkwNIBLjsgbVbxSAJJOKc0OYgXRXZ/r3VnJKj+9w9+DtVLF8XEkktX2Z8cTbuvuy3q3E6KPXrvEoU8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196748; c=relaxed/simple; bh=WOGgVxaSyvealCotRclm+4BylMOthHPB34gcr+z71s8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JLH7/F2fd1EBCNnVSaa9RHDEggK/bAEsPein1jdwWmE2Fk6q+Jcy8rqC7TAZr5DBGutSLQlJTnDWDSTEYRIwIr7A3ObI2EG+fKntqfS1UKzZOkGKvpNKwb1XXYRoQL/Opj8+//9K7mOcscosmKRqlGD74aLx4KR8of4T3lYgs+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=T/vrsQcf; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="T/vrsQcf" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2IGAkl013586; Tue, 3 Dec 2024 03:32:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 9EC1w8s8BPhkx4Uz/TKlbIJEh7clG4u1fkw5OdL8y/0=; b=T/vrsQcfDwcFEYPg EYBPkZDRayle1K4x4cUpU6Dnn/FvMmIu1qwZrjPuaavJwVwPlpHz8Scws1ivgm8b t0/vIUL/d5VALdAE1S7yxvGII9dYPHW0ayI3k0gRXDRpYiULDw6MtmfFdJxhbPUY 1zJiXNV21IkfwTBbIKVsmFORa+M2oCZ6+i+w7ygR6ZQzfsdXp8HhTtcfQoO3OePb 5RStFJiWvme+YVrdZ911Zo8P00EwmC6036mDVLfB6QKy53q/w4JOyxUGEKFXZl5b B8D4r6Lo1PfRoSOTWQWq7NDzhuNjpDppu1K0aXATem1xpePTwNfZi49FcAxTMYMB 7HuI2A== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437tstepq0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Dec 2024 03:32:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WEeY003570 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:14 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:14 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:41 -0800 Subject: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock binding Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-3-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733196732; l=4326; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=WOGgVxaSyvealCotRclm+4BylMOthHPB34gcr+z71s8=; b=/HH69Y2AK4ZWZz3GL7UWlJlCQCqMWMFIsmXhLWyPJp+a6LSKM2T3qLbk25ZR1zVKOL6iuSd/I 2LiI614tW5TAAyCJLJEgG6bmFyHTPzQkQT+1urSoZliQEGUSM2GzlqE X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 8BVxJ41RklhKrqVG9iUk9MLrvvPyWkpb X-Proofpoint-GUID: 8BVxJ41RklhKrqVG9iUk9MLrvvPyWkpb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030028 On some chipsets the display port controller can support more than one pixel stream (multi-stream transport). To support MST on such chipsets, add the binding for stream 1 pixel clock for display port controller. Since this mode is not supported on all chipsets, add exception rules and min/max items to clearly mark which chipsets support only SST mode (single stream) and which ones support MST. Signed-off-by: Abhinav Kumar --- .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++ .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9fe2bf0484d8..650d19e58277 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -50,30 +50,38 @@ properties: maxItems: 1 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel + - const: stream_1_pixel assigned-clocks: + minItems: 2 items: - description: link clock source - description: stream 0 pixel clock source + - description: stream 1 pixel clock source assigned-clock-parents: + minItems: 2 items: - description: Link clock PLL output provided by PHY block - description: Stream 0 pixel clock PLL output provided by PHY block + - description: Stream 1 pixel clock PLL output provided by PHY block phys: maxItems: 1 @@ -175,6 +183,30 @@ allOf: required: - "#sound-dai-cells" + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + + then: + properties: + clocks: + maxItems: 6 + clock-names: + items: + - const: core_iface + - const: core_aux + - const: ctrl_link + - const: ctrl_link_iface + - const: stream_pixel + - const: stream_1_pixel + assigned-clocks: + maxItems: 3 + assigned-clock-parents: + maxItems: 3 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index 58f8a01f29c7..7f10e6ad8f63 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -177,16 +177,19 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>, <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; + assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>, <&mdss0_edp_phy 1>; phys = <&mdss0_edp_phy>; phy-names = "dp"; From patchwork Tue Dec 3 03:31:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhinav Kumar X-Patchwork-Id: 13891664 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36A853F9D2; Tue, 3 Dec 2024 03:32:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196748; cv=none; b=HHWcJk4M9tt9CaxjLpR63eWEmgRxSPQFdUx6ZGL6/EehteQ9Sbt5f1hNvrv2eBS0Zgkbwc5wp9s/YbxOOCfhQPmD5TbFhvJtyOylvCyux75l6qk6ZDF0ZRYKY1HoXX/FOStV8QZTIDBeUh1gEX+BNPtwyx33jXNQn8kcfgNqF2s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733196748; c=relaxed/simple; bh=HakEq3N95BMIIM8PvAiGX6Tyi359l/c7+yzyHgH238I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nJeiZd273+5CnDLwb7bYMZ3LeIh6UYZnIMQKsEdkslKGszZMA+Uf1Dq0h5lZeO5zGjBx3XR7Jtj1SXuS/UXnxKF4azwXuBPeSuTNRHlEMu2AhxIXcp/iB0QX8iMn+ZjY/1VsWmZrQ9ncQb/zusDIIcQzBnJspD70jP8adS+Q6yo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=gOBD5e8r; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="gOBD5e8r" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B2HYOov000533; Tue, 3 Dec 2024 03:32:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= z+R+UM++NH21AZ0ur5MVMvElzBMLjkujEXByMCIj7/w=; b=gOBD5e8rkbliSOS3 PdmvF6A/CzxpWQVI75obD9gJPa3IORMeRNnjqGr3KqD8KFnc/kKwB7vhUXBjkCk7 OBgH4xArROqOQQwd2JMplq4Rm0EcLDwk9EtNYvn3KJEmV4EriSfykLBseuaOqDKO aGTWSwUtdfKxCIVyMfP9k0kU/+YsjXR2wPG9/6J4+GqaQ4NHgSjQ2KNtVpmY3GJ8 X9ueRbt6ezi+zgW7JNsddFgIh+FDSrs8jtOrfSCr2MWpZfry1BCqs8xZdYqMDF2p U7OWwLjBA9q35jz7NrJBU1AlDQQHPhApifR63jP8cQtZWfEdpwYVMLaDe5sjg9HZ XkKOvA== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 437r2mxxad-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Dec 2024 03:32:16 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B33WFhX003573 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 03:32:15 GMT Received: from abhinavk-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 19:32:14 -0800 From: Abhinav Kumar Date: Mon, 2 Dec 2024 19:31:42 -0800 Subject: [PATCH 4/4] dt-bindings: display: msm: dp: update maintainer entry Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241202-dp_mst_bindings-v1-4-9a9a43b0624a@quicinc.com> References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> In-Reply-To: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> To: Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Simona Vetter" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan CC: , , , , , Abhinav Kumar X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733196732; l=871; i=quic_abhinavk@quicinc.com; s=20240509; h=from:subject:message-id; bh=HakEq3N95BMIIM8PvAiGX6Tyi359l/c7+yzyHgH238I=; b=s9j5zjatjgOO5bNtG2zAChI5qkNVND1C8bvlUCCjT1Q0wUxVMgT0gmOFn2vPpUb6a6QOOtTKq hT+dzUMnoQuA0aa8lOv+SkH8ZGWgaw59BXSbKQel/wJdnZWRCR5bsP/ X-Developer-Key: i=quic_abhinavk@quicinc.com; a=ed25519; pk=SD3D8dOKDDh6BoX3jEYjsHrTFwuIK8+o0cLPgQok9ys= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: NZfElm75zQbQHrJ519NnY-6oHkWwqdzY X-Proofpoint-GUID: NZfElm75zQbQHrJ519NnY-6oHkWwqdzY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 phishscore=0 mlxlogscore=878 clxscore=1015 mlxscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030028 Add myself as maintainer for dp controller yaml as to support review of the incoming changes. Signed-off-by: Abhinav Kumar --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 650d19e58277..9867eb5133ab 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -8,6 +8,7 @@ title: MSM Display Port Controller maintainers: - Kuogee Hsieh + - Abhinav Kumar description: | Device tree bindings for DisplayPort host controller for MSM targets