From patchwork Tue Dec 3 10:49:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892116 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D50261DDA37; Tue, 3 Dec 2024 10:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223042; cv=none; b=rSAzAdPfieu18j9c3WfgFfSmw/JKnqAqsLGEKHcN/uT6LdVFfBmWAl4HJrr3O7FyS7vmpuhttkv274s078Qh7QaTWuQsntMkVHtD1nBZmljx5zkIyIxMncoouocaohZ0ojxXlRCfdCvqC/CiuNe2rfIqlP/CaRXdqAuV7OCHqFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223042; c=relaxed/simple; bh=H+aZeWO1C99Vy3dMeHF6AwCee+MLij92uMHaEAwmYf4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UGKOSiFiNlfXhVLWWFp78t3kMIs8zVDSXXE5VCgnBw2NlXIobbrHDzIRlJhGUUwF7zQZNiHDOZtSXLni9LlojyJPc3lTqYkvjTsOCHjZsrWKxxka++LEE0PysQoa63DkyQICHhUsIa+bCvojvgEpgHi0qU9KPJ+ztFek+5ONM1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: elaYuPkqQ0+qL09p5QgKYQ== X-CSE-MsgGUID: WyWNG/DvSy6bgv8uZrIbGA== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754406" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:38 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0808D4003FA5; Tue, 3 Dec 2024 19:50:12 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Greg Kroah-Hartman , Jiri Slaby , Geert Uytterhoeven , Magnus Damm , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: [PATCH v2 01/13] dt-bindings: serial: renesas: Document RZ/G3E (r9a09g047) scif Date: Tue, 3 Dec 2024 10:49:28 +0000 Message-ID: <20241203105005.103927-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document scif bindings for the Renesas RZ/G3E (a.k.a r9a09g047) SoC. SCIF interface in Renesas RZ/G3E is similar to the one available in RZ/V2H. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Collected Ack from Conor Dooley. --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml index 51d9fb0f4763..8e82999e6acb 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -83,6 +83,11 @@ properties: - const: renesas,scif-r9a09g057 # RZ/V2H(P) + - items: + - enum: + - renesas,scif-r9a09g047 # RZ/G3E + - const: renesas,scif-r9a09g057 # RZ/V2H fallback + reg: maxItems: 1 From patchwork Tue Dec 3 10:49:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892133 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8B0AC1E2842; Tue, 3 Dec 2024 10:55:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223339; cv=none; b=iR70EdlF0lCBP6vBP7+aRdSqePaL0mv+O8rgCfIaeBkFjv7hSaoVatM5iweJ3OLy3+YP0w0J+zUqB/O8VI4cHREU/KwhxproMBbWvc2mNi3jmDf46AybVgur0WSLoUH1Qa8WyAtLWCplerDEFef3Lb05RS9HutaPhsN2R66mzhg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223339; c=relaxed/simple; bh=BkS5NGLe+XrlU8Nq40oJSaeQ2ynDfiztyTGzi3onipY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I4pHIxIK7wsipytbD2uKaNbAfATlE+cUGFlQpMyGTlax2uH9WwlwT0MGbiaxSGKMGnMvwdTnkLqRgsQy61qNFO/THVgY3fUpoC5ScKbZ+e7CPr+UdOtzHo+QRoBxLYnWTE2Y0bshkAJepyblnEnInw5JpihTx7/6u6cSHEnQfKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: Uptgq1wuS3Wh/3rlvYxjLA== X-CSE-MsgGUID: MrAZ5pN6SBaU77V8JpU+qQ== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754379" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:26 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7D5A4400753A; Tue, 3 Dec 2024 19:50:17 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Conor Dooley Subject: [PATCH v2 02/13] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Date: Tue, 3 Dec 2024 10:49:29 +0000 Message-ID: <20241203105005.103927-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document Renesas RZ/G3E (R9A09G047) SoC variants. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Collected Ack tag from Conor Dooley --- .../devicetree/bindings/soc/renesas/renesas.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index b7acb65bdecd..7cc2bb97db13 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -525,6 +525,19 @@ properties: - renesas,rzv2mevk2 # RZ/V2M Eval Board v2.0 - const: renesas,r9a09g011 + - description: RZ/G3E (R9A09G047) + items: + - enum: + - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) + - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) + - renesas,r9a09g047e48 # Quad Cortex-A55 + Cortex-M33 (21mm BGA) + - renesas,r9a09g047e47 # Quad Cortex-A55 + Cortex-M33 (15mm BGA) + - renesas,r9a09g047e38 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) + - renesas,r9a09g047e37 # Dual Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) + - renesas,r9a09g047e28 # Dual Cortex-A55 + Cortex-M33 (21mm BGA) + - renesas,r9a09g047e27 # Dual Cortex-A55 + Cortex-M33 (15mm BGA) + - const: renesas,r9a09g047 + - description: RZ/V2H(P) (R9A09G057) items: - enum: From patchwork Tue Dec 3 10:49:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892134 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5F3121E2853; Tue, 3 Dec 2024 10:55:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223340; cv=none; b=kzHFN7paZ+S0a2KWOJqy4iZ5q6+qHQEnEltQ5o1HNc7aU9+otzO/e14NzHrXMpPqJfWatWV10mFY1R4Ih+TnkRnOY0JTa2bGRX1inK8wGlEV4rE43qRP2hjsCeCs/j7AI0BXTxjpwY/U6b4DW9p1LCdqRxB6SI0k5cCjBTerCow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223340; c=relaxed/simple; bh=SaRPBbEw/J0MvD3sGG9Zw9g/JlBMBuJYa5d5CPyRo/M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IQTmCPpD2xBUm8Z9Tq5lrxNoEyJpiudkHuCV3HdZ55a/sDxaTrxoutfLkIQOA95ddTyV5D+Cr6l/NS5X0Zz9SsMjHXunV76NYKLia02FlZLuMiYN8nsMskBsWAfXnUevakarvo7YGMn4ogwAAnolr22CWgAujgboZQ90/3U+oGk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: /jte91FxSLasgxybh1sA3Q== X-CSE-MsgGUID: 067r4LIwQwGlC9PXfpXY2g== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754383" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:26 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 342654005634; Tue, 3 Dec 2024 19:50:20 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 03/13] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Date: Tue, 3 Dec 2024 10:49:30 +0000 Message-ID: <20241203105005.103927-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the Renesas RZ/G3E SMARC Carrier-II EVK board which is based on the Renesas RZ/G3E SMARC SoM. The RZ/G3E SMARC Carrier-II EVK consists of an RZ/G3E SoM module and a SMARC Carrier-II carrier board. The SoM module sits on top of the carrier board. Signed-off-by: Biju Das Acked-by: Rob Herring (Arm) --- v1->v2: * No change. --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 7cc2bb97db13..1785142fc8da 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -527,6 +527,10 @@ properties: - description: RZ/G3E (R9A09G047) items: + - enum: + - renesas,smarc2-evk # RZ SMARC Carrier-II EVK + - enum: + - renesas,rzg3e-smarcm # RZ/G3E SMARC Module (SoM) - enum: - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA) - renesas,r9a09g047e57 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (15mm BGA) From patchwork Tue Dec 3 10:49:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892137 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C98EC1E284A; Tue, 3 Dec 2024 10:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223351; cv=none; b=Iog8UDY9bCor3ePaWBoRA86bjgAKBz0G/jem4ci5SyA2XA1emlTDPpIpSbafc5i/dtz2Db/ULu4GnowLvFV1AeEmXCMUB0MG1/2XmmYcHlFoO29OzHlXtPvzJ/WzZ6JfSlLdx9ib+V7ki/NT/lakcp9qHnm8mH6stBjd6wOZpwk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223351; c=relaxed/simple; bh=il5uQxRRwe3m1cW8/aVHsvKrWXrxpCQj0vVq+9VUl88=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=siRdRtgfXIzlXYmKDCYjJr5QKAMQWuvlYV3/gU/zkltX9FnbpgVzNNTE0J4ekE6GV+VUZOR1c54hvb5YYAXaSX8YFUz4jJhA/MZ4V3b/yBRg85bAQ36CVPNLcljNHzxWCW4o4aRyHgc6H7/xWx8CDToBLVSfEUGUcsnZrETt9OA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: r4vTt+CxSIOfAhlqah7OKQ== X-CSE-MsgGUID: YrcfNOrUQZ6zR4nofdf4Ig== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="226779505" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:40 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9A6DA4003FA4; Tue, 3 Dec 2024 19:50:24 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Biju Das , Conor Dooley Subject: [PATCH v2 04/13] dt-bindings: clock: renesas: Document RZ/G3E SoC CPG Date: Tue, 3 Dec 2024 10:49:31 +0000 Message-ID: <20241203105005.103927-5-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley Signed-off-by: Biju Das --- v1->v2: * Added Ack from Conor Dooley. * Fixed typo "CORE_CLK*"->"CORECLK*" to match with hardware manual. --- .../bindings/clock/renesas,rzv2h-cpg.yaml | 15 +++++++------ .../dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 +++++++++++++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 include/dt-bindings/clock/renesas,r9a09g047-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index 926c503bed1f..c3fe76abd549 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,19 +4,22 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) maintainers: - Lad Prabhakar description: - On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation - and control of clock signals for the IP modules, generation and control of resets, - and control over booting, low power consumption and power supply domains. + On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + generation and control of clock signals for the IP modules, generation and + control of resets, and control over booting, low power consumption and power + supply domains. properties: compatible: - const: renesas,r9a09g057-cpg + enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H reg: maxItems: 1 @@ -37,7 +40,7 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - , + , - For module clocks, the two clock specifier cells must be "CPG_MOD" and a module number. The module number is calculated as the CLKON register offset index multiplied by 16, plus the actual bit in the register diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ From patchwork Tue Dec 3 10:49:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892135 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A2D231E2842 for ; Tue, 3 Dec 2024 10:55:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223341; cv=none; b=O1+SA4e1T91EKKJ0WmPfKZPToHebwL+LDboLwJPNDlEOp1Lt9pPgnw1QKbBVoOoR8JAAxktM5NkaDVybgam5z/hSi7Yy7bKu/p0f+0ilMGlxu2M0AMcCKIBeouFxWg8V5HScDHDFmp3nNN3coeFW8YE5Xgkkv1OT+Giz4nVOlrw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223341; c=relaxed/simple; bh=7igNhRGV/N7xzAJJl1ESRfzqC83aDTGC6g9/qty1qcg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VE1uvXPhp0BAOY7j8/l4tFojTw4kurDdHeSvZ/txJJvxydlBDrVUXP2vAyqavvi2TA3SSPHu41/eDFlgyVGd+qiFTD4X3wQ20nROAF/YnlYCNaWZCT13twWoFKeVd65EuKDu8uWC4PjATg+IKTqZrdoO+uw+mSFQQHidrOeksuM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: +/8uJEpPQ2eabPAcpyckRQ== X-CSE-MsgGUID: vuYGDpL4SqiC34Y7EgDjMw== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754394" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:36 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1E69E400753A; Tue, 3 Dec 2024 19:50:28 +0900 (JST) From: Biju Das To: Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 05/13] soc: renesas: Add RZ/G3E (R9A09G047) config option Date: Tue, 3 Dec 2024 10:49:32 +0000 Message-ID: <20241203105005.103927-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a configuration option for the RZ/G3E SoC. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/soc/renesas/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 9f7fe02310b9..6d2e135eed89 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -345,6 +345,11 @@ config ARCH_R9A09G011 help This enables support for the Renesas RZ/V2M SoC. +config ARCH_R9A09G047 + bool "ARM64 Platform support for RZ/G3E" + help + This enables support for the Renesas RZ/G3E SoC variants. + config ARCH_R9A09G057 bool "ARM64 Platform support for RZ/V2H(P)" select RENESAS_RZV2H_ICU From patchwork Tue Dec 3 10:49:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892117 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2CD801DDA37; Tue, 3 Dec 2024 10:50:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223045; cv=none; b=GFszVbn+FiZC5Vyy7dVsynmry1u0caymMn5+nrROgcu3BQ1jowc5m16o5aiGmfEJpmhwI1ivwVUptzk5PbWZ5fp2724gpAAWJLHCmNzfa+DiXWcdoZOWKlWN+MUsk1wvTCIOhbmj6/GIRwlny6U0+Nr9RCtyqQR7PkWs5IYt/XU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223045; c=relaxed/simple; bh=FcaYsPwrLK3ZqoRhidvcE0etwCXxgZRYqtlhKQkntBI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oy8yEGWCSSKUPN0J24XfFNO17ZS/KgQIL4dqyuj4NXU2bQpEO6Sdw2/wXsXBpbtewuCGJS2NJHU9W+OkHvrZ8jga3AZy5jFp0MY+iuesSyuGSYP374YoPrfPcmvp9kGpHtE/nW8DsWdblQ12J7VCtuDKjKLj0ExX+ohjKjCwLc4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: xo2p3+PHTyuoVpmJzaMLDQ== X-CSE-MsgGUID: Nd9GqulZTteRNK0eBOEcwg== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754411" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:42 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 7900F40061AD; Tue, 3 Dec 2024 19:50:31 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 06/13] clk: renesas: Add support for RZ/G3E SoC Date: Tue, 3 Dec 2024 10:49:33 +0000 Message-ID: <20241203105005.103927-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1 are present only on the RZ/G3E SoC. Add minimal clock and reset entries required to boot the Renesas RZ/G3E SMARC EVK and binds it with the RZ/V2H CPG core driver. Signed-off-by: Biju Das --- v1->v2: * No change. --- drivers/clk/renesas/Kconfig | 7 ++- drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g047-cpg.c | 98 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 6 ++ drivers/clk/renesas/rzv2h-cpg.h | 1 + 5 files changed, 112 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/renesas/r9a09g047-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index ff01f5f0ed20..5a4bc3f94d49 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -40,6 +40,7 @@ config CLK_RENESAS select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 + select CLK_R9A09G047 if ARCH_R9A09G047 select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_SH73A0 if ARCH_SH73A0 @@ -194,6 +195,10 @@ config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A09G047 + bool "RZ/G3E clock support" if COMPILE_TEST + select CLK_RZV2H + config CLK_R9A09G057 bool "RZ/V2H(P) clock support" if COMPILE_TEST select CLK_RZV2H @@ -234,7 +239,7 @@ config CLK_RZG2L select RESET_CONTROLLER config CLK_RZV2H - bool "RZ/V2H(P) family clock support" if COMPILE_TEST + bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST select RESET_CONTROLLER config CLK_RENESAS_VBATTB diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 82efaa835ac7..2d6e746939c4 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o +obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c new file mode 100644 index 000000000000..5d7611cee9bc --- /dev/null +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G3E CPG driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzv2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK, + + /* External Input Clocks */ + CLK_AUDIO_EXTAL, + CLK_RTXIN, + CLK_QEXTAL, + + /* PLL Clocks */ + CLK_PLLCM33, + CLK_PLLDTY, + CLK_PLLCA55, + + /* Internal Core Clocks */ + CLK_PLLCM33_DIV16, + CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct clk_div_table dtable_2_64[] = { + {0, 2}, + {1, 4}, + {2, 8}, + {3, 16}, + {4, 64}, + {0, 0}, +}; + +static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), + DEF_INPUT("rtxin", CLK_RTXIN), + DEF_INPUT("qextal", CLK_QEXTAL), + + /* PLL Clocks */ + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), + + /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + + DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), + + /* Core Clocks */ + DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), +}; + +static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), +}; + +static const struct rzv2h_reset r9a09g047_resets[] __initconst = { + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ +}; + +const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { + /* Core Clocks */ + .core_clks = r9a09g047_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g047_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks = r9a09g047_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks), + .num_hw_mod_clks = 28 * 16, + + /* Resets */ + .resets = r9a09g047_resets, + .num_resets = ARRAY_SIZE(r9a09g047_resets), +}; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 1154493583a7..ef26e7760a88 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -868,6 +868,12 @@ static const struct of_device_id rzv2h_cpg_match[] = { .compatible = "renesas,r9a09g057-cpg", .data = &r9a09g057_cpg_info, }, +#endif +#ifdef CONFIG_CLK_R9A09G047 + { + .compatible = "renesas,r9a09g047-cpg", + .data = &r9a09g047_cpg_info, + }, #endif { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index ed8d2cad3260..1e5bf1eb65a4 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -202,6 +202,7 @@ struct rzv2h_cpg_info { unsigned int num_resets; }; +extern const struct rzv2h_cpg_info r9a09g047_cpg_info; extern const struct rzv2h_cpg_info r9a09g057_cpg_info; #endif /* __RENESAS_RZV2H_CPG_H__ */ From patchwork Tue Dec 3 10:49:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892136 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E91C1E2853 for ; Tue, 3 Dec 2024 10:55:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223343; 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d="scan'208";a="230754398" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:37 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 653C040015FF; Tue, 3 Dec 2024 19:50:34 +0900 (JST) From: Biju Das To: Michael Turquette , Stephen Boyd Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 07/13] clk: renesas: rzv2h-cpg: Add MSTOP support Date: Tue, 3 Dec 2024 10:49:34 +0000 Message-ID: <20241203105005.103927-8-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add bus MSTOP support for RZ/{V2H, G3E}. For some module clocks, there are no MSTOP bits and the sequence ordering for mstop and clock on is different compared to the RZ/G2L family. Signed-off-by: Biju Das --- v1->v2: * This patch has dependency on [1] * Added MSTOP data for RZ/V2H CRU IP. * Fixed typo clock->clk in error path of rzv2h_cpg_register_mod_clk() [1] https://lore.kernel.org/all/20241202203916.48668-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ --- drivers/clk/renesas/r9a09g047-cpg.c | 6 +- drivers/clk/renesas/r9a09g057-cpg.c | 153 ++++++++++++++++++---------- drivers/clk/renesas/rzv2h-cpg.c | 92 ++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 26 +++-- 4 files changed, 214 insertions(+), 63 deletions(-) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 5d7611cee9bc..ab63a7e7e480 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -69,8 +69,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { - DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19), - DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, + BUS_MSTOP(3, BIT(5))), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, + BUS_MSTOP(3, BIT(14))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 5aa9710aa402..5539fdb13d57 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -115,57 +115,108 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { - DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5), - DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3), - DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4), - DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5), - DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6), - DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7), - DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8), - DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9), - DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10), - DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11), - DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12), - DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13), - DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14), - DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15), - DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16), - DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17), - DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18), - DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), - DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19), - DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20), - DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21), - DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22), - DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23), - DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24), - DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25), - DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26), - DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27), - DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3), - DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4), - DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5), - DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6), - DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7), - DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8), - DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9), - DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10), - DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11), - DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12), - DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13), - DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14), - DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18), - DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19), - DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20), - DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21), - DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22), - DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23), - DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24), - DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25), - DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26), - DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27), - DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28), - DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29), + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NO_DATA), + DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, + BUS_MSTOP(5, BIT(10))), + DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, + BUS_MSTOP(5, BIT(11))), + DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, + BUS_MSTOP(2, BIT(13))), + DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, + BUS_MSTOP(2, BIT(14))), + DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, + BUS_MSTOP(11, BIT(13))), + DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, + BUS_MSTOP(11, BIT(14))), + DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, + BUS_MSTOP(11, BIT(15))), + DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, + BUS_MSTOP(12, BIT(0))), + DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, + BUS_MSTOP(3, BIT(10))), + DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, + BUS_MSTOP(3, BIT(10))), + DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, + BUS_MSTOP(5, BIT(13))), + DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, + BUS_MSTOP(5, BIT(13))), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, + BUS_MSTOP(3, BIT(14))), + DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, + BUS_MSTOP(3, BIT(13))), + DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, + BUS_MSTOP(1, BIT(1))), + DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, + BUS_MSTOP(1, BIT(2))), + DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, + BUS_MSTOP(1, BIT(3))), + DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, + BUS_MSTOP(1, BIT(4))), + DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, + BUS_MSTOP(1, BIT(5))), + DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, + BUS_MSTOP(1, BIT(6))), + DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, + BUS_MSTOP(1, BIT(7))), + DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, + BUS_MSTOP(1, BIT(8))), + DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, + BUS_MSTOP_NO_DATA), + DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, + BUS_MSTOP_NO_DATA), + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, + BUS_MSTOP(9, BIT(4))), + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, + BUS_MSTOP(9, BIT(4))), + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, + BUS_MSTOP(9, BIT(4))), + DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, + BUS_MSTOP(9, BIT(5))), + DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, + BUS_MSTOP(9, BIT(5))), + DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, + BUS_MSTOP(9, BIT(5))), + DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, + BUS_MSTOP(9, BIT(6))), + DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, + BUS_MSTOP(9, BIT(6))), + DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, + BUS_MSTOP(9, BIT(6))), + DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, + BUS_MSTOP(9, BIT(7))), + DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, + BUS_MSTOP(9, BIT(7))), + DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, + BUS_MSTOP(9, BIT(7))), }; static const struct rzv2h_reset r9a09g057_resets[] __initconst = { diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index ef26e7760a88..fb5221faabea 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -83,6 +84,11 @@ struct rzv2h_cpg_priv { #define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev) +struct rzv2h_mstop { + u32 data; + refcount_t ref_cnt; +}; + struct pll_clk { struct rzv2h_cpg_priv *priv; void __iomem *base; @@ -97,6 +103,7 @@ struct pll_clk { * struct mod_clock - Module clock * * @priv: CPG private data + * @mstop: handle to cpg bus mstop data * @hw: handle between common and hardware-specific interfaces * @no_pm: flag to indicate PM is not supported * @on_index: register offset @@ -106,6 +113,7 @@ struct pll_clk { */ struct mod_clock { struct rzv2h_cpg_priv *priv; + struct rzv2h_mstop *mstop; struct clk_hw hw; bool no_pm; u8 on_index; @@ -433,6 +441,38 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, core->name, PTR_ERR(clk)); } +static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, + struct mod_clock *clock) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&priv->rmw_lock, flags); + if (!refcount_read(&clock->mstop->ref_cnt)) { + val = BUS_MSTOP_VAL(clock->mstop->data) << 16; + writel(val, priv->base + BUS_MSTOP_OFF(clock->mstop->data)); + refcount_set(&clock->mstop->ref_cnt, 1); + } else { + refcount_inc(&clock->mstop->ref_cnt); + } + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + +static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv, + struct mod_clock *clock) +{ + unsigned long flags; + u32 val; + + spin_lock_irqsave(&priv->rmw_lock, flags); + if (refcount_dec_and_test(&clock->mstop->ref_cnt)) { + val = BUS_MSTOP_VAL(clock->mstop->data) << 16 | + BUS_MSTOP_VAL(clock->mstop->data); + writel(val, priv->base + BUS_MSTOP_OFF(clock->mstop->data)); + } + spin_unlock_irqrestore(&priv->rmw_lock, flags); +} + static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) { struct mod_clock *clock = to_mod_clock(hw); @@ -447,10 +487,16 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) enable ? "ON" : "OFF"); value = bitmask << 16; - if (enable) + if (enable) { value |= bitmask; - - writel(value, priv->base + reg); + writel(value, priv->base + reg); + if (clock->mstop) + rzv2h_mod_clock_mstop_enable(priv, clock); + } else { + if (clock->mstop) + rzv2h_mod_clock_mstop_disable(priv, clock); + writel(value, priv->base + reg); + } if (!enable || clock->mon_index < 0) return 0; @@ -500,6 +546,38 @@ static const struct clk_ops rzv2h_mod_clock_ops = { .is_enabled = rzv2h_mod_clock_is_enabled, }; +static struct rzv2h_mstop +*rzv2h_cpg_get_mstop(struct rzv2h_cpg_priv *priv, u32 mstop_data) +{ + struct rzv2h_mstop *mstop; + unsigned int i; + + for (i = 0; i < priv->num_mod_clks; i++) { + struct mod_clock *clk; + struct clk_hw *hw; + + if (priv->clks[priv->num_core_clks + i] == ERR_PTR(-ENOENT)) + continue; + + hw = __clk_get_hw(priv->clks[priv->num_core_clks + i]); + clk = to_mod_clock(hw); + if (!clk->mstop) + continue; + + if (clk->mstop->data == mstop_data) + return clk->mstop; + } + + mstop = devm_kzalloc(priv->dev, sizeof(*mstop), GFP_KERNEL); + if (!mstop) + return NULL; + + mstop->data = mstop_data; + refcount_set(&mstop->ref_cnt, 0); + + return mstop; +} + static void __init rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, struct rzv2h_cpg_priv *priv) @@ -555,6 +633,14 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, priv->clks[id] = clock->hw.clk; + if (mod->mstop_data != BUS_MSTOP_NO_DATA) { + clock->mstop = rzv2h_cpg_get_mstop(priv, mod->mstop_data); + if (!clock->mstop) { + clk = ERR_PTR(-ENOMEM); + goto fail; + } + } + return; fail: diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 1e5bf1eb65a4..8c94a02d5147 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -35,6 +35,7 @@ struct ddiv { #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CPG_BUS_1_MSTOP (0xd00) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) @@ -46,6 +47,14 @@ struct ddiv { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) +#define CPG_BUS_MSTOP_START (CPG_BUS_1_MSTOP - 4) +#define CPG_BUS_MSTOP(x) (CPG_BUS_MSTOP_START + (x) * 4) + +#define BUS_MSTOP(index, mask) ((CPG_BUS_MSTOP(index) & 0xffff) << 16 | (mask)) +#define BUS_MSTOP_OFF(val) (((val) >> 16) & 0xffff) +#define BUS_MSTOP_VAL(val) ((val) & 0xffff) +#define BUS_MSTOP_NO_DATA GENMASK(31, 0) + /** * Definitions of CPG Core Clocks * @@ -104,6 +113,7 @@ enum clk_types { * struct rzv2h_mod_clk - Module Clocks definitions * * @name: handle between common and hardware-specific interfaces + * @mstop_data: packed data mstop register offset and mask * @parent: id of parent clock * @critical: flag to indicate the clock is critical * @no_pm: flag to indicate PM is not supported @@ -114,6 +124,7 @@ enum clk_types { */ struct rzv2h_mod_clk { const char *name; + u32 mstop_data; u16 parent; bool critical; bool no_pm; @@ -123,9 +134,10 @@ struct rzv2h_mod_clk { u8 mon_bit; }; -#define DEF_MOD_BASE(_name, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ +#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, _onbit, _monindex, _monbit) \ { \ .name = (_name), \ + .mstop_data = (_mstop), \ .parent = (_parent), \ .critical = (_critical), \ .no_pm = (_no_pm), \ @@ -135,14 +147,14 @@ struct rzv2h_mod_clk { .mon_bit = (_monbit), \ } -#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, false, false, _onindex, _onbit, _monindex, _monbit) +#define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _monindex, _monbit) -#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, true, false, _onindex, _onbit, _monindex, _monbit) +#define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _monindex, _monbit) -#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ - DEF_MOD_BASE(_name, _parent, false, true, _onindex, _onbit, _monindex, _monbit) +#define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mstop) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _monindex, _monbit) /** * struct rzv2h_reset - Reset definitions From patchwork Tue Dec 3 10:49:35 2024 Content-Type: text/plain; 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Signed-off-by: Biju Das --- v2: * New patch. --- drivers/clk/renesas/r9a09g047-cpg.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index ab63a7e7e480..d4c119c06d06 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -37,6 +37,14 @@ enum clk_ids { MOD_CLK_BASE, }; +static const struct clk_div_table dtable_1_8[] = { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] = { {0, 2}, {1, 4}, @@ -65,6 +73,14 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55, + CDDIV1_DIVCTL0, dtable_1_8), + DEF_DDIV("ca55_0_coreclk1", R9A09G047_CA55_0_CORECLK1, CLK_PLLCA55, + CDDIV1_DIVCTL1, dtable_1_8), + DEF_DDIV("ca55_0_coreclk2", R9A09G047_CA55_0_CORECLK2, CLK_PLLCA55, + CDDIV1_DIVCTL2, dtable_1_8), + DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55, + CDDIV1_DIVCTL3, dtable_1_8), DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), }; From patchwork Tue Dec 3 10:49:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892118 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A085E1E25F0; Tue, 3 Dec 2024 10:50:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223046; cv=none; b=SOBXryXEDh+beeFN2z0g8gCMIzEMngWsEpoew/eBE5lgnbInDPIxS8bBxRkjEiBwi8+vi1U9011lg9xvmtSd04lFIoVIVy9DWLExus9QJ+LsNPzEHnKBXHMPimhgLM2cl/nLIy33vxdaHi5O7nccb/UWaRIxSnvSmMJTUvTWkCo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223046; c=relaxed/simple; bh=0o4J4J8nc2g+xgTx0PcuHy4Ujy7JYoHu87x6kLgXW8M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=maF4+LOnl7j5DYSLu3sno+dP9eE8NCNmIDPo8Nh8BDRLRbzsuSZq6uHZG2YwLZOyjxHTf+8EIb4QbNA64WGcvxccvcxjuDjEgzWSk7Rfm51GgZkZQfTggM907WMGur+6Ks0DB3qKzzRUjMif9B7igZCPR8KmRzuCXCK7v39MNSU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: acGjIY8xRmqVWZGWVr8SXg== X-CSE-MsgGUID: kL9QiM0tRzabTjBlJOKxkg== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754414" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:43 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B93A040062A5; Tue, 3 Dec 2024 19:50:40 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 09/13] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Date: Tue, 3 Dec 2024 10:49:36 +0000 Message-ID: <20241203105005.103927-10-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the initial DTSI for the RZ/G3E SoC. The files in this commit have the following meaning: - r9a09g047.dtsi: RZ/G3E family SoC common parts - r9a09g047e57.dtsi: RZ/G3E R0A09G047E{4,5}{7,8} SoC specific parts - r9a09g047e37.dtsi: RZ/G3E R0A09G047E{2,3}{7,8} SoC specific parts Signed-off-by: Biju Das --- v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 144 ++++++++++++++++++ arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 +++ arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi | 13 ++ 3 files changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi new file mode 100644 index 000000000000..4176b9aa6892 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g047"; + #address-cells = <2>; + #size-cells = <2>; + + audio_extal_clk: audio-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + qextal_clk: qextal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + rtxin_clk: rtxin-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@10420000 { + compatible = "renesas,r9a09g047-cpg"; + reg = <0 0x10420000 0 0x10000>; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; + clock-names = "audio_extal", "rtxin", "qextal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + scif0: serial@11c01400 { + compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; + reg = <0 0x11c01400 0 0x400>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", + "tei", "tei-dri", "rxi-edge", "txi-edge"; + clocks = <&cpg CPG_MOD 0x8f>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg 0x95>; + status = "disabled"; + }; + + gic: interrupt-controller@14900000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x14900000 0 0x20000>, + <0x0 0x14940000 0 0x80000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi new file mode 100644 index 000000000000..e50d9159e832 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g047.dtsi" + +/ { + compatible = "renesas,r9a09g047e37", "renesas,r9a09g047"; + + cpus { + /delete-node/ cpu@200; + /delete-node/ cpu@300; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi new file mode 100644 index 000000000000..98a5faebd47a --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E R9A09G047E57 SoC specific parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g047.dtsi" + +/ { + compatible = "renesas,r9a09g047e57", "renesas,r9a09g047"; +}; From patchwork Tue Dec 3 10:49:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892138 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D26D71E284A; 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dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: jztms97SRcSZB/edsqLEDw== X-CSE-MsgGUID: Zg6UYKAfTsinPunOAy1A7w== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="226779510" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:47 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 3635540062A5; Tue, 3 Dec 2024 19:50:43 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 10/13] arm64: dts: renesas: r9a09g047: Add OPP table Date: Tue, 3 Dec 2024 10:49:37 +0000 Message-ID: <20241203105005.103927-11-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add OPP table for RZ/G3E SoC. Signed-off-by: Biju Das --- v2: * New patch. --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 4176b9aa6892..39a7cfb3095b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + /* + * The default cluster table is based on the assumption that the PLLCA55 clock + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be + * clocked to 1.8GHz as well). The table below should be overridden in the board + * DTS based on the PLLCA55 clock frequency. + */ + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <900000>; + clock-latency-ns = <300000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-425000000 { + opp-hz = /bits/ 64 <425000000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + }; + opp-212500000 { + opp-hz = /bits/ 64 <212500000>; + opp-microvolt = <800000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -30,6 +63,8 @@ cpu0: cpu@0 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -38,6 +73,8 @@ cpu1: cpu@100 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -46,6 +83,8 @@ cpu2: cpu@200 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -54,6 +93,8 @@ cpu3: cpu@300 { device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From patchwork Tue Dec 3 10:49:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892120 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 252FE1DE4FD; Tue, 3 Dec 2024 10:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223057; cv=none; b=K08W6HD4EnDjTRUyqXjOuOghZCTFoVtQw8wVzyEvQOPuEDpgzCs73+jpCHwjUl0/dCPaVekAwXqtiiyXXsrAn3u3h5+e/1VMcZNJFNinvasKwNooysdITHyzbbxevH9rZLcS5N1PpjqyrfTP5Kck1/flGOAr2KSjLdwv1a+eDm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223057; c=relaxed/simple; bh=SAczOtyShWB7VFtkQ2ixtcmfUdisJH5FWg83dTyKaZQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RUdNBh6xPO6nqT8burBUG1Q+mgdnb06NBXZsQUjdfEKeSBheuXjBnoItw8JZHyvedpske5XkmjL6jYZUOeHcV80flpg4qVGD8ilvSpC2GGx460pDsFQBt6QFD94CR+0a0xLQzvAE8zr4xAZjU4uaeXB/7/qZp9X4UBDVOnxPlcY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: eg2b4tUjSWWG7j04KZB/xw== X-CSE-MsgGUID: 3qS42FIeRxSgFNSqvgD5pA== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754429" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:55 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 9B0424005E06; Tue, 3 Dec 2024 19:50:47 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 11/13] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Date: Tue, 3 Dec 2024 10:49:38 +0000 Message-ID: <20241203105005.103927-12-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial support for the RZ/G3E SMARC SoM with 4GB memory, audio_extal, qextal and rtxin clks. Signed-off-by: Biju Das --- v1->v2: * No change. --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi new file mode 100644 index 000000000000..c8cf61545a5f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R9A09G047E57 SMARC SoM board. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/ { + compatible = "renesas,rzg3e-smarc", "renesas,r9a09g047e57", "renesas,r9a09g047"; + + memory@48000000 { + device_type = "memory"; + /* First 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0xf8000000>; + }; +}; + +&audio_extal_clk { + clock-frequency = <48000000>; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&rtxin_clk { + clock-frequency = <32768>; +}; From patchwork Tue Dec 3 10:49:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 13892121 X-Patchwork-Delegate: geert@linux-m68k.org Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2D2141E25EE; Tue, 3 Dec 2024 10:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223059; cv=none; b=WnpL1rGqBVPGgrWIO3vTaLwJeenyp57kJFMR6QVzkEbYSzKEX5ia+SrEUfdfCIN6jvUIzAUUslevjNaMOXBAdSSyrV0jzQezdyiCbSMi7zbVAR52YMs7mXq9qcYzvsXQBKJ0fN+aHgTXDF3MvI9DzUZV/GTRmBX2e9bBhC2Gmp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733223059; c=relaxed/simple; bh=5aJZWQLjQySciuqeTRJaWpCd00N91lfD1GyA0/Tmxxg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FzdbN1yg3AZl6L4nYTSeNEgH2eec6KDvsj+28WW+JC+VzBOGla+8LU5TPe11VxktdGgMWAENTYNG+89m5SlCuKqGH9sW35rxbPp4EP/0mM5NGRzTtpPKwyu1LmXlyYSmhgblzr8ovBVhzv+54E6wn4IBLTMGaK0SeGRHWzpealY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: 1QC8HeuNTl2sooijPKcPQw== X-CSE-MsgGUID: Kp7I2tsyTgScQWgut/ZCLw== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="230754431" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 03 Dec 2024 19:50:55 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 10168400753A; Tue, 3 Dec 2024 19:50:50 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v2 12/13] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Date: Tue, 3 Dec 2024 10:49:39 +0000 Message-ID: <20241203105005.103927-13-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the initial device tree for the Renesas RZ/G3E SMARC EVK board. Signed-off-by: Biju Das --- v1->v2: * No change. --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a09g047e57-smarc.dts | 18 ++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 24 +++++++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 97228a3cb99c..bf5b49f47ce8 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -140,6 +140,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb +dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb + dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts new file mode 100644 index 000000000000..d4d61bd03969 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3E SMARC EVK board + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g047e57.dtsi" +#include "rzg3e-smarc-som.dtsi" +#include "renesas-smarc2.dtsi" + +/ { + model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; + compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", + "renesas,r9a09g047e57", "renesas,r9a09g047"; +}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi new file mode 100644 index 000000000000..e378d55e6e9b --- /dev/null +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ SMARC Carrier-II Board. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/ { + model = "Renesas RZ SMARC Carrier-II Board"; + compatible = "renesas,smarc2-evk"; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial3:115200n8"; + }; + + aliases { + serial3 = &scif0; + }; +}; + +&scif0 { + status = "okay"; +}; From patchwork Tue Dec 3 10:49:40 2024 Content-Type: text/plain; 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smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com; spf=pass smtp.mailfrom=bp.renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=bp.renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bp.renesas.com X-CSE-ConnectionGUID: dnEh4QHzS/G6FrHe7XWF3g== X-CSE-MsgGUID: vrghDf0tTNeQ1BHutAf9/w== X-IronPort-AV: E=Sophos;i="6.12,204,1728918000"; d="scan'208";a="226779526" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 03 Dec 2024 19:51:07 +0900 Received: from localhost.localdomain (unknown [10.226.93.2]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 773DE40031FE; Tue, 3 Dec 2024 19:50:54 +0900 (JST) From: Biju Das To: Catalin Marinas , Will Deacon Cc: Biju Das , Bjorn Andersson , Geert Uytterhoeven , Krzysztof Kozlowski , Dmitry Baryshkov , Konrad Dybcio , Neil Armstrong , Arnd Bergmann , =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , linux-arm-kernel@lists.infradead.org, Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 13/13] arm64: defconfig: Enable R9A09G047 SoC Date: Tue, 3 Dec 2024 10:49:40 +0000 Message-ID: <20241203105005.103927-14-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> References: <20241203105005.103927-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable support for the Renesas RZ/G3E (R9A09G047) SoC in the ARM64 defconfig. Signed-off-by: Biju Das --- v1->v2: * No change. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d13218d0c30f..a14d48444bd8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1458,6 +1458,7 @@ CONFIG_ARCH_R9A07G044=y CONFIG_ARCH_R9A07G054=y CONFIG_ARCH_R9A08G045=y CONFIG_ARCH_R9A09G011=y +CONFIG_ARCH_R9A09G047=y CONFIG_ARCH_R9A09G057=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_ARCH_TEGRA_132_SOC=y