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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:03 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 01/10] iio: accel: adxl345: fix comment on probe Date: Tue, 3 Dec 2024 20:52:32 +0000 Message-Id: <20241203205241.48077-2-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Fix comment on the probe function. Add covered sensors and fix typo. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index b1efab0f640..cf73d7052e9 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -169,8 +169,7 @@ static void adxl345_powerdown(void *regmap) } /** - * adxl345_core_probe() - probe and setup for the adxl345 accelerometer, - * also covers the adlx375 accelerometer + * adxl345_core_probe() - Probe and setup for the accelerometer. * @dev: Driver model representation of the device * @regmap: Regmap instance for the device * @setup: Setup routine to be executed right before the standard device From patchwork Tue Dec 3 20:52:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13892958 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39CD5207A3B; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:05 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 02/10] iio: accel: adxl345: rename variable data to st Date: Tue, 3 Dec 2024 20:52:33 +0000 Message-Id: <20241203205241.48077-3-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename the locally used variable data to st. The st refers to "state", representing the internal state of the driver object. Further it prepares the usage of an internal data pointer needed for the implementation of the sensor features. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 44 ++++++++++++++++---------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index cf73d7052e9..0b613f5652e 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -17,7 +17,7 @@ #include "adxl345.h" -struct adxl345_data { +struct adxl345_state { const struct adxl345_chip_info *info; struct regmap *regmap; }; @@ -43,7 +43,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { - struct adxl345_data *data = iio_priv(indio_dev); + struct adxl345_state *st = iio_priv(indio_dev); __le16 accel; long long samp_freq_nhz; unsigned int regval; @@ -56,7 +56,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte */ - ret = regmap_bulk_read(data->regmap, + ret = regmap_bulk_read(st->regmap, ADXL345_REG_DATA_AXIS(chan->address), &accel, sizeof(accel)); if (ret < 0) @@ -66,10 +66,10 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val = 0; - *val2 = data->info->uscale; + *val2 = st->info->uscale; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_CALIBBIAS: - ret = regmap_read(data->regmap, + ret = regmap_read(st->regmap, ADXL345_REG_OFS_AXIS(chan->address), ®val); if (ret < 0) return ret; @@ -81,7 +81,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; case IIO_CHAN_INFO_SAMP_FREQ: - ret = regmap_read(data->regmap, ADXL345_REG_BW_RATE, ®val); + ret = regmap_read(st->regmap, ADXL345_REG_BW_RATE, ®val); if (ret < 0) return ret; @@ -99,7 +99,7 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { - struct adxl345_data *data = iio_priv(indio_dev); + struct adxl345_state *st = iio_priv(indio_dev); s64 n; switch (mask) { @@ -108,14 +108,14 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, * 8-bit resolution at +/- 2g, that is 4x accel data scale * factor */ - return regmap_write(data->regmap, + return regmap_write(st->regmap, ADXL345_REG_OFS_AXIS(chan->address), val / 4); case IIO_CHAN_INFO_SAMP_FREQ: n = div_s64(val * NANOHZ_PER_HZ + val2, ADXL345_BASE_RATE_NANO_HZ); - return regmap_update_bits(data->regmap, ADXL345_REG_BW_RATE, + return regmap_update_bits(st->regmap, ADXL345_REG_BW_RATE, ADXL345_BW_RATE, clamp_val(ilog2(n), 0, ADXL345_BW_RATE)); @@ -180,7 +180,7 @@ static void adxl345_powerdown(void *regmap) int adxl345_core_probe(struct device *dev, struct regmap *regmap, int (*setup)(struct device*, struct regmap*)) { - struct adxl345_data *data; + struct adxl345_state *st; struct iio_dev *indio_dev; u32 regval; unsigned int data_format_mask = (ADXL345_DATA_FORMAT_RANGE | @@ -189,17 +189,17 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, ADXL345_DATA_FORMAT_SELF_TEST); int ret; - indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); if (!indio_dev) return -ENOMEM; - data = iio_priv(indio_dev); - data->regmap = regmap; - data->info = device_get_match_data(dev); - if (!data->info) + st = iio_priv(indio_dev); + st->regmap = regmap; + st->info = device_get_match_data(dev); + if (!st->info) return -ENODEV; - indio_dev->name = data->info->name; + indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = adxl345_channels; @@ -207,12 +207,12 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, if (setup) { /* Perform optional initial bus specific configuration */ - ret = setup(dev, data->regmap); + ret = setup(dev, st->regmap); if (ret) return ret; /* Enable full-resolution mode */ - ret = regmap_update_bits(data->regmap, ADXL345_REG_DATA_FORMAT, + ret = regmap_update_bits(st->regmap, ADXL345_REG_DATA_FORMAT, data_format_mask, ADXL345_DATA_FORMAT_FULL_RES); if (ret) @@ -221,14 +221,14 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, } else { /* Enable full-resolution mode (init all data_format bits) */ - ret = regmap_write(data->regmap, ADXL345_REG_DATA_FORMAT, + ret = regmap_write(st->regmap, ADXL345_REG_DATA_FORMAT, ADXL345_DATA_FORMAT_FULL_RES); if (ret) return dev_err_probe(dev, ret, "Failed to set data range\n"); } - ret = regmap_read(data->regmap, ADXL345_REG_DEVID, ®val); + ret = regmap_read(st->regmap, ADXL345_REG_DEVID, ®val); if (ret < 0) return dev_err_probe(dev, ret, "Error reading device ID\n"); @@ -237,11 +237,11 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, regval, ADXL345_DEVID); /* Enable measurement mode */ - ret = adxl345_powerup(data->regmap); + ret = adxl345_powerup(st->regmap); if (ret < 0) return dev_err_probe(dev, ret, "Failed to enable measurement mode\n"); - ret = devm_add_action_or_reset(dev, adxl345_powerdown, data->regmap); + ret = devm_add_action_or_reset(dev, adxl345_powerdown, st->regmap); if (ret < 0) return ret; From patchwork Tue Dec 3 20:52:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13892959 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EF5220A5CA; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:07 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 03/10] iio: accel: adxl345: measure right-justified Date: Tue, 3 Dec 2024 20:52:34 +0000 Message-Id: <20241203205241.48077-4-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make measurements right-justified, since it is the default for the driver and sensor. By not setting the ADXL345_DATA_FORMAT_JUSTIFY bit, the data becomes right-judstified. This was the original setting, there is no reason to change it to left-justified, where right-justified simplifies working on the registers. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 0b613f5652e..11eb0ceef39 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -184,7 +184,6 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, struct iio_dev *indio_dev; u32 regval; unsigned int data_format_mask = (ADXL345_DATA_FORMAT_RANGE | - ADXL345_DATA_FORMAT_JUSTIFY | ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); int ret; From patchwork Tue Dec 3 20:52:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13892960 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 780B4207A1F; Tue, 3 Dec 2024 20:53:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733259193; cv=none; b=QKXh8sfYVOaHBadFykNz7WBQZBm28l2d7eItf2Npzp8M28KEZtfqcWD34Fot0VxoHAXvUhN2jlmP+bS4i+uuiHuEVQ8YuMLvFRgcEIw2+fwtnc52MdUhNYRt+vYt5ItjBHmt3YKO93SgRBx1K+Tn4p/wrHJdMeR+X/qdAXauGgQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733259193; c=relaxed/simple; bh=o/lpI9Fd+uyjmqbC3M5WpJqu5Nkn3HEhk7znZmdrG90=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mj65jkO/tJpNINOknxASBqDb3p2so8AXV3tGYpcSCIpCdVyRnEXYLSJR85avzZdIzJ58q2yZHmUZSWoZstUU5yjphQUASumi5EUhrsmuhJ5y+6M6J1EdbRzSuRRwKAqbPsxNtX+QolW9K/iXdj5M1YoCVwabhueX77SqFz2KBaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Ya8N23bL; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Ya8N23bL" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4348f65e373so7054315e9.2; Tue, 03 Dec 2024 12:53:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733259190; x=1733863990; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P0SeLMeajdOsD9tUkvbsJQTKmVK5v3TGj4Il/E1cJl0=; b=Ya8N23bL+hjzkJiRmRZQGemyDU0MJc9C2sdojBN1LPgRjVw/d894cig9KC1IJWK942 F6SLRCrJhSAhXlSB+Gc8nYsnCiWIvEB4i1zYa821BSS2LMMx5VXZ2V1RpHtGhkNM74R7 aLJz5l3lWgrshm6ZAOFqDoQx3YXpPmaRH55/rV3vR0qbWJImaLCWqxP35a8VghJg32NX y0r70Kf3ztR0n95qaDEQmF5TgESXtNiAzaQ7yPQCa+Wm/rDJpKJJgydXfj1VQVIYYlCN b+Mk9/hktMUZOXNzgyb+PWcJiufe8i1VOM0PkItzjrj+rbnwpiKEBnRjjnUESglycP/d FvYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733259190; x=1733863990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P0SeLMeajdOsD9tUkvbsJQTKmVK5v3TGj4Il/E1cJl0=; b=K865vB3lac1SuFpQfpUNKNsnUeg6AjMlO0VzYZQlHWNjnl9bNXdAItCTEEhkuW4aEe F8gKpNsnxEEGDcOnsh9HfdBYNBb9aupeexYCu9j8EenTettmUSaom+cxbWfCqIws/Ae8 pV9RYt5XLt8lAVgGgzKR88puVyPywb2xCg/jFgroAfFpdYyFIxvg+WG03ENScjZ733G3 fH7+jeXJtsHF0QiHWJ4/yfqQP39SGz2GQ0q4oCIjvY6y8Aqmfy2oDvnJfEJB/y+M5XKg wYvmbCdlUEZfyWjfBoksNll2dq9pp5Bj/aQkkruTJFOt9MioTDKqlR6DQztL+8/B6hjY G7tA== X-Forwarded-Encrypted: i=1; AJvYcCV/xvYoJ9g7a1uAOlgTloIredzNgbLnQA+/NSg2QKnorzTmeWVJie5NcNOrgEHw8oESuBkXQ3aGANg=@vger.kernel.org, AJvYcCWCI/43OQxwuX5ynpv4JV1Qll9PZlL/7ZQWeNjdA5xd1bGrVJRtXylH5rRGoTcVF0dtmqtOzHeyisV1RWE/@vger.kernel.org X-Gm-Message-State: AOJu0Yy2ttrbbQfQJEwKuf0xvithTbvp3vJcldeVe2wINGn9gioc5SCC znZiiMEUOUde5YoobmzWx+CEBOCJrN204EE4yw8bNQVCNTaXzHb3ECCeyw== X-Gm-Gg: ASbGnctPDyOkPMWdWByWSuLOYKlcfyzIlSA0aWMcv5/qLpA/+nSOEc6kpnpFeg8N7Eh KXD6IQBu/A3hz8QOSzSoewCYYVHnslVOgKK+d/VI3JqUsJlWshXXADRTdK+Z/kp/C8mMCpC4vGa rJe6HIBtvey+10ERPdgcLTvfBGdwm45girUTHOj2PsHld8G8AHEtQXoh5X68VDS2bfPKVyqj1ZK esj+Ld1EHMj7JxuZs1iy7Hf5z70LC4bqZHvFOJX0PMUO8vnyyaOZu5b0jMND058/9iR2TNREEti CzCdD5zJpfaedPhVVaD0KtI+6hSc X-Google-Smtp-Source: AGHT+IGD6ZPOpR8AqIvu2pWgIl8eW2InmZPbtk93t30ynomOzynLmktqEl1UxTwRpizJhTJWWvrK2A== X-Received: by 2002:a05:600c:1c02:b0:431:4a7e:a121 with SMTP id 5b1f17b1804b1-434d0a38d88mr14284985e9.9.1733259189703; Tue, 03 Dec 2024 12:53:09 -0800 (PST) Received: from 7b58d44c4ff6.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:09 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 04/10] iio: accel: adxl345: add function to switch measuring Date: Tue, 3 Dec 2024 20:52:35 +0000 Message-Id: <20241203205241.48077-5-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Replace the powerup / powerdown functions by a generic function to put the sensor in STANDBY, or MEASURE mode. This is needed for several features of the accelerometer. It allows to change e.g. FIFO settings. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 44 ++++++++++++++++++++++---------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 11eb0ceef39..0bb2c653e13 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -138,6 +138,34 @@ static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, } } +/** + * adxl345_set_measure_en() - Enable and disable measuring. + * + * @st: The device data. + * @en: Enable measurements, else standby mode. + * + * For lowest power operation, standby mode can be used. In standby mode, + * current consumption is supposed to be reduced to 0.1uA (typical). In this + * mode no measurements are made. Placing the device into standby mode + * preserves the contents of FIFO. + * + * Return: Returns 0 if successful, or a negative error value. + */ +static int adxl345_set_measure_en(struct adxl345_state *st, bool en) +{ + unsigned int val = 0; + + val = (en) ? ADXL345_POWER_CTL_MEASURE : ADXL345_POWER_CTL_STANDBY; + return regmap_write(st->regmap, ADXL345_REG_POWER_CTL, val); +} + +static void adxl345_powerdown(void *ptr) +{ + struct adxl345_state *st = ptr; + + adxl345_set_measure_en(st, false); +} + static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200" ); @@ -158,16 +186,6 @@ static const struct iio_info adxl345_info = { .write_raw_get_fmt = adxl345_write_raw_get_fmt, }; -static int adxl345_powerup(void *regmap) -{ - return regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_MEASURE); -} - -static void adxl345_powerdown(void *regmap) -{ - regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_STANDBY); -} - /** * adxl345_core_probe() - Probe and setup for the accelerometer. * @dev: Driver model representation of the device @@ -236,13 +254,13 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, regval, ADXL345_DEVID); /* Enable measurement mode */ - ret = adxl345_powerup(st->regmap); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:10 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 05/10] iio: accel: adxl345: extend list of defines Date: Tue, 3 Dec 2024 20:52:36 +0000 Message-Id: <20241203205241.48077-6-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Extend the list of constants. Keep them the header file for readability. The constants allow the implementation of events like FIFO-watermark, single tap, double tap, freefall, etc. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 89 ++++++++++++++++++++++++++++++++----- 1 file changed, 77 insertions(+), 12 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index 3d5c8719db3..ed81d5cf445 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -9,37 +9,102 @@ #define _ADXL345_H_ #define ADXL345_REG_DEVID 0x00 +#define ADXL345_REG_THRESH_TAP 0x1D #define ADXL345_REG_OFSX 0x1E #define ADXL345_REG_OFSY 0x1F #define ADXL345_REG_OFSZ 0x20 -#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) +/* Tap duration */ +#define ADXL345_REG_DUR 0x21 +/* Tap latency */ +#define ADXL345_REG_LATENT 0x22 +/* Tap window */ +#define ADXL345_REG_WINDOW 0x23 +/* Activity threshold */ +#define ADXL345_REG_THRESH_ACT 0x24 +/* Inactivity threshold */ +#define ADXL345_REG_THRESH_INACT 0x25 +/* Inactivity time */ +#define ADXL345_REG_TIME_INACT 0x26 +/* Axis enable control for activity and inactivity detection */ +#define ADXL345_REG_ACT_INACT_CTRL 0x27 +/* Free-fall threshold */ +#define ADXL345_REG_THRESH_FF 0x28 +/* Free-fall time */ +#define ADXL345_REG_TIME_FF 0x29 +/* Axis control for single tap or double tap */ +#define ADXL345_REG_TAP_AXIS 0x2A +/* Source of single tap or double tap */ +#define ADXL345_REG_ACT_TAP_STATUS 0x2B +/* Data rate and power mode control */ #define ADXL345_REG_BW_RATE 0x2C #define ADXL345_REG_POWER_CTL 0x2D +#define ADXL345_REG_INT_ENABLE 0x2E +#define ADXL345_REG_INT_MAP 0x2F +#define ADXL345_REG_INT_SOURCE 0x30 #define ADXL345_REG_DATA_FORMAT 0x31 -#define ADXL345_REG_DATAX0 0x32 -#define ADXL345_REG_DATAY0 0x34 -#define ADXL345_REG_DATAZ0 0x36 -#define ADXL345_REG_DATA_AXIS(index) \ - (ADXL345_REG_DATAX0 + (index) * sizeof(__le16)) +#define ADXL345_REG_XYZ_BASE 0x32 +#define ADXL345_REG_DATA_AXIS(index) \ + (ADXL345_REG_XYZ_BASE + (index) * sizeof(__le16)) + +#define ADXL345_REG_FIFO_CTL 0x38 +#define ADXL345_REG_FIFO_STATUS 0x39 + +#define ADXL345_DEVID 0xE5 + +#define ADXL345_FIFO_CTL_SAMLPES(x) (0x1f & (x)) +#define ADXL345_FIFO_CTL_TRIGGER(x) (0x20 & ((x) << 5)) /* 0: INT1, 1: INT2 */ +#define ADXL345_FIFO_CTL_MODE(x) (0xc0 & ((x) << 6)) +#define ADXL345_INT_DATA_READY BIT(7) +#define ADXL345_INT_SINGLE_TAP BIT(6) +#define ADXL345_INT_DOUBLE_TAP BIT(5) +#define ADXL345_INT_ACTIVITY BIT(4) +#define ADXL345_INT_INACTIVITY BIT(3) +#define ADXL345_INT_FREE_FALL BIT(2) +#define ADXL345_INT_WATERMARK BIT(1) +#define ADXL345_INT_OVERRUN BIT(0) + +#define ADXL345_S_TAP_MSK ADXL345_INT_SINGLE_TAP +#define ADXL345_D_TAP_MSK ADXL345_INT_DOUBLE_TAP + +#define ADXL345_INT1 0 +#define ADXL345_INT2 1 + +/* + * BW_RATE bits - Bandwidth and output data rate. The default value is + * 0x0A, which translates to a 100 Hz output data rate + */ #define ADXL345_BW_RATE GENMASK(3, 0) +#define ADXL345_BW_LOW_POWER BIT(4) #define ADXL345_BASE_RATE_NANO_HZ 97656250LL -#define ADXL345_POWER_CTL_MEASURE BIT(3) #define ADXL345_POWER_CTL_STANDBY 0x00 +#define ADXL345_POWER_CTL_WAKEUP GENMASK(1, 0) +#define ADXL345_POWER_CTL_SLEEP BIT(2) +#define ADXL345_POWER_CTL_MEASURE BIT(3) +#define ADXL345_POWER_CTL_AUTO_SLEEP BIT(4) +#define ADXL345_POWER_CTL_LINK BIT(5) #define ADXL345_DATA_FORMAT_RANGE GENMASK(1, 0) /* Set the g range */ -#define ADXL345_DATA_FORMAT_JUSTIFY BIT(2) /* Left-justified (MSB) mode */ +#define ADXL345_DATA_FORMAT_IS_LEFT_JUSTIFIED BIT(2) #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */ -#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) /* 3-wire SPI mode */ -#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) /* Enable a self test */ - +#define ADXL345_DATA_FORMAT_SPI_3WIRE BIT(6) +#define ADXL345_DATA_FORMAT_SELF_TEST BIT(7) #define ADXL345_DATA_FORMAT_2G 0 #define ADXL345_DATA_FORMAT_4G 1 #define ADXL345_DATA_FORMAT_8G 2 #define ADXL345_DATA_FORMAT_16G 3 -#define ADXL345_DEVID 0xE5 +#define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index)) + +/* + * FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries + * available at any given time because an additional entry is available at the + * output filter of the device. + * + * (see datasheet FIFO_STATUS description on "Entries Bits") + */ +#define ADXL345_FIFO_SIZE 33 /* * In full-resolution mode, scale factor is maintained at ~4 mg/LSB From patchwork Tue Dec 3 20:52:37 2024 Content-Type: text/plain; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:12 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 06/10] dt-bindings: iio: accel: add interrupt-names Date: Tue, 3 Dec 2024 20:52:37 +0000 Message-Id: <20241203205241.48077-7-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add interrupt-names INT1 and INT2 for the two interrupt lines of the sensor. Only one line will be connected for incoming events. The driver needs to be configured accordingly. If no interrupt line is set up, the sensor will still measure, but no events are possible. Signed-off-by: Lothar Rubusch --- .../devicetree/bindings/iio/accel/adi,adxl345.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml index 280ed479ef5..c3483a4b652 100644 --- a/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml +++ b/Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml @@ -37,6 +37,17 @@ properties: interrupts: maxItems: 1 + interrupt-names: + Data ready is only available on INT1, but events can use either or + both pins. If not specified, first element assumed to correspond + to INT1 and second (where present) to INT2. + minItems: 1 + maxItems: 2 + items: + enum: + - INT1 + - INT2 + required: - compatible - reg @@ -61,6 +72,7 @@ examples: reg = <0x2a>; interrupt-parent = <&gpio0>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; }; }; - | @@ -79,5 +91,6 @@ examples: spi-cpha; interrupt-parent = <&gpio0>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT2"; }; }; From patchwork Tue Dec 3 20:52:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lothar Rubusch X-Patchwork-Id: 13892963 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B95820B211; Tue, 3 Dec 2024 20:53:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733259198; cv=none; b=K8+Be71Ya+9G/ANTwIDy2/JTMrVwOMmrwMMhuYncI0uUUgXDIimF9b7R18DEMXHolVqI4wvx7Mq5s499uqpk5QcSNmUdVwQWJOuw+O7XbwpyehqrPjal8FYlz6MbsO0JbbmT5pyL3Wpi+SIB4qk29vwH2bc9jArqSNbCRyXB+ac= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733259198; c=relaxed/simple; bh=FY91FECIG8vyXTtfxzalXSXZ249nSTm+wGDBjFYvNpU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=i+KGl03Cju4D1EnG0nJEbCC8uKuxwxXqgZSChyrzScxJiFrTqREAxkNgHAE48IJnECbq0M5fWFYDQ1vsZVBReCREEWQN6PPHedJ/dmlm9wKaqqSWILTb6is9IVn3A8Pc5kUXnI65mLwohsWOy05Rbozzbybsr6aemlzXYggG4i0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ChGkL5oK; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ChGkL5oK" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-434a29ecbceso7078605e9.0; Tue, 03 Dec 2024 12:53:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1733259194; x=1733863994; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yA7vOziRlmc/bZx4fMvI0r+Cuk3SCmX4PpXxbI8VPks=; b=ChGkL5oKYMG4OGy9tnFfWEKYdX4NhGnSNGcgZkNZiTWewNUHHL62btl3Jch5OSbsC8 egFdjkJ3F/NCkn44qD9vXebn3x8CCwad2NZMjNzwHeGEpK8Aj0J8BkR0tLgGNeOYdsK2 3x8Fme6O3bxCBSfBY5GR5cF8bGjNqkUhCXlDPfL6F5FKOQvVs02PADhyBY7bkUvbPLge DKizbwFL+CrEqPrv0TNrWvOpvx46u6O6UgXLX6VxCbHWgl3cFYF+6ghejfXbrj+MhbXZ A8x6+WN5zj/QxFp3zKNtFh7w37qMI2Y+JmejbNSaXqyAH5Wuh2hKtzytogOav731/PTB diBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733259194; x=1733863994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yA7vOziRlmc/bZx4fMvI0r+Cuk3SCmX4PpXxbI8VPks=; b=CnuYDsFThDhlfVgQD+l/xnFglGdo9mtPG5Fy+PvgbV3hML9FqTOwO4v8sF3ojbQcfj 3oUA3psShPC3n4Yb46JJKtIIuStG8QIPlDkejjogwVbjr0d/Z3Ra6neKCvRqNgD/Uty3 cXKAPQL4OMN6DwD5/P/0JLqTZeiA3PfiEEj6iPy4l2nb1xJrCm04SBn7mDUG4JlJIoWw B5RpRSOWZGmxqT0A+agEFxyU1TM5hWL3jOba9zdEGYcIRQr9L+62CHo4Q4A0R6QZusO5 4runpQDdu8Ji3QrDWB7ZDa+tTcPWfvPy7ctyhPYlsKHR5VwZ+uVsggmdy3TRU1qOUTrk pRMg== X-Forwarded-Encrypted: i=1; AJvYcCUbbYyem3zidzD2o7ygaho3Mpqn/Vrq0RPL22KlRKu0UDjVgXfDpQURZdPgknqfeUISLOvFX9fYGnQrUCqJ@vger.kernel.org, AJvYcCWE2jcwnp/0AkvUeWMKDaZjGF28qWM7H+et2ztuA3sMlHjNQI9NuMGPLfNT6/U5DB2alw6C9WHBJLs=@vger.kernel.org X-Gm-Message-State: AOJu0Ywk02RA3A4C0n0qttr5S3wbAzwiNzCzkE3EeuT4w8OU8OigXch7 fSxCaymtjC5A9mExDxOYP9ZagcDtAJ0zRv1JFfx/TVw936mN/jwg X-Gm-Gg: ASbGncslLvzVoxJDHfb7Cg2veVR1LEl8Jt4rPEp1E06rPkqs3oo8tFTK3bQ3SwbzVVN b3DRTzsTjdoVmAQXzvWdwgWwat+dfh8cJW7TTkcxji3uatVGd3k+h9byJ7HmkIwOqurk4BzVKJX kAd3iOhRFh9kXgemiwtCEHl/4P6lZQT/kN8w7jXFD7eGxI16xEIjC6TjtEKPMqtZAnlgYEfXZ0b 7NV7u19kRUesS5nLqSiTZ15aA+aRc90TCZVpXodgErN5s3TI3nEQKjmhJm46OVm5L7xpnajPuVS AjGHpSlkktIypwMSZmOIeyq2tF+x X-Google-Smtp-Source: AGHT+IF8CuGWZEBktezY5BS7YphnMd2zJ/kIWieEl2c7J3moHhstF2htiyuWmP6rtnP+sHe/iTdE6Q== X-Received: by 2002:a05:6000:4011:b0:382:4e71:1a12 with SMTP id ffacd0b85a97d-385fd3c30aamr1439178f8f.1.1733259194422; Tue, 03 Dec 2024 12:53:14 -0800 (PST) Received: from 7b58d44c4ff6.v.cablecom.net (84-72-156-211.dclient.hispeed.ch. [84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:14 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 07/10] iio: accel: adxl345: initialize IRQ number Date: Tue, 3 Dec 2024 20:52:38 +0000 Message-Id: <20241203205241.48077-8-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the possibility to claim an interrupt and init the state structure with interrupt number and interrupt line to use. The adxl345 can use two different interrupt lines, mainly to signal FIFO watermark events, single or double tap, activity, etc. Hence, having the interrupt line available is crucial to implement such features. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 0bb2c653e13..dc91b2dcd62 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -18,8 +19,10 @@ #include "adxl345.h" struct adxl345_state { + int irq; const struct adxl345_chip_info *info; struct regmap *regmap; + u8 intio; }; #define ADXL345_CHANNEL(index, axis) { \ @@ -212,6 +215,17 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, st = iio_priv(indio_dev); st->regmap = regmap; + + st->intio = -1; + st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT1"); + if (st->irq > 0) + st->intio = ADXL345_INT1; + else { + st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "INT2"); + if (st->irq > 0) + st->intio = ADXL345_INT2; + } + st->info = device_get_match_data(dev); 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:16 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 08/10] iio: accel: adxl345: initialize FIFO delay value for SPI Date: Tue, 3 Dec 2024 20:52:39 +0000 Message-Id: <20241203205241.48077-9-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the possibility to delay FIFO access when SPI is used. According to the datasheet this is needed for the adxl345. When initialization happens over SPI the need for delay is to be signalized, and the delay will be used. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345.h | 1 + drivers/iio/accel/adxl345_core.c | 12 ++++++++++++ drivers/iio/accel/adxl345_i2c.c | 2 +- drivers/iio/accel/adxl345_spi.c | 7 +++++-- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/iio/accel/adxl345.h b/drivers/iio/accel/adxl345.h index ed81d5cf445..c07709350d3 100644 --- a/drivers/iio/accel/adxl345.h +++ b/drivers/iio/accel/adxl345.h @@ -127,6 +127,7 @@ struct adxl345_chip_info { }; int adxl345_core_probe(struct device *dev, struct regmap *regmap, + bool fifo_delay_default, int (*setup)(struct device*, struct regmap*)); #endif /* _ADXL345_H_ */ diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index dc91b2dcd62..636b8ec48db 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -22,6 +22,7 @@ struct adxl345_state { int irq; const struct adxl345_chip_info *info; struct regmap *regmap; + bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; }; @@ -193,12 +194,21 @@ static const struct iio_info adxl345_info = { * adxl345_core_probe() - Probe and setup for the accelerometer. * @dev: Driver model representation of the device * @regmap: Regmap instance for the device + * @fifo_delay_default: Using FIFO with SPI needs delay * @setup: Setup routine to be executed right before the standard device * setup * + * For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS + * pin to ensure a total delay of 5 us; otherwise, the delay is not sufficient. + * The total delay necessary for 5 MHz operation is at most 3.4 us. This is not + * a concern when using I2C mode because the communication rate is low enough + * to ensure a sufficient delay between FIFO reads. + * Ref: "Retrieving Data from FIFO", p. 21 of 36, Data Sheet ADXL345 Rev. G + * * Return: 0 on success, negative errno on error */ int adxl345_core_probe(struct device *dev, struct regmap *regmap, + bool fifo_delay_default, int (*setup)(struct device*, struct regmap*)) { struct adxl345_state *st; @@ -230,6 +240,8 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, if (!st->info) return -ENODEV; + st->fifo_delay = fifo_delay_default; + indio_dev->name = st->info->name; indio_dev->info = &adxl345_info; indio_dev->modes = INDIO_DIRECT_MODE; diff --git a/drivers/iio/accel/adxl345_i2c.c b/drivers/iio/accel/adxl345_i2c.c index cb23fb11fcd..8c385dd6c01 100644 --- a/drivers/iio/accel/adxl345_i2c.c +++ b/drivers/iio/accel/adxl345_i2c.c @@ -27,7 +27,7 @@ static int adxl345_i2c_probe(struct i2c_client *client) if (IS_ERR(regmap)) return dev_err_probe(&client->dev, PTR_ERR(regmap), "Error initializing regmap\n"); - return adxl345_core_probe(&client->dev, regmap, NULL); + return adxl345_core_probe(&client->dev, regmap, false, NULL); } static const struct adxl345_chip_info adxl345_i2c_info = { diff --git a/drivers/iio/accel/adxl345_spi.c b/drivers/iio/accel/adxl345_spi.c index 015b334e5b0..ec1773e7ff1 100644 --- a/drivers/iio/accel/adxl345_spi.c +++ b/drivers/iio/accel/adxl345_spi.c @@ -12,6 +12,7 @@ #include "adxl345.h" #define ADXL345_MAX_SPI_FREQ_HZ 5000000 +#define ADXL345_MAX_FREQ_NO_FIFO_DELAY 1500000 static const struct regmap_config adxl345_spi_regmap_config = { .reg_bits = 8, @@ -28,6 +29,7 @@ static int adxl345_spi_setup(struct device *dev, struct regmap *regmap) static int adxl345_spi_probe(struct spi_device *spi) { struct regmap *regmap; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:17 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 09/10] iio: accel: adxl345: prepare channel for scan_index Date: Tue, 3 Dec 2024 20:52:40 +0000 Message-Id: <20241203205241.48077-10-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add separate fields for register and index to the channel definition. The scan_index is set up with the kfifo in the follow up patches. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 636b8ec48db..0a3acce2198 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -26,21 +26,26 @@ struct adxl345_state { u8 intio; }; -#define ADXL345_CHANNEL(index, axis) { \ +#define ADXL345_CHANNEL(index, reg, axis) { \ .type = IIO_ACCEL, \ .modified = 1, \ .channel2 = IIO_MOD_##axis, \ - .address = index, \ + .address = (reg), \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_CALIBBIAS), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = (index), \ } +enum adxl345_chans { + chan_x, chan_y, chan_z, +}; + static const struct iio_chan_spec adxl345_channels[] = { - ADXL345_CHANNEL(0, X), - ADXL345_CHANNEL(1, Y), - ADXL345_CHANNEL(2, Z), + ADXL345_CHANNEL(0, chan_x, X), + ADXL345_CHANNEL(1, chan_y, Y), + ADXL345_CHANNEL(2, chan_z, Z), }; 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[84.72.156.211]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ebaf3bccsm9042750f8f.68.2024.12.03.12.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Dec 2024 12:53:19 -0800 (PST) From: Lothar Rubusch To: lars@metafoo.de, Michael.Hennerich@analog.com, jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, eraretuya@gmail.com, l.rubusch@gmail.com Subject: [PATCH v3 10/10] iio: accel: adxl345: add kfifo with watermark Date: Tue, 3 Dec 2024 20:52:41 +0000 Message-Id: <20241203205241.48077-11-l.rubusch@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20241203205241.48077-1-l.rubusch@gmail.com> References: <20241203205241.48077-1-l.rubusch@gmail.com> Precedence: bulk X-Mailing-List: linux-iio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add a basic setup for kfifo with configurable watermark, add a handler for watermark interrupt events and extend the channel for the scan_index needed for the kfifo. The sensor is configurable to use a FIFO_BYPASSED mode or a FIFO_STREAM mode. For the FIFO_STREAM mode a watermark can be configured, or disabled by setting 0. Further features are based on the FIFO setup. Signed-off-by: Lothar Rubusch --- drivers/iio/accel/adxl345_core.c | 300 +++++++++++++++++++++++++++++++ 1 file changed, 300 insertions(+) diff --git a/drivers/iio/accel/adxl345_core.c b/drivers/iio/accel/adxl345_core.c index 0a3acce2198..8c20e1e39c3 100644 --- a/drivers/iio/accel/adxl345_core.c +++ b/drivers/iio/accel/adxl345_core.c @@ -15,15 +15,28 @@ #include #include +#include +#include +#include #include "adxl345.h" +#define ADXL345_FIFO_BYPASS 0 +#define ADXL345_FIFO_FIFO 1 +#define ADXL345_FIFO_STREAM 2 + +#define ADXL345_DIRS 3 + struct adxl345_state { int irq; const struct adxl345_chip_info *info; struct regmap *regmap; + __le16 fifo_buf[ADXL345_DIRS * ADXL345_FIFO_SIZE]; bool fifo_delay; /* delay: delay is needed for SPI */ u8 intio; + u8 int_map; + u8 watermark; + u8 fifo_mode; }; #define ADXL345_CHANNEL(index, reg, axis) { \ @@ -36,6 +49,13 @@ struct adxl345_state { .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_SAMP_FREQ), \ .scan_index = (index), \ + .scan_type = { \ + .sign = 's', \ + .realbits = 13, \ + .storagebits = 16, \ + .shift = 0, \ + .endianness = IIO_LE, \ + }, \ } enum adxl345_chans { @@ -48,6 +68,25 @@ static const struct iio_chan_spec adxl345_channels[] = { ADXL345_CHANNEL(2, chan_z, Z), }; +static int adxl345_set_interrupts(struct adxl345_state *st) +{ + int ret; + unsigned int int_enable = st->int_map; + unsigned int int_map; + + /* Any bits set to 0 in the INT map register send their respective + * interrupts to the INT1 pin, whereas bits set to 1 send their respective + * interrupts to the INT2 pin. The intio shall convert this accordingly. + */ + int_map = 0xFF & (st->intio ? st->int_map : ~st->int_map); + + ret = regmap_write(st->regmap, ADXL345_REG_INT_MAP, int_map); + if (ret) + return ret; + + return regmap_write(st->regmap, ADXL345_REG_INT_ENABLE, int_enable); +} + static int adxl345_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -133,6 +172,31 @@ static int adxl345_write_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int adxl345_set_watermark(struct iio_dev *indio_dev, unsigned int value) +{ + struct adxl345_state *st = iio_priv(indio_dev); + unsigned int fifo_mask = 0x1F; + int ret; + + if (value == 0) { + st->int_map &= ~ADXL345_INT_WATERMARK; + return 0; + } + + if (value > ADXL345_FIFO_SIZE) + value = ADXL345_FIFO_SIZE; + + ret = regmap_update_bits(st->regmap, ADXL345_REG_FIFO_CTL, + fifo_mask, value); + if (ret) + return ret; + + st->watermark = value; + st->int_map |= ADXL345_INT_WATERMARK; + + return 0; +} + static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, long mask) @@ -188,11 +252,224 @@ static const struct attribute_group adxl345_attrs_group = { .attrs = adxl345_attrs, }; +static int adxl345_set_fifo(struct adxl345_state *st) +{ + u8 fifo_ctl; + int ret; + + /* FIFO should only be configured while in standby mode */ + ret = adxl345_set_measure_en(st, false); + if (ret < 0) + return ret; + + fifo_ctl = ADXL345_FIFO_CTL_SAMLPES(st->watermark) | + ADXL345_FIFO_CTL_TRIGGER(st->intio) | + ADXL345_FIFO_CTL_MODE(st->fifo_mode); + + ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); + if (ret < 0) + return ret; + + return adxl345_set_measure_en(st, true); +} + +/** + * adxl345_get_samples() - Read number of FIFO entries. + * @st: The initialized state instance of this driver. + * + * The sensor does not support treating any axis individually, or exclude them + * from measuring. + * + * Return: negative error, or value. + */ +static int adxl345_get_samples(struct adxl345_state *st) +{ + unsigned int regval = 0; + int ret; + + ret = regmap_read(st->regmap, ADXL345_REG_FIFO_STATUS, ®val); + if (ret < 0) + return ret; + + return 0x3f & regval; +} + +/** + * adxl345_fifo_transfer() - Read samples number of elements. + * @st: The instance of the state object of this sensor. + * @samples: The number of lines in the FIFO referred to as fifo_entry, + * a fifo_entry has 3 elements for X, Y and Z direction of 2 bytes each. + * + * It is recommended that a multiple-byte read of all registers be performed to + * prevent a change in data between reads of sequential registers. That is to + * read out the data registers X0, X1, Y0, Y1, Z0, Z1 at once. + * + * Return: 0 or error value. + */ +static int adxl345_fifo_transfer(struct adxl345_state *st, int samples) +{ + size_t count; + int i, ret; + + count = sizeof(st->fifo_buf[0]) * ADXL345_DIRS; + for (i = 0; i < samples; i++) { + ret = regmap_noinc_read(st->regmap, ADXL345_REG_XYZ_BASE, + st->fifo_buf + (i * count / 2), count); + if (ret < 0) + return ret; + } + return ret; +} + +/** + * adxl345_fifo_reset() - Empty the FIFO in error condition. + * @st: The instance to the state object of the sensor. + * + * Read all elements of the FIFO. Reading the interrupt source register + * resets the sensor. + */ +static void adxl345_fifo_reset(struct adxl345_state *st) +{ + int regval; + int samples; + + adxl345_set_measure_en(st, false); + + samples = adxl345_get_samples(st); + if (samples > 0) + adxl345_fifo_transfer(st, samples); + + regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); + + adxl345_set_measure_en(st, true); +} + +static int adxl345_buffer_postenable(struct iio_dev *indio_dev) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int ret; + + ret = adxl345_set_interrupts(st); + if (ret < 0) + return ret; + + st->fifo_mode = ADXL345_FIFO_STREAM; + return adxl345_set_fifo(st); +} + +static int adxl345_buffer_predisable(struct iio_dev *indio_dev) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int ret; + + st->int_map = 0x00; + + ret = adxl345_set_interrupts(st); + if (ret < 0) + return ret; + + st->fifo_mode = ADXL345_FIFO_BYPASS; + return adxl345_set_fifo(st); +} + +static const struct iio_buffer_setup_ops adxl345_buffer_ops = { + .postenable = adxl345_buffer_postenable, + .predisable = adxl345_buffer_predisable, +}; + +static int adxl345_get_status(struct adxl345_state *st) +{ + int ret; + unsigned int regval; + + ret = regmap_read(st->regmap, ADXL345_REG_INT_SOURCE, ®val); + if (ret < 0) + return ret; + + return (0xff & regval); +} + +static int adxl345_fifo_push(struct iio_dev *indio_dev, + int samples) +{ + struct adxl345_state *st = iio_priv(indio_dev); + int i, ret; + + if (samples <= 0) + return -EINVAL; + + ret = adxl345_fifo_transfer(st, samples); + if (ret) + return ret; + + for (i = 0; i < ADXL345_DIRS * samples; i += ADXL345_DIRS) { + /* + * To ensure that the FIFO has completely popped, there must be at least 5 + * us between the end of reading the data registers, signified by the + * transition to register 0x38 from 0x37 or the CS pin going high, and the + * start of new reads of the FIFO or reading the FIFO_STATUS register. For + * SPI operation at 1.5 MHz or lower, the register addressing portion of the + * transmission is sufficient delay to ensure the FIFO has completely + * popped. It is necessary for SPI operation greater than 1.5 MHz to + * de-assert the CS pin to ensure a total of 5 us, which is at most 3.4 us + * at 5 MHz operation. + */ + if (st->fifo_delay && (samples > 1)) + udelay(3); + + iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); + } + + return 0; +} + +/** + * irqreturn_t adxl345_event_handler() - Handle events of the ADXL345. + * @irq: The irq being handled. + * @p: The struct iio_device pointer for the device. + * + * Return: The interrupt was handled. + */ +static irqreturn_t adxl345_event_handler(int irq, void *p) +{ + struct iio_dev *indio_dev = p; + struct adxl345_state *st = iio_priv(indio_dev); + u8 int_stat; + int samples; + + int_stat = adxl345_get_status(st); + if (int_stat < 0) + return IRQ_NONE; + + if (int_stat == 0x0) + goto err; + + if (int_stat & ADXL345_INT_OVERRUN) + goto err; + + if (int_stat & (ADXL345_INT_DATA_READY | ADXL345_INT_WATERMARK)) { + samples = adxl345_get_samples(st); + if (samples < 0) + goto err; + + if (adxl345_fifo_push(indio_dev, samples) < 0) + goto err; + + } + return IRQ_HANDLED; + +err: + adxl345_fifo_reset(st); + + return IRQ_HANDLED; +} + static const struct iio_info adxl345_info = { .attrs = &adxl345_attrs_group, .read_raw = adxl345_read_raw, .write_raw = adxl345_write_raw, .write_raw_get_fmt = adxl345_write_raw_get_fmt, + .hwfifo_set_watermark = adxl345_set_watermark, }; /** @@ -222,6 +499,7 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, unsigned int data_format_mask = (ADXL345_DATA_FORMAT_RANGE | ADXL345_DATA_FORMAT_FULL_RES | ADXL345_DATA_FORMAT_SELF_TEST); + u8 fifo_ctl; int ret; indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); @@ -293,6 +571,28 @@ int adxl345_core_probe(struct device *dev, struct regmap *regmap, if (ret < 0) return dev_err_probe(dev, ret, "Failed to add action or reset\n"); + if (st->irq > 0) { + dev_dbg(dev, "initialize for FIFO_STREAM mode\n"); + + ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, &adxl345_buffer_ops); + if (ret) + return ret; + + ret = devm_request_threaded_irq(dev, st->irq, NULL, &adxl345_event_handler, + IRQF_SHARED | IRQF_ONESHOT, + indio_dev->name, indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup triggered buffer\n"); + + } else { + dev_dbg(dev, "initialize for FIFO_BYPASS mode (fallback)\n"); + + fifo_ctl = ADXL345_FIFO_CTL_MODE(ADXL345_FIFO_BYPASS); + + ret = regmap_write(st->regmap, ADXL345_REG_FIFO_CTL, fifo_ctl); + if (ret < 0) + return ret; + } return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(adxl345_core_probe, "IIO_ADXL345");