From patchwork Wed Dec 4 10:03:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13893501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 254C3E77171 for ; Wed, 4 Dec 2024 10:23:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C2DBF10ECBF; Wed, 4 Dec 2024 10:23:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GqwEBmQE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9906F10ECBF for ; Wed, 4 Dec 2024 10:23:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733307804; x=1764843804; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gPTm9Yj8JEjuznbg0RRjX2izoKzDzdEzLDfw/OVzZKU=; b=GqwEBmQE7crpjeWsySGrNfK3ncf95Y8aN427cvZTEJ8WFbTJ7fvzNz6O kHlp8NKHI3ycZvh2OIBn5D4xoizTrEFTw99HGABRPWwcpYuGwH7uT+e4t SUH8OTX3C/+hg6ifRamJFauurA1g/YkhD1o5lz/6sFFOxusa11zG8O0cl 0brzLbkvRxrPJ7tqCphQ0hz8WgECeYsaIoLzIY+gMzDj1tTv/Wyigti5X RFIaug4XWbHk4w1F4mws8jNOYgvAgOpZYut2Wql1BAo+bvfGSP+PE9bnH nZ37FomX+6Ogewu7A9hfRpZYDMB04bZ41CLNdSrbkZrQbVjiypGcl+dp/ A==; X-CSE-ConnectionGUID: PWt7g5qWRPOVSAwr/WIY+A== X-CSE-MsgGUID: DgJrcNg7S0mnInLnTwbm5A== X-IronPort-AV: E=McAfee;i="6700,10204,11275"; a="44957828" X-IronPort-AV: E=Sophos;i="6.12,207,1728975600"; d="scan'208";a="44957828" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2024 02:23:24 -0800 X-CSE-ConnectionGUID: 71FvNqevRquhMviUyuIs+w== X-CSE-MsgGUID: S99sGPwXRQ6/g/QT3tANFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,207,1728975600"; d="scan'208";a="93615166" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orviesa009.jf.intel.com with ESMTP; 04 Dec 2024 02:23:23 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Cc: jouni.hogander@intel.com, jani.nikula@intel.com, jeevan.b@intel.com, Animesh Manna Subject: [PATCH v2 1/2] drm/i915/lobf: Add lobf enablement in post plane update Date: Wed, 4 Dec 2024 15:33:27 +0530 Message-Id: <20241204100328.3738778-2-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20241204100328.3738778-1-animesh.manna@intel.com> References: <20241204100328.3738778-1-animesh.manna@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enablement of LOBF is added in post plane update whenever has_lobf flag is set. As LOBF can be enabled in non-psr case as well so adding in post plane update. There is no change of configuring alpm with psr path. v1: Initial version. v2: Use encoder-mask to find the associated encoder from crtc-state. [Jani] Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_alpm.c | 25 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_alpm.h | 4 ++++ drivers/gpu/drm/i915/display/intel_display.c | 3 +++ 3 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 55f3ae1e68c9..75063342a100 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -367,6 +367,31 @@ void intel_alpm_configure(struct intel_dp *intel_dp, lnl_alpm_configure(intel_dp, crtc_state); } +void intel_alpm_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(state); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct intel_encoder *encoder; + + if (!crtc_state->has_lobf) + return; + + for_each_intel_encoder_mask(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + struct intel_dp *intel_dp; + + if (!intel_encoder_is_dp(encoder)) + continue; + + intel_dp = enc_to_intel_dp(encoder); + + if (intel_dp_is_edp(intel_dp)) + intel_alpm_configure(intel_dp, crtc_state); + } +} + static int i915_edp_lobf_info_show(struct seq_file *m, void *data) { struct intel_connector *connector = m->private; diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index 8c409b10dce6..2f862b0476a8 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -12,6 +12,8 @@ struct intel_dp; struct intel_crtc_state; struct drm_connector_state; struct intel_connector; +struct intel_atomic_state; +struct intel_crtc; void intel_alpm_init_dpcd(struct intel_dp *intel_dp); bool intel_alpm_compute_params(struct intel_dp *intel_dp, @@ -21,6 +23,8 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, struct drm_connector_state *conn_state); void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_alpm_post_plane_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_alpm_lobf_debugfs_add(struct intel_connector *connector); bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp); bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4805bf682d43..ffd96b187e5e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -55,6 +55,7 @@ #include "i9xx_plane.h" #include "i9xx_plane_regs.h" #include "i9xx_wm.h" +#include "intel_alpm.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_audio.h" @@ -1190,6 +1191,8 @@ static void intel_post_plane_update(struct intel_atomic_state *state, intel_psr_post_plane_update(state, crtc); + intel_alpm_post_plane_update(state, crtc); + intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) From patchwork Wed Dec 4 10:03:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Manna, Animesh" X-Patchwork-Id: 13893502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26EC5E7716D for ; Wed, 4 Dec 2024 10:23:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C83E810ECC0; Wed, 4 Dec 2024 10:23:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jqzzAkV9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3D2D610ECC0 for ; Wed, 4 Dec 2024 10:23:27 +0000 (UTC) DKIM-Signature: v=1; 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d="scan'208";a="93615174" Received: from srr4-3-linux-101-amanna.iind.intel.com ([10.223.74.76]) by orviesa009.jf.intel.com with ESMTP; 04 Dec 2024 02:23:26 -0800 From: Animesh Manna To: intel-gfx@lists.freedesktop.org Cc: jouni.hogander@intel.com, jani.nikula@intel.com, jeevan.b@intel.com, Animesh Manna Subject: [PATCH v2 2/2] drm/i915/lobf: Add debug print for LOBF Date: Wed, 4 Dec 2024 15:33:28 +0530 Message-Id: <20241204100328.3738778-3-animesh.manna@intel.com> X-Mailer: git-send-email 2.29.0 In-Reply-To: <20241204100328.3738778-1-animesh.manna@intel.com> References: <20241204100328.3738778-1-animesh.manna@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Lobf is enabled part of ALPM configuration and if has_lobf is set to true respective bit for LOBF will be set. Add debug print while setting the bitfield of LOBF. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_alpm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 75063342a100..5fa6b36b0193 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -353,8 +353,10 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); } - if (crtc_state->has_lobf) + if (crtc_state->has_lobf) { alpm_ctl |= ALPM_CTL_LOBF_ENABLE; + drm_dbg_kms(display->drm, "Link off between frames (LOBF) enabled\n"); + } alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines);