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Wed, 04 Dec 2024 10:52:54 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4B4AqsSX008972; Wed, 4 Dec 2024 10:52:54 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4B4AqrSO008893 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 10:52:54 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id E3D7419E4; Wed, 4 Dec 2024 18:52:52 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ziyue Zhang Subject: [PATCH 1/3] dt-bindings: phy: qcom,qmp-pcie: add optional current load properties Date: Wed, 4 Dec 2024 18:52:47 +0800 Message-Id: <20241204105249.3544114-2-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204105249.3544114-1-quic_ziyuzhan@quicinc.com> References: <20241204105249.3544114-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 7MnpvqgsvsAYFISoTdlQfAIribvmbCgW X-Proofpoint-GUID: 7MnpvqgsvsAYFISoTdlQfAIribvmbCgW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1011 phishscore=0 adultscore=0 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040085 On some platforms, the power supply for PCIe PHY is not able to provide enough current when it works in LPM mode. Hence, PCIe PHY driver needs to set current load to vote the regulator to HPM mode. Document the current load as properties for each power supply PCIe PHY required, namely vdda-phy-max-microamp, vdda-pll-max-microamp and vdda-qref-max-microamp, respectively.PCIe PHY driver should parse them to set appropriate current load during PHY power on. This three properties are optional and not mandatory for those platforms that PCIe PHY can still work with power supply. Signed-off-by: Ziyue Zhang --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 34d977af9263..0e2715301c54 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -78,10 +78,16 @@ properties: vdda-phy-supply: true + vdda-phy-max-microamp: true + vdda-pll-supply: true + vdda-pll-max-microamp: true + vdda-qref-supply: true + vdda-qref-max-microamp: true + qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array @@ -261,6 +267,7 @@ examples: vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; + vdda-pll-max-microamp = <165000>; #clock-cells = <0>; clock-output-names = "pcie_2b_pipe_clk"; @@ -288,6 +295,7 @@ examples: vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; + vdda-pll-max-microamp = <165000>; qcom,4ln-config-sel = <&tcsr 0xa044 0>; From patchwork Wed Dec 4 10:52:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyue Zhang X-Patchwork-Id: 13893550 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D4E81B2180; Wed, 4 Dec 2024 10:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733309586; cv=none; b=gWBAlWPJbkB2jYkNLLC2QcQKj5YuLwX6pnhvnrmYB0+z039LCH840GSLez7IFLGlPB+Eotu922+QBsLoquxKvV6nkbUbl2dILoetTXXKKaQQN1AUydNsK4QxYFh8QdaAFrivTL+dFDVTtFA45CufBPYv8oIy4efEQU9kXocpLd8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 4 Dec 2024 10:52:55 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 437uskmrtm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 10:52:55 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4B4AqsDt008980; Wed, 4 Dec 2024 10:52:55 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4B4AqsHj008971 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 10:52:54 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4438065) id 5568219E7; Wed, 4 Dec 2024 18:52:53 +0800 (CST) From: Ziyue Zhang To: vkoul@kernel.org, kishon@kernel.org, dmitry.baryshkov@linaro.org, abel.vesa@linaro.org, neil.armstrong@linaro.org, manivannan.sadhasivam@linaro.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Ziyue Zhang Subject: [PATCH 2/3] phy: qcom: qmp-pcie: add current load vote/devote for PCIe PHY Date: Wed, 4 Dec 2024 18:52:48 +0800 Message-Id: <20241204105249.3544114-3-quic_ziyuzhan@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241204105249.3544114-1-quic_ziyuzhan@quicinc.com> References: <20241204105249.3544114-1-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: igVsU6bqkqVrkfhZhbB7AnerrjJHwSGZ X-Proofpoint-GUID: igVsU6bqkqVrkfhZhbB7AnerrjJHwSGZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 adultscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 mlxscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040085 On some platform (eg.qcs615), the current that phy consumes will exceed the maximum current the regulator can provide in LPM mode, leading to over current protection and system boot up stuck. Fix this issue by setting regulator load to an expected value getting from phy device tree node during init so that the regulator can scale up to HPM to allow a larger current load. This change will also set load to zero during deinit to let regulator scale down to LPM mode to reduce itself's power consumptionif PCIe suspend. Signed-off-by: Ziyue Zhang --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 35 ++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index c8e39c147ba4..782d51ab5cf1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -39,6 +39,7 @@ #include "phy-qcom-qmp-pcie-qhp.h" #define PHY_INIT_COMPLETE_TIMEOUT 10000 +#define MAX_PROP_SIZE 32 /* set of registers with offsets different per-PHY */ enum qphy_reg_layout { @@ -2905,6 +2906,7 @@ struct qmp_pcie { struct reset_control_bulk_data *resets; struct reset_control *nocsr_reset; struct regulator_bulk_data *vregs; + u32 *max_current_load; struct phy *phy; int mode; @@ -4087,6 +4089,17 @@ static int qmp_pcie_init(struct phy *phy) const struct qmp_phy_cfg *cfg = qmp->cfg; int ret; + for (int i = 0; i < cfg->num_vregs; i++) { + if (qmp->max_current_load[i]) { + ret = regulator_set_load(qmp->vregs[i].consumer, qmp->max_current_load[i]); + if (ret) { + dev_err(&phy->dev, + "failed to set load at %s\n", qmp->vregs[i].supply); + return ret; + } + } + } + ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); if (ret) { dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); @@ -4129,6 +4142,7 @@ static int qmp_pcie_init(struct phy *phy) static int qmp_pcie_exit(struct phy *phy) { + int ret; struct qmp_pcie *qmp = phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -4137,7 +4151,16 @@ static int qmp_pcie_exit(struct phy *phy) clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); - + for (int i = 0; i < cfg->num_vregs; i++) { + if (qmp->max_current_load[i]) { + ret = regulator_set_load(qmp->vregs[i].consumer, 0); + if (ret) { + dev_err(&phy->dev, + "failed to set load at %s\n", qmp->vregs[i].supply); + return ret; + } + } + } return 0; } @@ -4274,14 +4297,22 @@ static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) const struct qmp_phy_cfg *cfg = qmp->cfg; struct device *dev = qmp->dev; int num = cfg->num_vregs; + char prop_name[MAX_PROP_SIZE]; int i; qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); if (!qmp->vregs) return -ENOMEM; - for (i = 0; i < num; i++) + qmp->max_current_load = devm_kcalloc(dev, num, sizeof(*qmp->max_current_load), GFP_KERNEL); + if (!qmp->max_current_load) + return -ENOMEM; + + for (i = 0; i < num; i++) { qmp->vregs[i].supply = cfg->vreg_list[i]; + snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", qmp->vregs[i].supply); + of_property_read_u32(qmp->dev->of_node, prop_name, &qmp->max_current_load[i]); + } return devm_regulator_bulk_get(dev, num, qmp->vregs); } From patchwork Wed Dec 4 10:52:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyue Zhang X-Patchwork-Id: 13893549 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87AC51B0F3E; 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The value of this property is from the power grid guide. It is the maximum current the regulator can provide. The property will be parsed by PCIe PHY driver to set the current load. Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 18f131ae9e07..6d93ef0d886b 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -215,6 +215,7 @@ &pcie { &pcie_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; + vdda-pll-max-microamp = <165000>; status = "okay"; };