From patchwork Wed Dec 4 14:43:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 13893891 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46A99205AB3; Wed, 4 Dec 2024 14:53:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733323986; cv=none; b=BEZBpD4dUl317KnQieTbOMh2awjyyXd7VzmUKJzav0aCJAMD4+7OGHP0XJ2k2es8sKnHNrkGIJG/Zs9CvlTjlJngemOMIRGL8Uz4LH8u8/9sCOKrx/Cn5uAYhXD7wMhe5zhhV32gDoa4TTcPQOrDcFC2pTtEW9qTluFQ/XY5V90= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733323986; c=relaxed/simple; bh=5H9xiq6zQ/EOKxt05SxXOzasrc6/C/oXkvCoJzbAo3c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=bo80N8AMkqSORO4ZdOPYY/KJTEYDnfQe0NbxozCK6nFj6SDLYFtEAzaPrNIbHCdC4SD8DtnjYrk4cf8JSsO3FvP9VQx5DoX9q36tJ3olYq/LPpPnFRdgT9wATf1u+WbuVCEijMLtJqwYopQSNd9QlTfTdmNCVkxRNC1SYSW1QYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Pmdd5bal; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Pmdd5bal" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B46kdCJ023313; Wed, 4 Dec 2024 14:52:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= D90expnj0SSF/9ucUSQPsvixz5/QNnMYJizpIQMPybs=; b=Pmdd5balSEsMIRaP 39RdXI/gWvXM0dgCKj2PVYYXgkHpQ3TIb8+mDwn1nantSYr/1CveFVmxQ22MfJ1C wATuiAZ2BQzZmWPDlFgxCGJcBgij1RUWwWmAohFT+OKlQxHb0/b89WqZhDPrcTGQ tI6uWZI5TWOibiOJNMhc5TtNu6Z5t0agXaFZrMaswOJqVz4Ydj+qCji2srHbG0iC Uwt/mnFl5ATCZ4L/QYXJuxQe+pVp3j1z7FEGvCPEzEFxEMcyc1KXrjVe5irc7cvj /9hetgbxyhu4aaf5PMbD8FWGhLQz9Vgz8s/E1WQMUxO+mY0mBxsLBaipwdo27wbA SowD5w== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43aj4298f2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 14:52:51 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4EqoGC004299 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 14:52:50 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 06:52:44 -0800 From: Lei Wei Date: Wed, 4 Dec 2024 22:43:53 +0800 Subject: [PATCH net-next v2 1/5] dt-bindings: net: pcs: Add Ethernet PCS for Qualcomm IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-ipq_pcs_rc1-v2-1-26155f5364a1@quicinc.com> References: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> In-Reply-To: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733323958; l=8670; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=5H9xiq6zQ/EOKxt05SxXOzasrc6/C/oXkvCoJzbAo3c=; b=w08EN6Coz6JbfdAJHO4habL4TLj3rmBbHSzAUsVjSlgfOk8qFvOPoPGocy19qO0cCvl+/54Ny BXKgTDcraBVD1A4sedRXPqkLu2cxG/bhtvu/UGwS6PClpQGdWar0qPD X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tt8rb_3g4ZK6AFimI23gp5WVXQ4bsQkS X-Proofpoint-ORIG-GUID: tt8rb_3g4ZK6AFimI23gp5WVXQ4bsQkS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1011 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040114 The 'UNIPHY' PCS block in the IPQ9574 SoC includes PCS and SerDes functions. It supports different interface modes to enable Ethernet MAC connections to different types of external PHYs/switch. It includes PCS functions for 1Gbps and 2.5Gbps interface modes and XPCS functions for 10Gbps interface modes. There are three UNIPHY (PCS) instances in IPQ9574 SoC which provide PCS/XPCS functions to the six Ethernet ports. Signed-off-by: Lei Wei Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/pcs/qcom,ipq9574-pcs.yaml | 190 +++++++++++++++++++++ include/dt-bindings/net/qcom,ipq9574-pcs.h | 15 ++ 2 files changed, 205 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml new file mode 100644 index 000000000000..74573c28d6fe --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/qcom,ipq9574-pcs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ethernet PCS for Qualcomm IPQ9574 SoC + +maintainers: + - Lei Wei + +description: + The UNIPHY hardware blocks in the Qualcomm IPQ SoC include PCS and SerDes + functions. They enable connectivity between the Ethernet MAC inside the + PPE (packet processing engine) and external Ethernet PHY/switch. There are + three UNIPHY instances in IPQ9574 SoC which provide PCS functions to the + six Ethernet ports. + + For SGMII (1Gbps PHY) or 2500BASE-X (2.5Gbps PHY) interface modes, the PCS + function is enabled by using the PCS block inside UNIPHY. For USXGMII (10Gbps + PHY), the XPCS block in UNIPHY is used. + + The SerDes provides 125M (1Gbps mode) or 312.5M (2.5Gbps and 10Gbps modes) + RX and TX clocks to the NSSCC (Networking Sub System Clock Controller). The + NSSCC divides these clocks and generates the MII RX and TX clocks to each + of the MII interfaces between the PCS and MAC, as per the link speeds and + interface modes. + + Different IPQ SoC may support different number of UNIPHYs (PCSes) since the + number of ports and their capabilities can be different between these SoCs + + Below diagram depicts the UNIPHY (PCS) connections for an IPQ9574 SoC based + board. In this example, the PCS0 has four GMIIs/XGMIIs, which can connect + with four MACs to support QSGMII (4 x 1Gbps) or 10G_QXGMII (4 x 2.5Gbps) + interface modes. + + - +-------+ +---------+ +-------------------------+ + +---------+CMN PLL| | GCC | | NSSCC (Divider) | + | +----+--+ +----+----+ +--+-------+--------------+ + | | | ^ | + | 31.25M | SYS/AHB|clk RX/TX|clk +------------+ + | ref clk| | | | | + | | v | MII RX|TX clk MAC| RX/TX clk + |25/50M +--+---------+----------+-------+---+ +-+---------+ + |ref clk | | +----------------+ | | | | PPE | + v | | | UNIPHY0 V | | V | + +-------+ | v | +-----------+ (X)GMII| | | + | | | +---+---+ | |--------|------|-- MAC0 | + | | | | | | | (X)GMII| | | + | Quad | | |SerDes | | PCS/XPCS |--------|------|-- MAC1 | + | +<----+ | | | | (X)GMII| | | + |(X)GPHY| | | | | |--------|------|-- MAC2 | + | | | | | | | (X)GMII| | | + | | | +-------+ | |--------|------|-- MAC3 | + +-------+ | | | | | | + | +-----------+ | | | + +-----------------------------------+ | | + +--+---------+----------+-------+---+ | | + +-------+ | UNIPHY1 | | | + | | | +-----------+ | | | + |(X)GPHY| | +-------+ | | (X)GMII| | | + | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC4 | + | | | | | | | | | | + +-------+ | +-------+ | | | | | + | +-----------+ | | | + +-----------------------------------+ | | + +--+---------+----------+-------+---+ | | + +-------+ | UNIPHY2 | | | + | | | +-----------+ | | | + |(X)GPHY| | +-------+ | | (X)GMII| | | + | +<----+ |SerDes | | PCS/XPCS |--------|------|- MAC5 | + | | | | | | | | | | + +-------+ | +-------+ | | | | | + | +-----------+ | | | + +-----------------------------------+ +-----------+ + +properties: + compatible: + enum: + - qcom,ipq9574-pcs + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + items: + - description: System clock + - description: AHB clock needed for register interface access + + clock-names: + items: + - const: sys + - const: ahb + + '#clock-cells': + const: 1 + description: See include/dt-bindings/net/qcom,ipq9574-pcs.h for constants + +patternProperties: + '^pcs-mii@[0-4]$': + type: object + description: PCS MII interface. + + properties: + reg: + minimum: 0 + maximum: 4 + description: MII index + + clocks: + items: + - description: PCS MII RX clock + - description: PCS MII TX clock + + clock-names: + items: + - const: rx + - const: tx + + required: + - reg + - clocks + - clock-names + + additionalProperties: false + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + ethernet-pcs@7a00000 { + compatible = "qcom,ipq9574-pcs"; + reg = <0x7a00000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>; + clock-names = "sys", + "ahb"; + #clock-cells = <1>; + + pcs-mii@0 { + reg = <0>; + clocks = <&nsscc 116>, + <&nsscc 117>; + clock-names = "rx", + "tx"; + }; + + pcs-mii@1 { + reg = <1>; + clocks = <&nsscc 118>, + <&nsscc 119>; + clock-names = "rx", + "tx"; + }; + + pcs-mii@2 { + reg = <2>; + clocks = <&nsscc 120>, + <&nsscc 121>; + clock-names = "rx", + "tx"; + }; + + pcs-mii@3 { + reg = <3>; + clocks = <&nsscc 122>, + <&nsscc 123>; + clock-names = "rx", + "tx"; + }; + }; diff --git a/include/dt-bindings/net/qcom,ipq9574-pcs.h b/include/dt-bindings/net/qcom,ipq9574-pcs.h new file mode 100644 index 000000000000..96bd036aaa70 --- /dev/null +++ b/include/dt-bindings/net/qcom,ipq9574-pcs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Device Tree constants for the Qualcomm IPQ9574 PCS + */ + +#ifndef _DT_BINDINGS_PCS_QCOM_IPQ9574_H +#define _DT_BINDINGS_PCS_QCOM_IPQ9574_H + +/* The RX and TX clocks which are provided from the SerDes to NSSCC. */ +#define PCS_RX_CLK 0 +#define PCS_TX_CLK 1 + +#endif /* _DT_BINDINGS_PCS_QCOM_IPQ9574_H */ From patchwork Wed Dec 4 14:43:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 13893893 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4C1620B213; Wed, 4 Dec 2024 14:53:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733323994; cv=none; b=ttdqErsyqkLHh5nJghuSzARRZYPZWiGjw6oYWV+w/v8srRohll+mSCsVEztBLJA7dfDedhyMM4JFigC0brpk3LfEo+mIGQXMti7CeRRHnk1v8ksSvF29ewlKTvakFJyi3ChxMqICWKZUPhiZGCWMjKaPhMvsVFLGeFCq5OZGm5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733323994; c=relaxed/simple; bh=hX2+RisNs7Sopsb8GRdv8J+NnTxdu3SzscHvnqrORME=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=deY5xoksRbxblaxa1skfJtOP8PjEIrR/1sT5d80Hk8RK0Z3qWEJ/aGMlzT1FcnOqsWRHH4k3RicKWAh8cbfHqZpNV8MsG+N3S60Q5voRKxhfljHifeB4CQi96PWN25qL+O61rUBKln2zNfWinvKP7e7Tsso3Dh1zFsrFEvU6GYY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=WdwN7mO9; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WdwN7mO9" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B4Ell9g032114; Wed, 4 Dec 2024 14:52:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= idFW12SlE3rXTKh+FQtdnXDuH7ENmQNRwNsOyDnOa7E=; b=WdwN7mO9G+BNGDMa LnJT1G2OqYnZ+QDkSlWoHB/Q3MIONbW2duQMx2sdmH/BnvwnamHyH0FLASYWFnBc vYnxx3lVUITu0R1SB2c4pjatjRwG4+ghq3Beq1NkLOQeM7y2WyZ1j70K3IPU+xxH m8I3wYNEpOxGmMA4ERtgNmoNYoBh+JRQ3mliyrlWppRTmjaNSu9HRbTQgd3JIQms kNzGWA5FTUaX+A5TaPbI9H+giPTPi7cTbbi3QFBQO5RihZhlfUFi/L39EGLgmvxh rk52sQp3LH6Ly/dKdnDnS9zL3xTKcxgNMHCOMWn3agahYT6DvwtRBJCCI3Plz+kt fk213Q== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43a3faufrm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 14:52:56 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4EqtNV019416 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 14:52:55 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 06:52:49 -0800 From: Lei Wei Date: Wed, 4 Dec 2024 22:43:54 +0800 Subject: [PATCH net-next v2 2/5] net: pcs: Add PCS driver for Qualcomm IPQ9574 SoC Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-ipq_pcs_rc1-v2-2-26155f5364a1@quicinc.com> References: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> In-Reply-To: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733323958; l=9172; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=hX2+RisNs7Sopsb8GRdv8J+NnTxdu3SzscHvnqrORME=; b=aUfDKtJZwhjPkTMCOL3jM1+XiftEdOODAG0HIFUWjlf+0wqZjrOE5uJcYcMY7IvUqcSROge1D dXBq2LdkB72D8wX3SIiHgOerGrWImyBgGIruCKggkfWmslkY1U8pXSg X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pBlI1EV9u0HuQjDHYTCEHtNHTPH7Ono_ X-Proofpoint-GUID: pBlI1EV9u0HuQjDHYTCEHtNHTPH7Ono_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 mlxscore=0 suspectscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1011 priorityscore=1501 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040114 The 'UNIPHY' PCS hardware block in Qualcomm's IPQ SoC supports different interface modes to enable Ethernet MAC connections for different types of external PHYs/switch. Each UNIPHY block includes a SerDes and PCS/XPCS blocks, and can operate in either PCS or XPCS modes. It supports 1Gbps and 2.5Gbps interface modes (Ex: SGMII) using the PCS, and 10Gbps interface modes (Ex: USXGMII) using the XPCS. There are three UNIPHY (PCS) instances in IPQ9574 SoC which support the six Ethernet ports in the SoC. This patch adds support for the platform driver, probe and clock registrations for the PCS driver. The platform driver creates an 'ipq_pcs' instance for each of the UNIPHY used on the given board. Signed-off-by: Lei Wei --- drivers/net/pcs/Kconfig | 9 ++ drivers/net/pcs/Makefile | 1 + drivers/net/pcs/pcs-qcom-ipq9574.c | 245 +++++++++++++++++++++++++++++++++++++ 3 files changed, 255 insertions(+) diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index f6aa437473de..de2ec527d523 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -25,6 +25,15 @@ config PCS_MTK_LYNXI This module provides helpers to phylink for managing the LynxI PCS which is part of MediaTek's SoC and Ethernet switch ICs. +config PCS_QCOM_IPQ9574 + tristate "Qualcomm IPQ9574 PCS" + depends on OF && (ARCH_QCOM || COMPILE_TEST) + depends on HAS_IOMEM + help + This module provides driver for UNIPHY PCS available on Qualcomm + IPQ9574 SoC. The UNIPHY PCS supports both PCS and XPCS functions + to support different interface modes for MAC to PHY connections. + config PCS_RZN1_MIIC tristate "Renesas RZ/N1 MII converter" depends on OF && (ARCH_RZN1 || COMPILE_TEST) diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 4f7920618b90..2fa3faf8a5db 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -7,4 +7,5 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-plat.o \ obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o +obj-$(CONFIG_PCS_QCOM_IPQ9574) += pcs-qcom-ipq9574.o obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o diff --git a/drivers/net/pcs/pcs-qcom-ipq9574.c b/drivers/net/pcs/pcs-qcom-ipq9574.c new file mode 100644 index 000000000000..ea90c1902b61 --- /dev/null +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define XPCS_INDIRECT_ADDR 0x8000 +#define XPCS_INDIRECT_AHB_ADDR 0x83fc +#define XPCS_INDIRECT_ADDR_H GENMASK(20, 8) +#define XPCS_INDIRECT_ADDR_L GENMASK(7, 0) +#define XPCS_INDIRECT_DATA_ADDR(reg) (FIELD_PREP(GENMASK(15, 10), 0x20) | \ + FIELD_PREP(GENMASK(9, 2), \ + FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) + +/* PCS private data */ +struct ipq_pcs { + struct device *dev; + void __iomem *base; + struct regmap *regmap; + phy_interface_t interface; + + /* RX clock supplied to NSSCC */ + struct clk_hw rx_hw; + /* TX clock supplied to NSSCC */ + struct clk_hw tx_hw; +}; + +static unsigned long ipq_pcs_clk_rate_get(struct ipq_pcs *qpcs) +{ + switch (qpcs->interface) { + case PHY_INTERFACE_MODE_USXGMII: + return 312500000; + default: + return 125000000; + } +} + +/* Return clock rate for the RX clock supplied to NSSCC + * as per the interface mode. + */ +static unsigned long ipq_pcs_rx_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ipq_pcs *qpcs = container_of(hw, struct ipq_pcs, rx_hw); + + return ipq_pcs_clk_rate_get(qpcs); +} + +/* Return clock rate for the TX clock supplied to NSSCC + * as per the interface mode. + */ +static unsigned long ipq_pcs_tx_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ipq_pcs *qpcs = container_of(hw, struct ipq_pcs, tx_hw); + + return ipq_pcs_clk_rate_get(qpcs); +} + +static int ipq_pcs_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + switch (req->rate) { + case 125000000: + case 312500000: + return 0; + default: + return -EINVAL; + } +} + +/* Clock ops for the RX clock supplied to NSSCC */ +static const struct clk_ops ipq_pcs_rx_clk_ops = { + .determine_rate = ipq_pcs_clk_determine_rate, + .recalc_rate = ipq_pcs_rx_clk_recalc_rate, +}; + +/* Clock ops for the TX clock supplied to NSSCC */ +static const struct clk_ops ipq_pcs_tx_clk_ops = { + .determine_rate = ipq_pcs_clk_determine_rate, + .recalc_rate = ipq_pcs_tx_clk_recalc_rate, +}; + +static struct clk_hw *ipq_pcs_clk_hw_get(struct of_phandle_args *clkspec, + void *data) +{ + struct ipq_pcs *qpcs = data; + + switch (clkspec->args[0]) { + case PCS_RX_CLK: + return &qpcs->rx_hw; + case PCS_TX_CLK: + return &qpcs->tx_hw; + } + + return ERR_PTR(-EINVAL); +} + +/* Register the RX and TX clock which are output from SerDes to + * the NSSCC. The NSSCC driver assigns the RX and TX clock as + * parent, divides them to generate the MII RX and TX clock to + * each MII interface of the PCS as per the link speeds and + * interface modes. + */ +static int ipq_pcs_clk_register(struct ipq_pcs *qpcs) +{ + struct clk_init_data init = { }; + int ret; + + init.ops = &ipq_pcs_rx_clk_ops; + init.name = devm_kasprintf(qpcs->dev, GFP_KERNEL, "%s::rx_clk", + dev_name(qpcs->dev)); + if (!init.name) + return -ENOMEM; + + qpcs->rx_hw.init = &init; + ret = devm_clk_hw_register(qpcs->dev, &qpcs->rx_hw); + if (ret) + return ret; + + init.ops = &ipq_pcs_tx_clk_ops; + init.name = devm_kasprintf(qpcs->dev, GFP_KERNEL, "%s::tx_clk", + dev_name(qpcs->dev)); + if (!init.name) + return -ENOMEM; + + qpcs->tx_hw.init = &init; + ret = devm_clk_hw_register(qpcs->dev, &qpcs->tx_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(qpcs->dev, ipq_pcs_clk_hw_get, qpcs); +} + +static int ipq_pcs_regmap_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct ipq_pcs *qpcs = context; + + /* PCS uses direct AHB access while XPCS uses indirect AHB access */ + if (reg >= XPCS_INDIRECT_ADDR) { + writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg), + qpcs->base + XPCS_INDIRECT_AHB_ADDR); + *val = readl(qpcs->base + XPCS_INDIRECT_DATA_ADDR(reg)); + } else { + *val = readl(qpcs->base + reg); + } + + return 0; +} + +static int ipq_pcs_regmap_write(void *context, unsigned int reg, + unsigned int val) +{ + struct ipq_pcs *qpcs = context; + + /* PCS uses direct AHB access while XPCS uses indirect AHB access */ + if (reg >= XPCS_INDIRECT_ADDR) { + writel(FIELD_GET(XPCS_INDIRECT_ADDR_H, reg), + qpcs->base + XPCS_INDIRECT_AHB_ADDR); + writel(val, qpcs->base + XPCS_INDIRECT_DATA_ADDR(reg)); + } else { + writel(val, qpcs->base + reg); + } + + return 0; +} + +static const struct regmap_config ipq_pcs_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_read = ipq_pcs_regmap_read, + .reg_write = ipq_pcs_regmap_write, + .fast_io = true, +}; + +static int ipq9574_pcs_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ipq_pcs *qpcs; + struct clk *clk; + int ret; + + qpcs = devm_kzalloc(dev, sizeof(*qpcs), GFP_KERNEL); + if (!qpcs) + return -ENOMEM; + + qpcs->dev = dev; + + qpcs->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qpcs->base)) + return dev_err_probe(dev, PTR_ERR(qpcs->base), + "Failed to ioremap resource\n"); + + qpcs->regmap = devm_regmap_init(dev, NULL, qpcs, &ipq_pcs_regmap_cfg); + if (IS_ERR(qpcs->regmap)) + return dev_err_probe(dev, PTR_ERR(qpcs->regmap), + "Failed to allocate register map\n"); + + clk = devm_clk_get_enabled(dev, "sys"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to enable SYS clock\n"); + + clk = devm_clk_get_enabled(dev, "ahb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Failed to enable AHB clock\n"); + + ret = ipq_pcs_clk_register(qpcs); + if (ret) + return ret; + + platform_set_drvdata(pdev, qpcs); + + return 0; +} + +static const struct of_device_id ipq9574_pcs_of_mtable[] = { + { .compatible = "qcom,ipq9574-pcs" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, ipq9574_pcs_of_mtable); + +static struct platform_driver ipq9574_pcs_driver = { + .driver = { + .name = "ipq9574_pcs", + .suppress_bind_attrs = true, + .of_match_table = ipq9574_pcs_of_mtable, + }, + .probe = ipq9574_pcs_probe, +}; +module_platform_driver(ipq9574_pcs_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm IPQ9574 PCS driver"); +MODULE_AUTHOR("Lei Wei "); From patchwork Wed Dec 4 14:43:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 13893894 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7A8820C483; Wed, 4 Dec 2024 14:53:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733323998; cv=none; b=tCQDgUqkAcl9m6k72WH/Jeuf7jTQ0aFMzjqcXcj9/MX8Ba9uJykxPqWjyrxA8wrpSOppCnXcyhpSQ+MCe+PQgxjM0kGEu360bo62i7Mu9OUGx06NY0ssoslOl1xwbYBK/W4e4UlalbaOTDzALxhxv+4QnMpLkGag7xTsqQ9JEMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733323998; c=relaxed/simple; bh=Dfg4V6X90rnF3AsmfnG9NF/ih4/tYqxrjeqAT4O+lBs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tJyx7U162nUcznN29TTF2XyXMn/Rmgd9DoYxB/5lFO5rwRbW5opq4IUf98fQXGNw7krofT7QRiKLVVcOCCZu0C4YrT8VmyYsCOK67u5J6x80DHXWU/CshPDJdasyAsgtEtXb48xb5B0IiVyrUgjJAR3bUlGIT0r6ZszJj6oRdN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=opSFU5EV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="opSFU5EV" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B45RksO010286; Wed, 4 Dec 2024 14:53:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= WoP0p0tCvWWHgYoyMz87xscZLWVguYkyWMA6hEj4+tY=; b=opSFU5EVqHp3rMlL zR/8ahqIvkSUCl9CKXuSCguWqgfVERARbrqlrHNLjP7nokvK5zCtD5ursQWSh7o4 3Y3+NYBF6pByB7bn+cgz91cJ1YeOSQssR79KEYGj36ibFINZXZkPbxvAuZZirqA9 ofaT/asQ9XiocNq41JU/BJnwP2h+d6Cq3ccHUklkUV1jXrKWHbbcNmLtvTX0lCCE rnkmp/ACn/arsqB9/kjRv5LpYz6Bg3lL5Msyy0Fm3YU5JKKOWnUBi70SIpm94iBh 3mh5A9w6CwiBncAQlEw6cN8svyJrr+G8on8dgGIqlTcXXZigpBOqY4q73HhFq6g1 +2Hzhw== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43a4by39tj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 14:53:02 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4Er1AC004847 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 14:53:01 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 06:52:55 -0800 From: Lei Wei Date: Wed, 4 Dec 2024 22:43:55 +0800 Subject: [PATCH net-next v2 3/5] net: pcs: qcom-ipq9574: Add PCS instantiation and phylink operations Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-ipq_pcs_rc1-v2-3-26155f5364a1@quicinc.com> References: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> In-Reply-To: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733323958; l=14584; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=Dfg4V6X90rnF3AsmfnG9NF/ih4/tYqxrjeqAT4O+lBs=; b=Yuo7Jn3yWheoBAiA7UFLqGQ6GwN2BrCMzFsr/vee7qq5nERvZpM/OFTF5BQHbT/fnnb1fuE/P 7L7BB9/7idPBzhEQmVJB+eBTuEDlu55tH5ZKT63TxAN7PTr5UKBON/Y X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EXVdHzRLdkr3SGuxQZBQNkTnbBrnv5du X-Proofpoint-ORIG-GUID: EXVdHzRLdkr3SGuxQZBQNkTnbBrnv5du X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1011 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 spamscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040114 This patch adds the following PCS functionality for the PCS driver for IPQ9574 SoC: a.) Parses PCS MII DT nodes and instantiate each MII PCS instance. b.) Exports PCS instance get and put APIs. The network driver calls the PCS get API to get and associate the PCS instance with the port MAC. c.) PCS phylink operations for SGMII/QSGMII interface modes. Signed-off-by: Lei Wei --- drivers/net/pcs/pcs-qcom-ipq9574.c | 462 +++++++++++++++++++++++++++++++++++ include/linux/pcs/pcs-qcom-ipq9574.h | 16 ++ 2 files changed, 478 insertions(+) diff --git a/drivers/net/pcs/pcs-qcom-ipq9574.c b/drivers/net/pcs/pcs-qcom-ipq9574.c index ea90c1902b61..3608f5506477 100644 --- a/drivers/net/pcs/pcs-qcom-ipq9574.c +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c @@ -6,12 +6,46 @@ #include #include #include +#include +#include +#include #include +#include #include #include #include +/* Maximum number of MIIs per PCS instance. There are 5 MIIs for PSGMII. */ +#define PCS_MAX_MII_NRS 5 + +#define PCS_CALIBRATION 0x1e0 +#define PCS_CALIBRATION_DONE BIT(7) + +#define PCS_MODE_CTRL 0x46c +#define PCS_MODE_SEL_MASK GENMASK(12, 8) +#define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) +#define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) + +#define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) +#define PCS_MII_ADPT_RESET BIT(11) +#define PCS_MII_FORCE_MODE BIT(3) +#define PCS_MII_SPEED_MASK GENMASK(2, 1) +#define PCS_MII_SPEED_1000 FIELD_PREP(PCS_MII_SPEED_MASK, 0x2) +#define PCS_MII_SPEED_100 FIELD_PREP(PCS_MII_SPEED_MASK, 0x1) +#define PCS_MII_SPEED_10 FIELD_PREP(PCS_MII_SPEED_MASK, 0x0) + +#define PCS_MII_STS(x) (0x488 + 0x18 * (x)) +#define PCS_MII_LINK_STS BIT(7) +#define PCS_MII_STS_DUPLEX_FULL BIT(6) +#define PCS_MII_STS_SPEED_MASK GENMASK(5, 4) +#define PCS_MII_STS_SPEED_10 0 +#define PCS_MII_STS_SPEED_100 1 +#define PCS_MII_STS_SPEED_1000 2 + +#define PCS_PLL_RESET 0x780 +#define PCS_ANA_SW_RESET BIT(6) + #define XPCS_INDIRECT_ADDR 0x8000 #define XPCS_INDIRECT_AHB_ADDR 0x83fc #define XPCS_INDIRECT_ADDR_H GENMASK(20, 8) @@ -20,6 +54,18 @@ FIELD_PREP(GENMASK(9, 2), \ FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) +/* Per PCS MII private data */ +struct ipq_pcs_mii { + struct ipq_pcs *qpcs; + struct phylink_pcs pcs; + int index; + + /* RX clock from NSSCC to PCS MII */ + struct clk *rx_clk; + /* TX clock from NSSCC to PCS MII */ + struct clk *tx_clk; +}; + /* PCS private data */ struct ipq_pcs { struct device *dev; @@ -27,12 +73,422 @@ struct ipq_pcs { struct regmap *regmap; phy_interface_t interface; + /* Lock to protect PCS configurations shared by multiple MII ports */ + struct mutex config_lock; + /* RX clock supplied to NSSCC */ struct clk_hw rx_hw; /* TX clock supplied to NSSCC */ struct clk_hw tx_hw; + + struct ipq_pcs_mii *qpcs_mii[PCS_MAX_MII_NRS]; }; +#define phylink_pcs_to_qpcs_mii(_pcs) \ + container_of(_pcs, struct ipq_pcs_mii, pcs) + +static void ipq_pcs_get_state_sgmii(struct ipq_pcs *qpcs, + int index, + struct phylink_link_state *state) +{ + unsigned int val; + int ret; + + ret = regmap_read(qpcs->regmap, PCS_MII_STS(index), &val); + if (ret) { + state->link = 0; + return; + } + + state->link = !!(val & PCS_MII_LINK_STS); + + if (!state->link) + return; + + switch (FIELD_GET(PCS_MII_STS_SPEED_MASK, val)) { + case PCS_MII_STS_SPEED_1000: + state->speed = SPEED_1000; + break; + case PCS_MII_STS_SPEED_100: + state->speed = SPEED_100; + break; + case PCS_MII_STS_SPEED_10: + state->speed = SPEED_10; + break; + default: + state->link = false; + return; + } + + if (val & PCS_MII_STS_DUPLEX_FULL) + state->duplex = DUPLEX_FULL; + else + state->duplex = DUPLEX_HALF; +} + +static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, + phy_interface_t interface) +{ + unsigned int val; + int ret; + + /* Configure PCS interface mode */ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + val = PCS_MODE_SGMII; + break; + case PHY_INTERFACE_MODE_QSGMII: + val = PCS_MODE_QSGMII; + break; + default: + dev_err(qpcs->dev, + "Unsupported interface %s\n", phy_modes(interface)); + return -EOPNOTSUPP; + } + + ret = regmap_update_bits(qpcs->regmap, PCS_MODE_CTRL, + PCS_MODE_SEL_MASK, val); + if (ret) + return ret; + + /* PCS PLL reset */ + ret = regmap_update_bits(qpcs->regmap, PCS_PLL_RESET, + PCS_ANA_SW_RESET, 0); + if (ret) + return ret; + + fsleep(1000); + ret = regmap_update_bits(qpcs->regmap, PCS_PLL_RESET, + PCS_ANA_SW_RESET, PCS_ANA_SW_RESET); + if (ret) + return ret; + + /* Wait for calibration completion */ + ret = regmap_read_poll_timeout(qpcs->regmap, PCS_CALIBRATION, + val, val & PCS_CALIBRATION_DONE, + 1000, 100000); + if (ret) { + dev_err(qpcs->dev, "PCS calibration timed-out\n"); + return ret; + } + + qpcs->interface = interface; + + return 0; +} + +static int ipq_pcs_config_sgmii(struct ipq_pcs *qpcs, + int index, + unsigned int neg_mode, + phy_interface_t interface) +{ + int ret; + + /* Access to PCS registers such as PCS_MODE_CTRL which are + * common to all MIIs, is lock protected and configured + * only once. + */ + mutex_lock(&qpcs->config_lock); + + if (qpcs->interface != interface) { + ret = ipq_pcs_config_mode(qpcs, interface); + if (ret) { + mutex_unlock(&qpcs->config_lock); + return ret; + } + } + + mutex_unlock(&qpcs->config_lock); + + /* Nothing to do here as in-band autoneg mode is enabled + * by default for each PCS MII port. + */ + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) + return 0; + + /* Set force speed mode */ + return regmap_update_bits(qpcs->regmap, PCS_MII_CTRL(index), + PCS_MII_FORCE_MODE, PCS_MII_FORCE_MODE); +} + +static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, + int index, + unsigned int neg_mode, + int speed) +{ + unsigned int val; + int ret; + + /* PCS speed need not be configured if in-band autoneg is enabled */ + if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) { + /* PCS speed set for force mode */ + switch (speed) { + case SPEED_1000: + val = PCS_MII_SPEED_1000; + break; + case SPEED_100: + val = PCS_MII_SPEED_100; + break; + case SPEED_10: + val = PCS_MII_SPEED_10; + break; + default: + dev_err(qpcs->dev, "Invalid SGMII speed %d\n", speed); + return -EINVAL; + } + + ret = regmap_update_bits(qpcs->regmap, PCS_MII_CTRL(index), + PCS_MII_SPEED_MASK, val); + if (ret) + return ret; + } + + /* PCS adapter reset */ + ret = regmap_update_bits(qpcs->regmap, PCS_MII_CTRL(index), + PCS_MII_ADPT_RESET, 0); + if (ret) + return ret; + + return regmap_update_bits(qpcs->regmap, PCS_MII_CTRL(index), + PCS_MII_ADPT_RESET, PCS_MII_ADPT_RESET); +} + +static int ipq_pcs_enable(struct phylink_pcs *pcs) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + int ret; + + ret = clk_prepare_enable(qpcs_mii->rx_clk); + if (ret) { + dev_err(qpcs->dev, "Failed to enable MII %d RX clock\n", index); + return ret; + } + + ret = clk_prepare_enable(qpcs_mii->tx_clk); + if (ret) { + dev_err(qpcs->dev, "Failed to enable MII %d TX clock\n", index); + clk_disable_unprepare(qpcs_mii->rx_clk); + return ret; + } + + return 0; +} + +static void ipq_pcs_disable(struct phylink_pcs *pcs) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + + if (__clk_is_enabled(qpcs_mii->rx_clk)) + clk_disable_unprepare(qpcs_mii->rx_clk); + + if (__clk_is_enabled(qpcs_mii->tx_clk)) + clk_disable_unprepare(qpcs_mii->tx_clk); +} + +static void ipq_pcs_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + ipq_pcs_get_state_sgmii(qpcs, index, state); + break; + default: + break; + } + + dev_dbg_ratelimited(qpcs->dev, + "mode=%s/%s/%s link=%u\n", + phy_modes(state->interface), + phy_speed_to_str(state->speed), + phy_duplex_to_str(state->duplex), + state->link); +} + +static int ipq_pcs_config(struct phylink_pcs *pcs, + unsigned int neg_mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + default: + dev_err(qpcs->dev, + "Unsupported interface %s\n", phy_modes(interface)); + return -EOPNOTSUPP; + }; +} + +static void ipq_pcs_link_up(struct phylink_pcs *pcs, + unsigned int neg_mode, + phy_interface_t interface, + int speed, int duplex) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + struct ipq_pcs *qpcs = qpcs_mii->qpcs; + int index = qpcs_mii->index; + int ret; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + ret = ipq_pcs_link_up_config_sgmii(qpcs, index, + neg_mode, speed); + break; + default: + dev_err(qpcs->dev, + "Unsupported interface %s\n", phy_modes(interface)); + return; + } + + if (ret) + dev_err(qpcs->dev, "PCS link up fail for interface %s\n", + phy_modes(interface)); +} + +static const struct phylink_pcs_ops ipq_pcs_phylink_ops = { + .pcs_enable = ipq_pcs_enable, + .pcs_disable = ipq_pcs_disable, + .pcs_get_state = ipq_pcs_get_state, + .pcs_config = ipq_pcs_config, + .pcs_link_up = ipq_pcs_link_up, +}; + +/** + * ipq_pcs_get() - Get the IPQ PCS MII instance + * @np: Device tree node to the PCS MII + * + * Description: Get the phylink PCS instance for the given PCS MII node @np. + * This instance is associated with the specific MII of the PCS and the + * corresponding Ethernet netdevice. + * + * Return: A pointer to the phylink PCS instance or an error-pointer value. + */ +struct phylink_pcs *ipq_pcs_get(struct device_node *np) +{ + struct platform_device *pdev; + struct ipq_pcs_mii *qpcs_mii; + struct ipq_pcs *qpcs; + u32 index; + + if (of_property_read_u32(np, "reg", &index)) + return ERR_PTR(-EINVAL); + + if (index >= PCS_MAX_MII_NRS) + return ERR_PTR(-EINVAL); + + /* Get the parent device */ + pdev = of_find_device_by_node(np->parent); + if (!pdev) + return ERR_PTR(-ENODEV); + + qpcs = platform_get_drvdata(pdev); + if (!qpcs) { + put_device(&pdev->dev); + + /* If probe is not yet completed, return DEFER to + * the dependent driver. + */ + return ERR_PTR(-EPROBE_DEFER); + } + + qpcs_mii = qpcs->qpcs_mii[index]; + if (!qpcs_mii) { + put_device(&pdev->dev); + return ERR_PTR(-ENOENT); + } + + return &qpcs_mii->pcs; +} +EXPORT_SYMBOL(ipq_pcs_get); + +/** + * ipq_pcs_put() - Release the IPQ PCS MII instance + * @pcs: PCS instance + * + * Description: Release a phylink PCS instance. + */ +void ipq_pcs_put(struct phylink_pcs *pcs) +{ + struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); + + /* Put reference taken by of_find_device_by_node() in + * ipq_pcs_get(). + */ + put_device(qpcs_mii->qpcs->dev); +} +EXPORT_SYMBOL(ipq_pcs_put); + +/* Parse the PCS MII DT nodes which are child nodes of the PCS node, + * and instantiate each MII PCS instance. + */ +static int ipq_pcs_create_miis(struct ipq_pcs *qpcs) +{ + struct device *dev = qpcs->dev; + struct ipq_pcs_mii *qpcs_mii; + struct device_node *mii_np; + u32 index; + int ret; + + for_each_available_child_of_node(dev->of_node, mii_np) { + ret = of_property_read_u32(mii_np, "reg", &index); + if (ret) { + dev_err(dev, "Failed to read MII index\n"); + of_node_put(mii_np); + return ret; + } + + if (index >= PCS_MAX_MII_NRS) { + dev_err(dev, "Invalid MII index\n"); + of_node_put(mii_np); + return -EINVAL; + } + + qpcs_mii = devm_kzalloc(dev, sizeof(*qpcs_mii), GFP_KERNEL); + if (!qpcs_mii) { + of_node_put(mii_np); + return -ENOMEM; + } + + qpcs_mii->qpcs = qpcs; + qpcs_mii->index = index; + qpcs_mii->pcs.ops = &ipq_pcs_phylink_ops; + qpcs_mii->pcs.neg_mode = true; + qpcs_mii->pcs.poll = true; + + qpcs_mii->rx_clk = devm_get_clk_from_child(dev, mii_np, "rx"); + if (IS_ERR(qpcs_mii->rx_clk)) { + dev_err(dev, "Failed to get MII %d RX clock\n", index); + of_node_put(mii_np); + return PTR_ERR(qpcs_mii->rx_clk); + } + + qpcs_mii->tx_clk = devm_get_clk_from_child(dev, mii_np, "tx"); + if (IS_ERR(qpcs_mii->tx_clk)) { + dev_err(dev, "Failed to get MII %d TX clock\n", index); + of_node_put(mii_np); + return PTR_ERR(qpcs_mii->tx_clk); + } + + qpcs->qpcs_mii[index] = qpcs_mii; + } + + return 0; +} + static unsigned long ipq_pcs_clk_rate_get(struct ipq_pcs *qpcs) { switch (qpcs->interface) { @@ -219,6 +675,12 @@ static int ipq9574_pcs_probe(struct platform_device *pdev) if (ret) return ret; + ret = ipq_pcs_create_miis(qpcs); + if (ret) + return ret; + + mutex_init(&qpcs->config_lock); + platform_set_drvdata(pdev, qpcs); return 0; diff --git a/include/linux/pcs/pcs-qcom-ipq9574.h b/include/linux/pcs/pcs-qcom-ipq9574.h new file mode 100644 index 000000000000..5469a81b4482 --- /dev/null +++ b/include/linux/pcs/pcs-qcom-ipq9574.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * + */ + +#ifndef __LINUX_PCS_QCOM_IPQ9574_H +#define __LINUX_PCS_QCOM_IPQ9574_H + +struct device_node; +struct phylink_pcs; + +struct phylink_pcs *ipq_pcs_get(struct device_node *np); +void ipq_pcs_put(struct phylink_pcs *pcs); + +#endif /* __LINUX_PCS_QCOM_IPQ9574_H */ From patchwork Wed Dec 4 14:43:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 13893895 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 397EB20CCE3; Wed, 4 Dec 2024 14:53:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733324004; cv=none; b=jw2xn+ZQvvx2Nrq8xY8g+WlO9/kZHuzv2fIgLu32k7SEkygzufMcaIcdcb0xAtsSonJIW/Gh4kTPFm1OQrRDI34Xr9oEhGNvKo0aGUr4XwB+z7MA/tarMqudWuD4tmV7QISgXMptD1+vlGgudh+8KrxdJRq+gAhITbTHYxhPfqg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733324004; c=relaxed/simple; bh=PcwhxhxpzymGc5PEGoKTVEJ3RohYhfCjdnNuo6RNtJw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=JHySxA3J2jXYfgW4XvnRH3NEcFK3K6W6wh/EWTSfmqIC/gq5D4iKXyqntHEiGU2O+5Fn3+eHmaXMlSlCx7KTpuBI7XW0BrbSrfRzqh/ffz/AxxBBUCF4kgzBMhGi/R6XIlKc2IWJ/8g3K1bRYUXHqCfqKrzlZ1X/03Sk+PqxQ6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=j9BFqMdC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="j9BFqMdC" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B4CjTrN027143; Wed, 4 Dec 2024 14:53:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= o9Dd1F3RUOKl+Bh7LF6T7f8wWWFAJ1BzR8qSP5H+tkU=; b=j9BFqMdCVZdhUFn+ Qdk5njkw+h7X1uzq8aB5JonSGtAcqvhpDa023jN56bW1/ym/h9os0CdXAYIsp2CX Cc6yATPYCH/D5r3LodEhY1V28CWu2b4ieyjbyC/VPnNMntxQsE2ZkpEu41VhCIDj 5nHNGfJ0OhgzgN9nqBFlUPi94zXWYjNd5Ju3nomxflgam5LNskseEaONcpUJ4iM1 /K1YvSx3RfqHH0qLm8+V7qaTp0UquBd4hIYvXQ3yjM1gvux/CSLqCD9MY/fqmiDJ hT0Hu6ZnlySoA/GFxFSZjuo6gNJQD1TdIEFfVLpw5QT76Ntsnkw8y5QII89CfZfA 06ASew== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43a1g5krf6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 14:53:07 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4Er6gw031658 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 14:53:06 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 06:53:01 -0800 From: Lei Wei Date: Wed, 4 Dec 2024 22:43:56 +0800 Subject: [PATCH net-next v2 4/5] net: pcs: qcom-ipq9574: Add USXGMII interface mode support Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-ipq_pcs_rc1-v2-4-26155f5364a1@quicinc.com> References: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> In-Reply-To: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733323958; l=7396; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=PcwhxhxpzymGc5PEGoKTVEJ3RohYhfCjdnNuo6RNtJw=; b=fYXZCq15Z9PJMa7wBGRIp6HLhk+sOb/0VjCQowcPXQJsb9OTpE6tYEHGKmkF8GyV3fz6iK7m5 rcTc2RRbaqPDuWdpmZspbtfpNH8DA2romOEDcqYm6AbPe2aAJ12jeBQ X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: hunt9awkvORd45ul8dT1z00WpaKAe8GF X-Proofpoint-ORIG-GUID: hunt9awkvORd45ul8dT1z00WpaKAe8GF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040114 USXGMII mode is enabled by PCS when 10Gbps PHYs are connected, such as Aquantia 10Gbps PHY. Signed-off-by: Lei Wei --- drivers/net/pcs/pcs-qcom-ipq9574.c | 177 +++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/drivers/net/pcs/pcs-qcom-ipq9574.c b/drivers/net/pcs/pcs-qcom-ipq9574.c index 3608f5506477..ad5e9551675a 100644 --- a/drivers/net/pcs/pcs-qcom-ipq9574.c +++ b/drivers/net/pcs/pcs-qcom-ipq9574.c @@ -26,6 +26,7 @@ #define PCS_MODE_SEL_MASK GENMASK(12, 8) #define PCS_MODE_SGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x4) #define PCS_MODE_QSGMII FIELD_PREP(PCS_MODE_SEL_MASK, 0x1) +#define PCS_MODE_XPCS FIELD_PREP(PCS_MODE_SEL_MASK, 0x10) #define PCS_MII_CTRL(x) (0x480 + 0x18 * (x)) #define PCS_MII_ADPT_RESET BIT(11) @@ -54,6 +55,35 @@ FIELD_PREP(GENMASK(9, 2), \ FIELD_GET(XPCS_INDIRECT_ADDR_L, reg))) +#define XPCS_DIG_CTRL 0x38000 +#define XPCS_USXG_ADPT_RESET BIT(10) +#define XPCS_USXG_EN BIT(9) + +#define XPCS_MII_CTRL 0x1f0000 +#define XPCS_MII_AN_EN BIT(12) +#define XPCS_DUPLEX_FULL BIT(8) +#define XPCS_SPEED_MASK (BIT(13) | BIT(6) | BIT(5)) +#define XPCS_SPEED_10000 (BIT(13) | BIT(6)) +#define XPCS_SPEED_5000 (BIT(13) | BIT(5)) +#define XPCS_SPEED_2500 BIT(5) +#define XPCS_SPEED_1000 BIT(6) +#define XPCS_SPEED_100 BIT(13) +#define XPCS_SPEED_10 0 + +#define XPCS_MII_AN_CTRL 0x1f8001 +#define XPCS_MII_AN_8BIT BIT(8) + +#define XPCS_MII_AN_INTR_STS 0x1f8002 +#define XPCS_USXG_AN_LINK_STS BIT(14) +#define XPCS_USXG_AN_DUPLEX_FULL BIT(13) +#define XPCS_USXG_AN_SPEED_MASK GENMASK(12, 10) +#define XPCS_USXG_AN_SPEED_10 0 +#define XPCS_USXG_AN_SPEED_100 1 +#define XPCS_USXG_AN_SPEED_1000 2 +#define XPCS_USXG_AN_SPEED_2500 4 +#define XPCS_USXG_AN_SPEED_5000 5 +#define XPCS_USXG_AN_SPEED_10000 3 + /* Per PCS MII private data */ struct ipq_pcs_mii { struct ipq_pcs *qpcs; @@ -126,9 +156,57 @@ static void ipq_pcs_get_state_sgmii(struct ipq_pcs *qpcs, state->duplex = DUPLEX_HALF; } +static void ipq_pcs_get_state_usxgmii(struct ipq_pcs *qpcs, + struct phylink_link_state *state) +{ + unsigned int val; + int ret; + + ret = regmap_read(qpcs->regmap, XPCS_MII_AN_INTR_STS, &val); + if (ret) { + state->link = 0; + return; + } + + state->link = !!(val & XPCS_USXG_AN_LINK_STS); + + if (!state->link) + return; + + switch (FIELD_GET(XPCS_USXG_AN_SPEED_MASK, val)) { + case XPCS_USXG_AN_SPEED_10000: + state->speed = SPEED_10000; + break; + case XPCS_USXG_AN_SPEED_5000: + state->speed = SPEED_5000; + break; + case XPCS_USXG_AN_SPEED_2500: + state->speed = SPEED_2500; + break; + case XPCS_USXG_AN_SPEED_1000: + state->speed = SPEED_1000; + break; + case XPCS_USXG_AN_SPEED_100: + state->speed = SPEED_100; + break; + case XPCS_USXG_AN_SPEED_10: + state->speed = SPEED_10; + break; + default: + state->link = false; + return; + } + + if (val & XPCS_USXG_AN_DUPLEX_FULL) + state->duplex = DUPLEX_FULL; + else + state->duplex = DUPLEX_HALF; +} + static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, phy_interface_t interface) { + unsigned long rate = 125000000; unsigned int val; int ret; @@ -140,6 +218,10 @@ static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, case PHY_INTERFACE_MODE_QSGMII: val = PCS_MODE_QSGMII; break; + case PHY_INTERFACE_MODE_USXGMII: + val = PCS_MODE_XPCS; + rate = 312500000; + break; default: dev_err(qpcs->dev, "Unsupported interface %s\n", phy_modes(interface)); @@ -174,6 +256,21 @@ static int ipq_pcs_config_mode(struct ipq_pcs *qpcs, qpcs->interface = interface; + /* Configure the RX and TX clock to NSSCC as 125M or 312.5M based + * on current interface mode. + */ + ret = clk_set_rate(qpcs->rx_hw.clk, rate); + if (ret) { + dev_err(qpcs->dev, "Failed to set RX clock rate\n"); + return ret; + } + + ret = clk_set_rate(qpcs->tx_hw.clk, rate); + if (ret) { + dev_err(qpcs->dev, "Failed to set TX clock rate\n"); + return ret; + } + return 0; } @@ -211,6 +308,35 @@ static int ipq_pcs_config_sgmii(struct ipq_pcs *qpcs, PCS_MII_FORCE_MODE, PCS_MII_FORCE_MODE); } +static int ipq_pcs_config_usxgmii(struct ipq_pcs *qpcs) +{ + int ret; + + /* Configure the XPCS for USXGMII mode if required */ + if (qpcs->interface != PHY_INTERFACE_MODE_USXGMII) { + ret = ipq_pcs_config_mode(qpcs, PHY_INTERFACE_MODE_USXGMII); + if (ret) + return ret; + + ret = regmap_update_bits(qpcs->regmap, XPCS_DIG_CTRL, + XPCS_USXG_EN, XPCS_USXG_EN); + if (ret) + return ret; + + ret = regmap_update_bits(qpcs->regmap, XPCS_MII_AN_CTRL, + XPCS_MII_AN_8BIT, XPCS_MII_AN_8BIT); + if (ret) + return ret; + + ret = regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, + XPCS_MII_AN_EN, XPCS_MII_AN_EN); + if (ret) + return ret; + } + + return 0; +} + static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, int index, unsigned int neg_mode, @@ -253,6 +379,49 @@ static int ipq_pcs_link_up_config_sgmii(struct ipq_pcs *qpcs, PCS_MII_ADPT_RESET, PCS_MII_ADPT_RESET); } +static int ipq_pcs_link_up_config_usxgmii(struct ipq_pcs *qpcs, int speed) +{ + unsigned int val; + int ret; + + switch (speed) { + case SPEED_10000: + val = XPCS_SPEED_10000; + break; + case SPEED_5000: + val = XPCS_SPEED_5000; + break; + case SPEED_2500: + val = XPCS_SPEED_2500; + break; + case SPEED_1000: + val = XPCS_SPEED_1000; + break; + case SPEED_100: + val = XPCS_SPEED_100; + break; + case SPEED_10: + val = XPCS_SPEED_10; + break; + default: + dev_err(qpcs->dev, "Invalid USXGMII speed %d\n", speed); + return -EINVAL; + } + + /* USXGMII only support full duplex mode */ + val |= XPCS_DUPLEX_FULL; + + /* Configure XPCS speed */ + ret = regmap_update_bits(qpcs->regmap, XPCS_MII_CTRL, + XPCS_SPEED_MASK | XPCS_DUPLEX_FULL, val); + if (ret) + return ret; + + /* XPCS adapter reset */ + return regmap_update_bits(qpcs->regmap, XPCS_DIG_CTRL, + XPCS_USXG_ADPT_RESET, XPCS_USXG_ADPT_RESET); +} + static int ipq_pcs_enable(struct phylink_pcs *pcs) { struct ipq_pcs_mii *qpcs_mii = phylink_pcs_to_qpcs_mii(pcs); @@ -299,6 +468,9 @@ static void ipq_pcs_get_state(struct phylink_pcs *pcs, case PHY_INTERFACE_MODE_QSGMII: ipq_pcs_get_state_sgmii(qpcs, index, state); break; + case PHY_INTERFACE_MODE_USXGMII: + ipq_pcs_get_state_usxgmii(qpcs, state); + break; default: break; } @@ -325,6 +497,8 @@ static int ipq_pcs_config(struct phylink_pcs *pcs, case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: return ipq_pcs_config_sgmii(qpcs, index, neg_mode, interface); + case PHY_INTERFACE_MODE_USXGMII: + return ipq_pcs_config_usxgmii(qpcs); default: dev_err(qpcs->dev, "Unsupported interface %s\n", phy_modes(interface)); @@ -348,6 +522,9 @@ static void ipq_pcs_link_up(struct phylink_pcs *pcs, ret = ipq_pcs_link_up_config_sgmii(qpcs, index, neg_mode, speed); break; + case PHY_INTERFACE_MODE_USXGMII: + ret = ipq_pcs_link_up_config_usxgmii(qpcs, speed); + break; default: dev_err(qpcs->dev, "Unsupported interface %s\n", phy_modes(interface)); From patchwork Wed Dec 4 14:43:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lei Wei X-Patchwork-Id: 13893896 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36A3A20ADF2; Wed, 4 Dec 2024 14:53:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733324022; cv=none; b=fbWPOjHMZV2+sqaTRu8cUCcjKMDvVx4RcMYW71H8oQZrUXhh+Zp3RiygZJ1Vhwsx8caJIBDoToanuI8zO2jbIwYgcggvI58e4ScE8rR/TVvm14K6lNHbddvCxOEOryoDyxQ19MP1TFxaeo50cx+Z35aY2L4TCWXvSlnak2w20XY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733324022; c=relaxed/simple; bh=+s1Akq84IIyT8pCTQiEDo6Zt/nb8OW5mR9Yly7SUG9E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nVHWO7C/hnl7H4I3Ia/kwH9YTBU2XNCqBv5HrHtnqxxJRcyKOtlKpm9D13egADTSLSoE4qpBZSLhquZTZWzVOU+GvgVPPrvBQeyL+n27DqnG9HHvl4jLAWJHARpSmmYD6WY5Ah9FLLg3kUZOFwDTeK7OvkfjswYX5yFvAQkxyIM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=kzvavOIH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="kzvavOIH" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4B46kg8i023340; Wed, 4 Dec 2024 14:53:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= drtWFiFON4ugZEisuLBAAdelrnN5zG/TKJ/SOlfxmBU=; b=kzvavOIHoE4mzbHc DXfXYwBfJA3COVAMrVF7Wd4o8FqJdfmal1FzKY91z2Tl0Pd04PIIQSUSlyV2pdPi 8RnbWCTGOxsKa0K+dzdlI10KDzsCZMQ/W7dPwwPWBmFmeODXWHJ3LHxyy4nIVtQd 0d0kegbC5DP8rf4udn0rORwq2WTvfj+yPwMRX54sp6MyEEcl8z8kte7Nzpn46NyL MHgDddWp2na0phwCqy5zCHrMgy0/dT+RAUrEBz7iBab/VWKrig+9NmuMY3j5CmV4 syp1Oem279wu0vWGNpa/Miq8o3Knh4d7NbV6a3t6zhiPfdzhK4ZBTyqpugxKIByq B+fXEw== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43aj4298gj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Dec 2024 14:53:27 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B4ErQF0022114 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 4 Dec 2024 14:53:26 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 4 Dec 2024 06:53:06 -0800 From: Lei Wei Date: Wed, 4 Dec 2024 22:43:57 +0800 Subject: [PATCH net-next v2 5/5] MAINTAINERS: Add maintainer for Qualcomm IPQ9574 PCS driver Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241204-ipq_pcs_rc1-v2-5-26155f5364a1@quicinc.com> References: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> In-Reply-To: <20241204-ipq_pcs_rc1-v2-0-26155f5364a1@quicinc.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , Heiner Kallweit , Russell King CC: , , , , , , , , , , , , , X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733323958; l=960; i=quic_leiwei@quicinc.com; s=20240829; h=from:subject:message-id; bh=+s1Akq84IIyT8pCTQiEDo6Zt/nb8OW5mR9Yly7SUG9E=; b=7YteXcZv/ctSOIsE3AdT1lqxh+/M/SxN8cIw2hfMO1otCAm3vzx/JmIYsyKecS0i7fBqq1kSx wHDb6e7i2UfCTH66c6Zs6oSWX+4IZID1sJMsagrmEn5pAMT+WmfBjVC X-Developer-Key: i=quic_leiwei@quicinc.com; a=ed25519; pk=uFXBHtxtDjtIrTKpDEZlMLSn1i/sonZepYO8yioKACM= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Z_nexa7FyoPQDzAXntihMYC8E41nBBV3 X-Proofpoint-ORIG-GUID: Z_nexa7FyoPQDzAXntihMYC8E41nBBV3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 mlxscore=0 mlxlogscore=828 lowpriorityscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412040114 Add maintainer for the Ethernet PCS driver supported for Qualcomm IPQ9574 SoC. Signed-off-by: Lei Wei --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c27f3190737f..c76348387326 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19164,6 +19164,15 @@ S: Maintained F: Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml F: drivers/regulator/vqmmc-ipq4019-regulator.c +QUALCOMM IPQ9574 Ethernet PCS DRIVER +M: Lei Wei +L: netdev@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/net/pcs/qcom,ipq9574-pcs.yaml +F: drivers/net/pcs/pcs-qcom-ipq9574.c +F: include/dt-bindings/net/qcom,ipq9574-pcs.h +F: include/linux/pcs/pcs-qcom-ipq9574.h + QUALCOMM NAND CONTROLLER DRIVER M: Manivannan Sadhasivam L: linux-mtd@lists.infradead.org