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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 01/15] cpufreq/amd-pstate: Add trace event for EPP perf updates Date: Thu, 5 Dec 2024 16:28:33 -0600 Message-ID: <20241205222847.7889-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|PH7PR12MB6761:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fa1b303-8fbc-4472-73f7-08dd157c397a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: Tpazii3HfjdNUEsopnI7wb0CRKokURu7QEprF5Z38Ev4iT4+sXDPLaft9MRA0db8Iut7WrBat1pNzQP41xnSiCpSD8DRR0A9dOHG/hvapbK49EvUhytjM9hkFgat2CN5PO6hCPZPUQ99y4GHeXbqmJFY3LgtaIj5H0Kwiuu7zfKbEQjXUIbnn4BeRdUWwx40k9aAl5xBcL7ffWIQp1Cf5AZ+SyUn8ZeTOiucw/7pp2MjOxpLK/Iz5ikrIag1FQmOMhVJd5ELx2gMsoWT7gzVQfNZvXcoyZnghIPsDw0pM/vJKa7MlMdo68VLhCpqL2fMpPDgSfvtwv4mEtMfdruDIA90l4cUxvgWpkbptN56U+gEC85c+Zbh0Ex8uJDSxzrxzE2x3K/xc+lhsE+WS0f5lzWFz2OsRVcWKwreHaOYpO6dBcO46havZdhrFdWeRWhRhRp47f+jncu1kT8yC4bEJrXPRMbPDnbkli6gSf4Bkmy43MnuYaEBZz58uIU5AKOmk5mj6dty2O89ci6G1JaSaQ3KLhwAYZaiLPhxYDAiJVfSxAzEU1RuSPWwWlrXMXaur+pNZ6zrVFJs3JdLuwkx6qCmAl/q75BEG/n8UzK+cfzHNEAYCVaA7Co8omKkd2tz6XBQgY7GvFix1aCxOiPk91lO9dxB6SHWxM4XTUl6j5fG6Ao0+MPAOjC35XF1WfRCx3YL5afs8xii9tb9Pnju1Jf+oCYbica5EtV7BewoHf2th+q1MEG56fNQeIqgDDlz/us6feLTSAYkSX1mNJ4ilSH2XytYwAn5yB/jIlhRvNPbdh5Qj2OB1XyBx64vjSOC60OrXrxI6lOK45WWDiCQXMphLLN77PQYjScwYWWMsyWPU7EhAKjSrZseuIF1h4ZZKD/1pLcSVj58IGgTpVGifFlZNBcfflAKsrnV41cZ6hMzxeI7yqm/sDXkLUrQ2GFYkCpfnKbZZz1/F5QSoM1aLpUv/VlrD6vWTkPt8ga0o7oZtbDcNjrfRa9H45Zom6pR1HML4LE27vzBWhUzZrrLCWFWRSFk++6HvybhIJeSEoX2AjfIGZUnA2k+a0kTl9J0X2qnRjQiis2SpG24X/m+SDW9A8+lMlJi2APc9MdsVBK6HZGfIKbzRHBwY66JAmRuMNX9b1b7asHsLChPj83OGMXhD4ECoZxXulELO3aY/IU2Bh4gev99nXCu2Kjp8zci8Tcq0UYwzxVJ5dNAWZSBwlQJ2B69iFUB2saRxYKm0G/NnW2YLmNvoBsS8+VcI4Z3dg51120lcP6RPjgjKxiv3wnLcmzJClXKEvtPTmd3QYivnKKYOTNbQfb+jna1tsMZgOXpTOhFqzf3M0jp+uq9TFeIx47y96v27MMGEngRt85boMSGohjCAcSwbagp1/yCf8FdpFRdFNjc2QwuNDTZQYIpfYjaaWClkQqKvC57A0Jwj0ljHKSv7x6GwFXkuDHl X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:04.0151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fa1b303-8fbc-4472-73f7-08dd157c397a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6761 In "active" mode the most important thing for debugging whether an issue is hardware or software based is to look at what was the last thing written to the CPPC request MSR or shared memory region. The 'amd_pstate_epp_perf' trace event shows the values being written for all CPUs. Signed-off-by: Mario Limonciello Reviewed-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate-trace.h | 45 ++++++++++++++++++++++++++++++ drivers/cpufreq/amd-pstate.c | 28 +++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstate-trace.h index 35f38ae67fb13..e2221a4b6901c 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -88,6 +88,51 @@ TRACE_EVENT(amd_pstate_perf, ) ); +TRACE_EVENT(amd_pstate_epp_perf, + + TP_PROTO(unsigned int cpu_id, + unsigned int highest_perf, + unsigned int epp, + unsigned int min_perf, + unsigned int max_perf, + bool boost + ), + + TP_ARGS(cpu_id, + highest_perf, + epp, + min_perf, + max_perf, + boost), + + TP_STRUCT__entry( + __field(unsigned int, cpu_id) + __field(unsigned int, highest_perf) + __field(unsigned int, epp) + __field(unsigned int, min_perf) + __field(unsigned int, max_perf) + __field(bool, boost) + ), + + TP_fast_assign( + __entry->cpu_id = cpu_id; + __entry->highest_perf = highest_perf; + __entry->epp = epp; + __entry->min_perf = min_perf; + __entry->max_perf = max_perf; + __entry->boost = boost; + ), + + TP_printk("cpu%u: [%u<->%u]/%u, epp=%u, boost=%u", + (unsigned int)__entry->cpu_id, + (unsigned int)__entry->min_perf, + (unsigned int)__entry->max_perf, + (unsigned int)__entry->highest_perf, + (unsigned int)__entry->epp, + (bool)__entry->boost + ) +); + #endif /* _AMD_PSTATE_TRACE_H */ /* This part must be outside protection */ diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 66fb7aee95d24..4d1da49d345ec 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -324,6 +324,14 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, return -EBUSY; } + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + epp, + AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + AMD_CPPC_MAX_PERF(cpudata->cppc_req_cached), + cpudata->boost_state); + } + ret = amd_pstate_set_epp(cpudata, epp); return ret; @@ -1596,6 +1604,13 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) WRITE_ONCE(cpudata->cppc_req_cached, value); + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, + cpudata->min_limit_perf, + cpudata->max_limit_perf, + cpudata->boost_state); + } + amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, cpudata->max_limit_perf, false); @@ -1639,6 +1654,13 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) max_perf = READ_ONCE(cpudata->highest_perf); + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + cpudata->epp_cached, + AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached), + max_perf, cpudata->boost_state); + } + amd_pstate_update_perf(cpudata, 0, 0, max_perf, false); amd_pstate_set_epp(cpudata, cpudata->epp_cached); } @@ -1667,6 +1689,12 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) mutex_lock(&amd_pstate_limits_lock); + if (trace_amd_pstate_epp_perf_enabled()) { + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + AMD_CPPC_EPP_BALANCE_POWERSAVE, + min_perf, min_perf, cpudata->boost_state); + } + amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false); amd_pstate_set_epp(cpudata, AMD_CPPC_EPP_BALANCE_POWERSAVE); From patchwork Thu Dec 5 22:28:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13896069 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2053.outbound.protection.outlook.com [40.107.243.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 196AA1CDA19; Thu, 5 Dec 2024 22:29:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 02/15] cpufreq/amd-pstate: convert mutex use to guard() Date: Thu, 5 Dec 2024 16:28:34 -0600 Message-ID: <20241205222847.7889-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|SA1PR12MB5638:EE_ X-MS-Office365-Filtering-Correlation-Id: ec594263-3195-4be2-31db-08dd157c3a1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: od8+MEOanL0/7hHi0HU8lmIlqbiteAgQRTAoZyc5lLoRBDR8vkMZ2A2zYqaTtmF3UIRGOFyickk4IgnNEH8qWFfX4XL3tnPUvGkNaBcujn35xzL5p4iPHOPfW5I91uLByQOVY+mJ9ao//uFHACiUqZD0B05aEoW1q2OduM5un0DLlWWl1VhALnxEkWyqllU4zmV3N/2UxMQ+fufJNVe3h2eY7ZX/5BQpPROEDEUsvh1jbWGVWISleZwJqXEpML+1QDP90bXFFMjdfaQa6WmLxnqRBv03cYjhG0o/rb04JfqJKkY7h1x04dRY79oXydMdOvbpSIwrY6qdYcLAuTc2ndzKw61vWn7OkJtsIzt7j9wnt7NVpWcQWmRw6slcBOb2fWdzsNgU1SGKNbBcAtbV3PO8oCuKGkP2Q4VNMpPnpuDZQtZsT3MsU4uH/13ieut5MD/Krwcftib+5tpVcsG9ohGXgrLrA+D+YyD3Ok4KoUpUJ6MZzxYQ62WV8Bd4gT74xZJTSkGD05j2+GJq/2HiWDWOJeTMGQAjrU2Gy5vTNGPJIRf7G0X0XnM6LaLApBC6vfZNUQthrQ2f4Ae5TilEZMMC7yoo/eWmp8u7aKjOQzbeXXf+BekvbwXE/oFa64tEbdPKypFhMbDh4l5sZ/owYCbRlmvr79zCIlGf5Kb/YoAhMpnBIsNlSYQYVJDOUkmV6hrlciLm6Gz9FSvdyex0njRwTi+vHZ2x49MB8ZvUv15i+rw8qrN68FLUJGSLQx2Mpiqa+Egrwsr7X/FOw2v9m3HeJszu7LEYbLs2F6CCjRX/MjBcI3QOWFksP/gL9zg8A5xWLG7KhNVb3oLMY+gULkqcrWgQ/W3ndwzSBSan6RkEvG/TrTCeI5EwsMue/PWWmh9Ztaw4blIXn5L8zGW7FeDK3C9HQze5VpTri0E2x0iBTfOZ2+vIz6W6p4O5L3r3Po8KdqSxzKIRtan91PVfBlcS6T5tdjB20TqEDuAHC53l5QnoCP7ugU4EqTqV7mNmjBDF4qqirtHLy1RU/CRYrIUzOPe6zgwQYPycv7xcwMCfzDNNi3GVHWwirMqxIOtq41RweuyIuKZNy1pf5s2e+Xm9FXj2lr/YiWVMfSh114yaRTCUHMiiHhx9IREoEBTjUP2JyhSPik2FkHexq/nGnbRHcBBvbj5fQ0XurDo/QNY+alddJK8tTBvJkCdPIWTeqekSO80QNeoN+uYyFqO2OKseO5jTX2dZUJ/FlL2Rkm4PXICW31GoSbO7r5Zdkdi3ACtzrexkq1H6puT+55u0yTJ1RNqyyI1wXCMa/+bxZ7EoT14+EVlYknGSVzTLyJst4J0D264oIDdVzdLMyrn7aurhVizTl4t7XZ6aECzDpbEzIqmCUj8KInsqdOFk5Q00yeFi6jEhPd4o/sREv3YchpkuXrlamAPLBAhxdwzjB7EAp+XbNyJArnt5opseU11X X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:04.9995 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec594263-3195-4be2-31db-08dd157c3a1a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5638 Using scoped guard declaration will unlock mutexes automatically. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 4d1da49d345ec..7eb013585df51 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -752,12 +752,12 @@ static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) pr_err("Boost mode is not supported by this processor or SBIOS\n"); return -EOPNOTSUPP; } - mutex_lock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); + ret = amd_pstate_cpu_boost_update(policy, state); WRITE_ONCE(cpudata->boost_state, !ret ? state : false); policy->boost_enabled = !ret ? state : false; refresh_frequency_limits(policy); - mutex_unlock(&amd_pstate_driver_lock); return ret; } @@ -848,7 +848,8 @@ static void amd_pstate_update_limits(unsigned int cpu) if (!amd_pstate_prefcore) return; - mutex_lock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); + ret = amd_get_highest_perf(cpu, &cur_high); if (ret) goto free_cpufreq_put; @@ -868,7 +869,6 @@ static void amd_pstate_update_limits(unsigned int cpu) if (!highest_perf_changed) cpufreq_update_policy(cpu); - mutex_unlock(&amd_pstate_driver_lock); } /* @@ -1201,11 +1201,11 @@ static ssize_t store_energy_performance_preference( if (ret < 0) return -EINVAL; - mutex_lock(&amd_pstate_limits_lock); + guard(mutex)(&amd_pstate_limits_lock); + ret = amd_pstate_set_energy_pref_index(cpudata, ret); - mutex_unlock(&amd_pstate_limits_lock); - return ret ?: count; + return ret ? ret : count; } static ssize_t show_energy_performance_preference( @@ -1369,13 +1369,10 @@ EXPORT_SYMBOL_GPL(amd_pstate_update_status); static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { - ssize_t ret; - mutex_lock(&amd_pstate_driver_lock); - ret = amd_pstate_show_status(buf); - mutex_unlock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); - return ret; + return amd_pstate_show_status(buf); } static ssize_t status_store(struct device *a, struct device_attribute *b, @@ -1384,9 +1381,8 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, char *p = memchr(buf, '\n', count); int ret; - mutex_lock(&amd_pstate_driver_lock); + guard(mutex)(&amd_pstate_driver_lock); ret = amd_pstate_update_status(buf, p ? p - buf : count); - mutex_unlock(&amd_pstate_driver_lock); return ret < 0 ? ret : count; } @@ -1687,7 +1683,7 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) min_perf = READ_ONCE(cpudata->lowest_perf); - mutex_lock(&amd_pstate_limits_lock); + guard(mutex)(&amd_pstate_limits_lock); if (trace_amd_pstate_epp_perf_enabled()) { trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, @@ -1698,8 +1694,6 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false); amd_pstate_set_epp(cpudata, AMD_CPPC_EPP_BALANCE_POWERSAVE); - mutex_unlock(&amd_pstate_limits_lock); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 03/15] cpufreq/amd-pstate: Drop cached epp_policy variable Date: Thu, 5 Dec 2024 16:28:35 -0600 Message-ID: <20241205222847.7889-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|CH2PR12MB4246:EE_ X-MS-Office365-Filtering-Correlation-Id: 247e63f5-9df5-4658-0229-08dd157c3acd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: HHcHo2ruwoiO417fRwc/JtQg1NxTn2WKjvobDg0TVHCzQF6tRSgDpFSzZJKswiXWwcSmn6yn1u6SF1WfYZT1+IqE1+S8qGVWSdn+VClW4ybTjO7ku4SdAEK8sU+uvOUQ7jJYPTrN6x04GfhtIGFVYma/eoFhZ4tCsWYTf0twNezBIJ4fAJchgvVFoShQnmDbny+uis/IT2+8SQ+wzi82RVc7yZDKmKBzUbEdV3DgPlfp5fRjl7MUSqTuGeB4RjObn1D6PbbuZs/XWBEAxreKHYAXal5UEmGd4cPxRWmM/h3R5S3EE6aVmi/2Yt8fabfDWZBue2siKt/ub5cl5V1kojtSFhnEWczIlrGS0tGiDnEut7C59twAgsYIL4Gdpi1dsTqoEkN40Esr8GjDSwX3pR2tbJo1N7h4qKsxLsmsZRpIxtWEsZ8YG2qfxH37eQylue8vGE9wC4eTcOq+yEr+en275CFwpN7kkpvEQpB2O1WCrq6dsg6qZPoAINZpHiMO7Q/XfDt3JcYOS5ohHxB0bEXWTocoZzAkPkv3gGpWG0shYFZXUKS7iVmYVMXxx09S1+VOzS/kLYWt15Spx1hibJb2WOg3qNCRx6fxhaAT6Wqp/W2als39t1Yr8KnV9lVavVJp2/O9ZoSl/KbUaw1pk4EAXPh8owsXYkKxM2sj5e4z/u2sIhQwe9x6fwMwolJg8hlBsMsJmmNc+VQ2e9sfkqfTz8/EDg2vlli/APZ9lgdFtv+4Ju05lIEQlZqBaEEUp3hHS9mqaPmFcw6SP8ZhQ/JdRQeGOSYsW5P1+mjik/c5a8MrI/v2zyzzGK2PT22CDEevMIx3vYz3I+q8sKzhAAgRz8UfRU3oJW2l39+gVI+JgGDjAOfNQKcyoZIYDeQhROtA6YVkUtzZ5iYo05xSMHtJM1KTDie8hpI4Fin9eLBuj1uVwWLRxbGuIlKsgxC1rsjJgUqCqvHAlOEysgadzwjr+GhdxYZ0zIBNU1QaQivR81IpJDYUu+p+Ehvm4srhmsx/d6z6NqzpV8mzYreqCvBc6ZFGRCrCgg5rGmaMhNtb4oLs0ei/cEezdVDQnvdpu3Elry3wAxk4efRexKRCLg2Jm9CX1BSo/CjfAqX/MLUemvkXbXhugdzGi0N/Lm1AhnWsB2beq62XcWQCppDC/IeOfysUUw/xifR4CCSirB6F/iUlw9PFb+dtzN1EBhkEku2O9fVXYfW8K7l78SH7eZx8SaPu5+nCKL0If1OEf6Tqq9+jf4yXR/IwxCmVRWn7A6lpOyyvTu1lT1hBLhmuSqzhFDYaKAkw6hl7RW+cjoz5stwy3vp0baCqssPhJ+PyCbg2i9QYLavaRuu1EqYqGIpmI7202Ub+so3+J9ZKfSpTMpsL4PVzmX0SVWjH4SPpX5B3z9cEyi4URyCwO8zHSPWaLH32jW5jgiDQRDXvK6hC05gW8erYCbLDWqu/CGdv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:06.2339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 247e63f5-9df5-4658-0229-08dd157c3acd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4246 epp_policy is not used by any of the current code and there is no need to cache it. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 3 --- drivers/cpufreq/amd-pstate.h | 2 -- 2 files changed, 5 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 7eb013585df51..22e212ca514c5 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1476,7 +1476,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return -ENOMEM; cpudata->cpu = policy->cpu; - cpudata->epp_policy = 0; ret = amd_pstate_init_perf(cpudata); if (ret) @@ -1583,8 +1582,6 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(0); - cpudata->epp_policy = cpudata->policy; - /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value); if (epp < 0) { diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index cd573bc6b6db8..7765c82f975c6 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -57,7 +57,6 @@ struct amd_aperf_mperf { * @hw_prefcore: check whether HW supports preferred core featue. * Only when hw_prefcore and early prefcore param are true, * AMD P-State driver supports preferred core featue. - * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value * @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value @@ -94,7 +93,6 @@ struct amd_cpudata { bool hw_prefcore; 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 04/15] cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros Date: Thu, 5 Dec 2024 16:28:36 -0600 Message-ID: <20241205222847.7889-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|MW3PR12MB4393:EE_ X-MS-Office365-Filtering-Correlation-Id: 6bc67ce3-af97-4d3c-0930-08dd157c3b59 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: pJdR6pJdB7q58pWvn43EjRGdU2+eorzgFvz4ia1IQ2NlkloY1K65sBCpkJ8+CYO2iTEOl0VNwjTNWt9kFFpFyunv0Hyyaq4n0q0zgOb1/d51ikPJlB2W2xlHTA4HHJtkVGF2avUAX7tfWPu//85UA4qPcMRJNb5+60vlAIjYEXJPVG2vyriIqmuvt0il65UmNvmHc9OAsDhk1NzYF14VpsZehZPQFTp02xzAsnFo+VXwEE58dEbSSRqwLeIgQATH405pNNA42sZ1qQvp3vGjhDjAL/gatwXXHBAwEvmfEU6BnNjKFJsz8wLdLa7XdHllzf8fXfpOs/f8Qhr9Qkn0cJy3b2oQ+2OOu2Fcq9pqFaJTnlXzKI3MnTJ9Pi/BxVByJYXOF2Nql8ZImIjHe5hCxKS5/hUorOBpr/JZOEHMPbVHLBdrwFLoxylbEH4ZV6L7ifVK5FrCdcr+fS2nlvRyeelDNiGbuOLj8rfdo/78zPgh4V8lE2JymRolhnKlHXql6szCMv42sheA6P1FhhJWKcRypgX9otKtB+urWcwHyMVfNtum9weP4IVzCdCJBAUEo39LTSDh0gLg6iywHagdlVcPlI1DwwwmlCyoBzu3dKwlJAkbC0VD7WlINY1X+SdpFhg6OJyDRqeH1Y/LlQZ9HXd2q9iF1UvWkC3Oeg4YRRtIVcw4QQJGK4D/U/u3zncL3LeUBiLnZPAHIsixhvafGfUi4oMKuvFTrGCdqjzEpAKQk1kCU6CSLOeSLt4Xsc0/sIj6s6THkLQLu/JDtiO1/3+Fh1W5X6j69MQFKiq3Lb0FXUJOvOsfAuEYto7FrKkQCkLIxzjUdhvnqw8mvTjgwqnA11G+1SDD2o2HJeQGxlpNzySjge9zncmp/N7pDMfE/1YjCknrpzti20Z5Ru0dLPauQFPyJxog8Lt2YFvt9oAFMnvjfUmLfwS2GFM0e9LEJNnyuu4erv+Medf7v7RX2bZLGaKtn4fmbqmAG93HanULJJSZ+9r2JV38T74QgmOW4dmYt/3/lviYWgiBzJLEDcdBeEyif1wdU+/hjDD9ooefZz97pCagVQez8Sz1Mby/WXkTOD69YYnPLH4qp3/sx+UxJEnS0ml2eTCYXG864Vc98vQpd45aFEKQVW1w8obQ/j340gXYoAJRYmZOzEVJk754Ii7VGUu1EJLqtxJjK5leoW07qNlQ1jenJBJ9R1Dyu4Wmz1/TntvbAuu57Kv66EOFwEYbUrUUNerx8K+BJZa1BLjQnUphWgyYkAmfztMThL3u0lGZFSI+b6Sb/g6VbhhWiU/jP561gwMb06EOwml21t8FuHU3rA+4t1rD+22lrv8onC1pnZNag4nDl9s/mos5TdtILlvJImvxbPzi07k5KeTS1Ykxn+Sx8aBjXHED7kYOED4rLmuBviDXhoBMxGb00EmXNGwcb/Gz6u7uZaZrLOidbTjlpnAewDFJhYxs X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:07.1515 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6bc67ce3-af97-4d3c-0930-08dd157c3b59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4393 The FIELD_PREP and FIELD_GET macros improve readability and help to avoid shifting bugs. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 45 ++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 22e212ca514c5..dbe014f3c2beb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -22,6 +22,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -88,6 +89,11 @@ static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +#define AMD_PSTATE_MAX_PERF_MASK GENMASK(7, 0) +#define AMD_PSTATE_MIN_PERF_MASK GENMASK(15, 8) +#define AMD_PSTATE_DES_PERF_MASK GENMASK(23, 16) +#define AMD_PSTATE_EPP_PERF_MASK GENMASK(31, 24) + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -182,7 +188,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lock); static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { - u64 epp; int ret; if (!cppc_req_cached) { @@ -192,9 +197,8 @@ static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) return ret; } } - epp = (cppc_req_cached >> 24) & 0xFF; - return (s16)epp; + return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached); } DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); @@ -269,12 +273,11 @@ static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - int ret; - u64 value = READ_ONCE(cpudata->cppc_req_cached); + int ret; - value &= ~GENMASK_ULL(31, 24); - value |= (u64)epp << 24; + value &= ~AMD_PSTATE_EPP_PERF_MASK; + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); @@ -533,18 +536,15 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, des_perf = 0; } - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(des_perf); - /* limit the max perf when core performance boost feature is disabled */ if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, @@ -1571,16 +1571,11 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) min_perf = min(cpudata->nominal_perf, max_perf); - /* Initial min/max values for CPPC Performance Controls Register */ - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); - - /* CPPC EPP feature require to set zero to the desire perf bit */ - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(0); + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value); From patchwork Thu Dec 5 22:28:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13896073 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2070.outbound.protection.outlook.com [40.107.92.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428CA1DDA0E; Thu, 5 Dec 2024 22:29:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.70 ARC-Seal: i=2; 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 05/15] cpufreq/amd-pstate: Store the boost numerator as highest perf again Date: Thu, 5 Dec 2024 16:28:37 -0600 Message-ID: <20241205222847.7889-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|PH0PR12MB8006:EE_ X-MS-Office365-Filtering-Correlation-Id: a9831660-3f20-449d-6efe-08dd157c3b9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: S0zRdPbm370a1hf+zKmXFQHQD6ZBLuOJZTzV/0QhiRk4KPpCwme9+7jcgqHavGiN8x/YUcd5jp6g9pcFkqEEUE+kqPAfMpHuxoDJi9MeKGmoeDaA3EqwtLMj5djzdX/3kIyNV2bzfS2Lkht8xErwdkQ1Lq7Mk8G9AF9TpmWN+TDuvLFFM+YszXxUjIqbeyQi8e22yP1Ae211UmuBUmnntdIFHs89mTzmFAGJ0hcbvkQ+fz5F+KqPsRF33ECxSwbbHXIuO4EXz7jU3waSYhJ2Ak5fNosBl9XCV85zLaEtvyDecn9Jo43XggJPxa7OurslJ4A2E70jR0Eov3COmeL76UtKUSHj7eCVDxS3Y0zQiHDs99gedFgcrEGvx/To5r98rV9KomSGz1dCybbc874otO48aQeUZu8ey1xeLelJdnyls18eI6LOPD7c/e4n0mtzhIvq9heK3XrP6YVuBUtfjBjPiVHH6Vzjvqg8XeJrICq9Fztk30plCzO7swEGqcWdlmHbf3gOF2GXBAH+T48eU1yRdKDdXU9uuEGle3zHDuCo8vEJ9Bo+4eRcr1GOI84mjMCT0Gugd66Pw9I9pjboo/69KgrcQQdgbZpqYGQ7SR/AGMrQDX2B07vX8zGMNJ0cgVlSXL9IhnSeo+O8fJwKtjltoFueqs4UODxsi4axGfuQMa4JQqPgfDPO3zPINKhrikzG1MqAGcr4FwtoqHJvXinzC7O76XVJzAoyvbNdyXDJYAaWj8SzyEiou/0/sfyFoePsbIqAPzyFamn13qCq2mtY3EMoLrWN0aoyVJWmqrQsXjLablwL0zacficCJMy34pnQ2Vu8TlhoS6yeDMVs4aCnLYyuhI2SmmExemAjVHY/Sqw0SMCRcZkGDq9OxaHDmXfWZGffuvQF88PG/A98LJdTCWyEi5PEZQwxZCw1kHc3/KO/R+5cvx90ORIB/gZa1oVHx7UNWJaXGYH9eKLujkStuCQFyIrGOX4mZ37yftosT5YZwEPmIDLn6C/Br07anajc6piRhQEmzNo81JMtUfLBZ+0fjS/F6O9nro3tBisaRZRWzT0ryhRXAs/MLWRO2X9HXFBKfqCub4biy1e9Hje0vftbrOM6ZU7tVOWCu/kReGhJjQWFcgY2tQO3ZvtIcX9i0TFHDlJ8NCLqIJFA/VihB6ivaGfXZzOK2j2tJ27wiM/1pSt2hvF1qhaf3hI6T7pNeHKU+/M9az/acJMpop1VDXKsPItN1yeuBstteRwBdTLdId/wiJrtr4SGkwgvrW547nmMV9PyN1Gt71DIjifvX49k7t9PRLKU1glyJ1itpGhxlNqa9SNaKeclOx7/XnX0E/dVb1N/lLk/Px08UtCBEi/+9jAMx3a9vlsogNa6V81ldKbWwHfA2SxZl55tHAYoLRG3VzI+CcNZ5pv0N8Eh/1vr/+PrJv8o3dZ7tfLUtVkUn+C9qtqbjbUFD9Nl X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:07.5776 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9831660-3f20-449d-6efe-08dd157c3b9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8006 commit ad4caad58d91d ("cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into amd_get_boost_ratio_numerator()") changed the semantics for highest perf and commit 18d9b52271213 ("cpufreq/amd-pstate: Use nominal perf for limits when boost is disabled") worked around those semantic changes. This however is a confusing result and furthermore makes it awkward to change frequency limits and boost due to the scaling differences. Restore the boost numerator to highest perf again. Suggested-by: Dhananjay Ugwekar Fixes: ad4caad58d91 ("cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into amd_get_boost_ratio_numerator()") Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- Documentation/admin-guide/pm/amd-pstate.rst | 4 +--- drivers/cpufreq/amd-pstate.c | 25 ++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 210a808b74ec2..412423c54f258 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -251,9 +251,7 @@ performance supported in `AMD CPPC Performance Capability `_). In some ASICs, the highest CPPC performance is not the one in the ``_CPC`` table, so we need to expose it to sysfs. If boost is not active, but still supported, this maximum frequency will be larger than the one in -``cpuinfo``. On systems that support preferred core, the driver will have -different values for some cores than others and this will reflect the values -advertised by the platform at bootup. +``cpuinfo``. This attribute is read-only. ``amd_pstate_lowest_nonlinear_freq`` diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index dbe014f3c2beb..738f63d70546f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -408,15 +408,19 @@ static inline int amd_pstate_cppc_enable(bool enable) static int msr_init_perf(struct amd_cpudata *cpudata) { - u64 cap1; + u64 cap1, numerator; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); - WRITE_ONCE(cpudata->max_limit_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, numerator); + WRITE_ONCE(cpudata->max_limit_perf, numerator); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); @@ -428,13 +432,18 @@ static int msr_init_perf(struct amd_cpudata *cpudata) static int shmem_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; + u64 numerator; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); - WRITE_ONCE(cpudata->max_limit_perf, cppc_perf.highest_perf); + ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); + if (ret) + return ret; + + WRITE_ONCE(cpudata->highest_perf, numerator); + WRITE_ONCE(cpudata->max_limit_perf, numerator); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); @@ -920,7 +929,6 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) { int ret; u32 min_freq, max_freq; - u64 numerator; u32 nominal_perf, nominal_freq; u32 lowest_nonlinear_perf, lowest_nonlinear_freq; u32 boost_ratio, lowest_nonlinear_ratio; @@ -942,10 +950,7 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) nominal_perf = READ_ONCE(cpudata->nominal_perf); - ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator); - if (ret) - return ret; - boost_ratio = div_u64(numerator << SCHED_CAPACITY_SHIFT, nominal_perf); + boost_ratio = div_u64(cpudata->highest_perf << SCHED_CAPACITY_SHIFT, nominal_perf); max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000; lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); From patchwork Thu Dec 5 22:28:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13896072 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2071.outbound.protection.outlook.com [40.107.236.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A17931D5149; Thu, 5 Dec 2024 22:29:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.71 ARC-Seal: i=2; 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 06/15] cpufreq/amd-pstate: Use boost numerator for upper bound of frequencies Date: Thu, 5 Dec 2024 16:28:38 -0600 Message-ID: <20241205222847.7889-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|SN7PR12MB7273:EE_ X-MS-Office365-Filtering-Correlation-Id: 1d54f203-3e89-40e7-6594-08dd157c3bd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: If7S57t4QYKUsj79W2Tsbd2jMfXBwkNzBC6ayYzwtITxYW1IyKU1XmbarcWQ68U6l1NG+K0d3Og9MxYJRZAki2+sW8zo0H2jsKK9usLz3n8641KjY5ccgNHz6WIIP0SHgFbeK1ikitmcDjPaQLdVOY/b5IBhiSyCFo6wwfxIVTUJbbTNJ/xdOyvVwCQPNKv5FUGEuqpvxRemWiiqkp/Ne47fxmUrwpgQEMlSbOoZAlgMboQohrBc6nTVTr6KCtDsm6QLELv4AvYB5qKYmnXK+PL+N5bQI2NwXsTQbio3JaAO6toTjav/68f+IlqXk3XTgZjz5qnQN/hP6x2nuV3Hpk/mYIg1xwM8b2TPbmwelqogfkwnI6nR3bXP9OvwR7W9SzX514NWzVa2sgDIBCn9l9F294oDSacAqQ0D8zr46lyb4n68ltKtoGLVcFaOcHctxtj27NIgfYtKt/yLOs2CCBU0cib9oFx6xY/JD3NdT9nEwrqSCB8g5HUMd759MDozjq48FIQRwb6RAq/4TkKdwAsICp+6I2EonxQfPGRTSVs6bw7/Cu7mO1wy7oeGWI3577Wm07V6yRi6HA/B5uW22ITgFV73dsqFjHDKcKcFNXCCWALJeOBLasYR8oVLSVSTLwjTwc8GSCvw1H8kJ929IC4UTVpbXe7R7sNkPxWKh70WC9zblTiv5lr12E0JpSQAAoGg855LF5QvLVykZjJ4KuqR1GQQC/Ul6Wn1zNiCbdUyptRd6dPs3onhVzxQT7DOUZNZSxgzNVAFTvUqi/K8ZiKjUF+HMcRnxunZSGWWHI8Yej2WtjEKXPu88cjfhc+PMCwj0ZOxuvQR/1WiigbJ3WKG9I4frq97Ird/kg15+S2W+H/5veP2TxHgCXrf8nYoQXWQ5Gm3bof0xaWT2iDd/Zao03iq73EJhxU2kaWfToo0FzLIiE9JLK8wbbr/x1I/BiatePAxSwtZMxyD4Pge9DDHMdbW3yXgB0Va93D625PjSzMxVB0HHeIZy6tu61df+r8Vykew10qiGrme1rJCKyO+mEle3BlxuBP4uhoTUqZd+zxIO9o64VlI5Kz3tjT/wwwd/BcoewHPER2ORGZQ4nD/HeXwpykwI8C1FT1bnXLuf3NHQ4KI+N2HD+VcsziJF5zyfyklAmSPtyB85jFQBkqpgw6VIJIJoYPCuhg5B3UJeXJCW9jCHT8u5w/1mNa8elQB7uU8yFPm6qAspbeQm/nD3trcCqeDIPtoekOKI6QYV4B28as/sCNOC7QR8DgGfnnP5dzuV+Jrj7wFJ9r2HNnUf0hcXLoaQTaHgbxEeQyvYJQqEoNca/AJXNwJe8C8VStQd5oia0Ako9xFkAwPj2GWJD9lx21aB5OAsDyuX8zYm1tZpRdHcQkkM2V2/Qfeeo+qBCKw24ZzqLBEA5Aqys2Lw5M6NYudkZOJ3IfMwugVuA8e2XH87f9cz5aB+2Fh X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:07.9641 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1d54f203-3e89-40e7-6594-08dd157c3bd7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7273 commit 18d9b5227121 ("cpufreq/amd-pstate: Use nominal perf for limits when boost is disabled") introduced different semantics for min/max limits based upon whether the user turned off boost from sysfs. This however is not necessary when the highest perf value is the boost numerator. Suggested-by: Dhananjay Ugwekar Fixes: 18d9b5227121 ("cpufreq/amd-pstate: Use nominal perf for limits when boost is disabled") Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 738f63d70546f..14bd6faa3d730 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -601,16 +601,13 @@ static int amd_pstate_verify(struct cpufreq_policy_data *policy_data) static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) { - u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf; + u32 max_limit_perf, min_limit_perf, lowest_perf, max_perf, max_freq; struct amd_cpudata *cpudata = policy->driver_data; - if (cpudata->boost_supported && !policy->boost_enabled) - max_perf = READ_ONCE(cpudata->nominal_perf); - else - max_perf = READ_ONCE(cpudata->highest_perf); - - max_limit_perf = div_u64(policy->max * max_perf, policy->cpuinfo.max_freq); - min_limit_perf = div_u64(policy->min * max_perf, policy->cpuinfo.max_freq); + max_perf = READ_ONCE(cpudata->highest_perf); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 07/15] cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on success Date: Thu, 5 Dec 2024 16:28:39 -0600 Message-ID: <20241205222847.7889-8-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|CY5PR12MB6348:EE_ X-MS-Office365-Filtering-Correlation-Id: af32b759-4cfa-4926-3ca1-08dd157c3c8d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: 6TNHE7GSgPOmKx4bIG0NX8OLAvnXLr9ftkWqGuvgPauJ3ciLxXEqhMb6jjiN+V/1Abz/fVR6Dpcx/+p++081J7bQdQRK46icFMQ/RMaY79JFFpK9JxdyKICfr+N4XAHJJuGue4Q/TWONFYQ0gtaGR/7TzUJxFJzxvC3iTZQT+nNxzi/8BU+4SXSwnI+g3uEs6OXo+a1kgvlGxN+TlYPKLGuyWVOsOsoTnVHkCVkq6G+pTQ++TPeKyuMHJQSLIuXGiXwMB7YpCofMWU4O8/GnOt5gsk6LWHPvoURRvm5ageCwpZBNuV4+oMKvsvNBkJl5pMiBgRbNJEQixBJTHySE7RAJW+kQ/4Jc/wTFXT/QKZSMP1tzKbARkSq2tOhtpaiFGeHdOoymWsS44bzo3XZbt0fOd9JTSFd6Sh8mu8uOBx58u/fhhRSnfg/mccPWmEDR43a7COPZIWVGyG8FCVjhLmcuSSgxfvwiuodYkSccUK1ykxuAa5mSuoJ0nBja3TVZXITsvMcFW78U3pysXIPqyZol71T9Q9mxwYtOTDF+U1pRAVPoxW5hId9Bzl59FwqBcHuYV50kq9RW1h7kyW9c2FB4MFC4QK4oiS1unhFFC6reOiYaTyb6yiJtkd7hv8NmQcLuj1AeLnd7U+Dv5kq+gskLMhN80c0O73gHS8VU1DtAZtbn1adwrOHLbv3P10qocypMB3TbuALtjnE32XhjlHuWois7vWivG3U5dcqPUVffzX6Gs50GXKCR7TlFp9gMy5tXxF070y6KB96ddOwK8ec1TuusjSKcn6lMXGIcwgkzUYAiU+42wkIpw17+0Sn+jAEw5lzYOABYmmAx2galj4z6dS5cvFfJMlc9cWi8pwtGJCG6G3pJlkZU9t8EGwWIMfbmOAcWtotYLhQfEB8acPO2yBWcNWjikCRIzfQO23IMerap7AmrS0ntfqWYCuYpFCUC/aBKk/eTe3MTxWqlzNpILT/oIzEIArYhNbZ1zQvYAoPRbnMkfsJl/FBoe0Qu38ZHMJ0EMq3vHXHrrormy0lEdRHSjWmgs7H3FlEg484xtRbsMtR8TlH1nQA7cKR/1x2xJ1Gg671+6u3wIh+fDrF738OihSc5lUREOhf9AhGAANECQPY/sHJjyvpzmmjvTyi6te6dA4oDjPr6QzsB3YNXFtAiEPGomfTZ+PlI81Lt4gMR0FSp9/Zrg++slozOQQf/YmFC7a9NTzhn1QtsL1S+4iCinV04rfV5nZPqufWFtb5HG1fzTMgDf8XvbunRh3YzGPs0dY8RzYQGhXgZuK2ZNaTEf0fzHKgy3UktpXTJ+jGcsrftsSSEpX/z2TDHnGQhYA+5c5o8GM4GgKb1wIB9P5kUzSIVFSv+OVY9fiRan70h3MpK+7i/5diJzHKTmrLeG0IX+Eb8fCl6Zgas287y4jVs4Lh/3hoJ78+KNNeSJt0M6d3Stys/AklMqb2y X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:09.1558 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af32b759-4cfa-4926-3ca1-08dd157c3c8d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6348 If writing the MSR MSR_AMD_CPPC_REQ fails then the cached value in the amd_cpudata structure should not be updated. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 14bd6faa3d730..ce70d1bfa55d0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -278,11 +278,15 @@ static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) value &= ~AMD_PSTATE_EPP_PERF_MASK; value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); - WRITE_ONCE(cpudata->cppc_req_cached, value); ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); - if (!ret) - cpudata->epp_cached = epp; + if (ret) { + pr_err("failed to set energy perf value (%d)\n", ret); + return ret; + } + + cpudata->epp_cached = epp; + WRITE_ONCE(cpudata->cppc_req_cached, value); return ret; } From patchwork Thu Dec 5 22:28:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13896079 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2068.outbound.protection.outlook.com [40.107.100.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03CA21DFE0C; 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Thu, 5 Dec 2024 16:29:04 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 08/15] cpufreq/amd-pstate: store all values in cpudata struct in khz Date: Thu, 5 Dec 2024 16:28:40 -0600 Message-ID: <20241205222847.7889-9-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|DS0PR12MB7946:EE_ X-MS-Office365-Filtering-Correlation-Id: e61af534-86df-405e-5f3e-08dd157c3cf1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: Ahof5tLOXuTmKJsNsRv3SdbaBigGG9paNmChVBxuXQ9gT+8H+9G1MUzdvlW8Vj51N1lCh1fN0w9JaLP0DydeO6dPj/CyyoDnYkf1QHYrP1XFw6yVfoT3mhtPrxmOLLcyvsm7IuiH6WZb/gGfQIhMOJpFoZsTzHa49keHhXeN2mNAihqDsrqEtJ8csrl40cuj0S3Y5/vepU1EqbLaP2E5Uci60u0TDruM4obHEcQ4JBYUO7veh0e/aV/Mqu9ab2+9hqG1xOe97OIipU6bLYYnvgawVGjkrIH601HJpwMCMkJXkQUns+EuOtYajkkgzwdxK4J1xm4LYmz5ukKK33CE5mNYfhzt85iqrQIfHZQR/ZTHoM+Db+ThadYC9DsyuZO0bLUilY5fAteWIdtavTcXpPn9qVOXGfr0ITGg/BrgzN8QSjmUL7pfJOkRxxi0y62YuMFVVTIKAe/QfY82s/4UHfcdV8EydTW+tIAcNM8R26Biyz+cpYB0iNWKemwShkwSUCe677mN4khDWOn1e+5Aaj2jIGa0D1ou3ABlccfpVpEjcPi2ol2LkbI+oW31WC6Pwux2J7pVXr7FsFzz9fCe4kWVCwAGxZWAlaBuPfjaCA714Cm7itIxaPJyATVUE6RjI3eYCHocd9L+cb0rygCPpVqCOn59a9AA+vWabMlkQBgzwo0d3znO49gb2bNUx2IZeJgop0ODTNboYRA1N3mXrwiKgoAc9TFzvXpJZjDb9e71ys19R3b6DyaRgXyv0FrZSu4+6F6Cv7xw9KlTvJSydHWkj1H4G5PybGWniaV7sbvv13/P8GvO81SYlatASSO8CDqzP/RLz02Axlfgc6TE+AOZ2iCRpzaxTK50t/qv1FXDeLAs74h4mvbp55qjbSH9EZ3Z3y77vuQm/IJcU2zKuKHVMjtVbq1AEN9e8UjvDKeBNOBSbXmrSnx7l0MfhOPb/X86yj9kydAWMCwovTG195UZmjieyjrxaXYUgcHH4p0YRz6WpSrVtDHVFLUZyXL660uk6rEe4uxP2pgK9ndcAYYkJmDKfSDAUtwG9eEVzJCmVz+Wo7Ogu9jwR32aJWG04o3CZbgg7xGUTeaghGNtN3xgCCzcNSWmgzqaM/Q4dXOuHgZPFguli8syrL/JRtHNwac/JFlAhXW5rR9IrwjbgaPs4z6+GKHaX3GPliK+wrY1LjSRNYtul5EbHbvNOQMgPMdkBMmXVoXGR4+rZ8P9rI8wTfyu2CDZJzGfzCwOWDvDo85IKrG2fCnKznABYIkuk0xM5QRhV6mFvrdzJZf+Yo2yQkLl2ZZHO4/mUCMupGkE/+t5PwKYaG7GrXjt/x7MPc9hBV8Ig7o2is6bO38BaLFtaXtciRg5o5wNvNox6Eeew3jPlbwaE1FGkC7moUX0lNNbsDqWG5U5NhDkLI8QEUFVPJCdmgEZSoBYNyZNwM+60ACc6DOEMUFpeCz/cB4V X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:09.8276 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e61af534-86df-405e-5f3e-08dd157c3cf1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7946 Storing values in the cpudata structure in different units leads to confusion and hardcoded conversions elsewhere. After ratios are calculated store everything in khz for any future use. Adjust all relevant consumers for this change as well. Suggested-by: Dhananjay Ugwekar Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate-ut.c | 12 +++++------- drivers/cpufreq/amd-pstate.c | 30 +++++++++++++++--------------- 2 files changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c index a261d7300951e..3a0a380c3590c 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -207,7 +207,6 @@ static void amd_pstate_ut_check_freq(u32 index) int cpu = 0; struct cpufreq_policy *policy = NULL; struct amd_cpudata *cpudata = NULL; - u32 nominal_freq_khz; for_each_possible_cpu(cpu) { policy = cpufreq_cpu_get(cpu); @@ -215,14 +214,13 @@ static void amd_pstate_ut_check_freq(u32 index) break; cpudata = policy->driver_data; - nominal_freq_khz = cpudata->nominal_freq*1000; - if (!((cpudata->max_freq >= nominal_freq_khz) && - (nominal_freq_khz > cpudata->lowest_nonlinear_freq) && + if (!((cpudata->max_freq >= cpudata->nominal_freq) && + (cpudata->nominal_freq > cpudata->lowest_nonlinear_freq) && (cpudata->lowest_nonlinear_freq > cpudata->min_freq) && (cpudata->min_freq > 0))) { amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_FAIL; pr_err("%s cpu%d max=%d >= nominal=%d > lowest_nonlinear=%d > min=%d > 0, the formula is incorrect!\n", - __func__, cpu, cpudata->max_freq, nominal_freq_khz, + __func__, cpu, cpudata->max_freq, cpudata->nominal_freq, cpudata->lowest_nonlinear_freq, cpudata->min_freq); goto skip_test; } @@ -236,13 +234,13 @@ static void amd_pstate_ut_check_freq(u32 index) if (cpudata->boost_supported) { if ((policy->max == cpudata->max_freq) || - (policy->max == nominal_freq_khz)) + (policy->max == cpudata->nominal_freq)) amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_PASS; else { amd_pstate_ut_cases[index].result = AMD_PSTATE_UT_RESULT_FAIL; pr_err("%s cpu%d policy_max=%d should be equal cpu_max=%d or cpu_nominal=%d !\n", __func__, cpu, policy->max, cpudata->max_freq, - nominal_freq_khz); + cpudata->nominal_freq); goto skip_test; } } else { diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ce70d1bfa55d0..464db6745d84e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -739,8 +739,8 @@ static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on) if (on) policy->cpuinfo.max_freq = max_freq; - else if (policy->cpuinfo.max_freq > nominal_freq * 1000) - policy->cpuinfo.max_freq = nominal_freq * 1000; + else if (policy->cpuinfo.max_freq > nominal_freq) + policy->cpuinfo.max_freq = nominal_freq; policy->max = policy->cpuinfo.max_freq; @@ -940,29 +940,29 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) return ret; if (quirks && quirks->lowest_freq) - min_freq = quirks->lowest_freq * 1000; + min_freq = quirks->lowest_freq; else - min_freq = cppc_perf.lowest_freq * 1000; + min_freq = cppc_perf.lowest_freq; if (quirks && quirks->nominal_freq) - nominal_freq = quirks->nominal_freq ; + nominal_freq = quirks->nominal_freq; else nominal_freq = cppc_perf.nominal_freq; nominal_perf = READ_ONCE(cpudata->nominal_perf); boost_ratio = div_u64(cpudata->highest_perf << SCHED_CAPACITY_SHIFT, nominal_perf); - max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000; + max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT); lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT, nominal_perf); - lowest_nonlinear_freq = (nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT) * 1000; + lowest_nonlinear_freq = (nominal_freq * lowest_nonlinear_ratio >> SCHED_CAPACITY_SHIFT); - WRITE_ONCE(cpudata->min_freq, min_freq); - WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq); - WRITE_ONCE(cpudata->nominal_freq, nominal_freq); - WRITE_ONCE(cpudata->max_freq, max_freq); + WRITE_ONCE(cpudata->min_freq, min_freq * 1000); + WRITE_ONCE(cpudata->lowest_nonlinear_freq, lowest_nonlinear_freq * 1000); + WRITE_ONCE(cpudata->nominal_freq, nominal_freq * 1000); + WRITE_ONCE(cpudata->max_freq, max_freq * 1000); /** * Below values need to be initialized correctly, otherwise driver will fail to load @@ -970,15 +970,15 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) * lowest_nonlinear_freq is a value between [min_freq, nominal_freq] * Check _CPC in ACPI table objects if any values are incorrect */ - if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) { + if (min_freq <= 0 || max_freq <= 0 || cpudata->nominal_freq <= 0 || min_freq > max_freq) { pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n", - min_freq, max_freq, nominal_freq * 1000); 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Thu, 5 Dec 2024 16:29:05 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 09/15] cpufreq/amd-pstate: Change amd_pstate_update_perf() to return an int Date: Thu, 5 Dec 2024 16:28:41 -0600 Message-ID: <20241205222847.7889-10-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|SA0PR12MB4477:EE_ X-MS-Office365-Filtering-Correlation-Id: cf7cf96f-674a-40eb-1fdf-08dd157c3d53 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: n2FopBTgP6OnfngRwuEEixcci7NZpADBAzgI7mJdWiAhoxR1tBYsZrxb69O/tJLGCj5fMb+45DeUNeM44YAtZWbYFqMeQ7qbenCe4orGV8alHFZt+EkFxKxyo82rEXvuO7TQeFNDAI/mGXukxPBCyzB3RzX4ofhG9vSOJeBKlAZZM4QTErvduO47o58IgZXjoPAy+01i27z+f8ZCcViRDiiV6UCKz41eCmtxgv10oyAMXOHbXlpYY4cVt7Sd92JuhdzeRKHznooDiOdOhKGwd00uPpBW4Jsb2TXDuQ7uHxW/eByJkJz01WzGCy9fUG+o7RCO2stoh1tOezmj2t6AFKjeVqsUZ/FpPqDE9kGO/LIfqzK3ladLd9iULuGjc7fGf6oEJxXXKbPlT9i0pE8oVGE+DCvt9krxeN5RiHi8n3sxdY++fLyKpQF39zcD9f/w1QdftXruNFzLLky9/XWc1LGIpBkN7PJkwosItLYzY2fStrZuRdQtzqSTmPfPHYYk4hGX6bsmIlkH9libDgA7Pf7aaJKZ+bi8+lOhcJGQfuQ4iWoGlzCYC7cO+2dxpuRVQYzZVjRgHxiXkwljerKJ2eoqCC9EY6B5+wiUu4FARSENy6kEkARwUd5ss+Cc16Csd6aLt25m+YwVWs5nMV8a8mes7QtymR+QudjhI0pwCMRlUEQJmI4TMBGsDNfIiL6LYyUCLL10CH9zThPNF7fBlulpec17/so23rcHtRDrFzDBZJbbWM32cb/1odBoILMoe94sFRjcPmzm2n9NY2gjGn/rrIWMUYX+/PoosYduMSCAuxn/qNS+MOj9sAUg41eH4inqcSZ0UJmKmrPc9PWFtUDxC7kweyb6PknResPNvnoj7bUAglzaiNf+LYuAn68b82G0vA//Tmd+LK5QS3K5cfPunfTgh31L9+FY1wsSNmCmhCit5rFuQCoAGyBTjJQHKsYA80wQtcOahLO2T6VTPoDUJn07v1TGP+zYEsC1/1ZIXOZTO2CKhR3vHe+cJCiykAqnqhqZZSDtORrKjk77lAt51KMJ9Y5bn4cMj1nsXYf1VvPQuWE0DCBawGapndnclKJ1GfaEPmUJ2pb3pYII6mLR/zg2FTrlfjn5xCGITR4qqlI0NV1fPAfCQw1m1dYTHfP0ornGWW4AN7/S+cAG10hLx2MvwIK9kGQlUVjDgyayNEUczo27Od6T7o4J1b/JJhz6nsTwFIOEIk5mTJ/2zxTTScpp4nbRcGXdkbIuPgKNy6v5vN5LIGdocqCjSkJhFSfqsWLGnD2XcXekjDcNnjVhPoNj9wJWSEwSAEyDVE8CnJKGLwkdRngB4Rv2B65+a2UHOgV8aIit/HoW9l7b4/zglqUMLaywz0BuqME5EYNJLPC42iE48IekQ0trtY0RAYf6LAQBXha+C/4jcqB8KGHYSACHuSwNRrV8Runm69YEohQI23MUL9NiO3X+8KmO X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:10.4683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf7cf96f-674a-40eb-1fdf-08dd157c3d53 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4477 As msr_update_perf() calls an MSR it's possible that it fails. Pass this return code up to the caller. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 464db6745d84e..842e7e3c5eaf2 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -251,24 +251,26 @@ static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) return index; } -static void msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, +static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { - if (fast_switch) + if (fast_switch) { wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); - else - wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); + return 0; + } + + return wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + READ_ONCE(cpudata->cppc_req_cached)); } DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf); -static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata, +static inline int amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { - static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, - max_perf, fast_switch); + return static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, + max_perf, fast_switch); } static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) @@ -480,7 +482,7 @@ static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) return static_call(amd_pstate_init_perf)(cpudata); } -static void shmem_update_perf(struct amd_cpudata *cpudata, +static int shmem_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { @@ -490,7 +492,7 @@ static void shmem_update_perf(struct amd_cpudata *cpudata, perf_ctrls.min_perf = min_perf; perf_ctrls.desired_perf = des_perf; - cppc_set_perf(cpudata->cpu, &perf_ctrls); + return cppc_set_perf(cpudata->cpu, &perf_ctrls); } static inline bool amd_pstate_sample(struct amd_cpudata *cpudata) From patchwork Thu Dec 5 22:28:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13896078 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2041.outbound.protection.outlook.com [40.107.95.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D17A1E0090; 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Thu, 5 Dec 2024 16:29:05 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 10/15] cpufreq/amd-pstate: Move limit updating code Date: Thu, 5 Dec 2024 16:28:42 -0600 Message-ID: <20241205222847.7889-11-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|PH7PR12MB9102:EE_ X-MS-Office365-Filtering-Correlation-Id: 22d17384-2514-454a-2e3e-08dd157c3dc3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: /JNMOvctAnWEPC0K7E8zVPi1u9t3wn/iq3zfKwrq7/iOCT15ZNPzjNG9k1p2PtTcJRXBPzLcwlx/00Ktk/yXGQMyBjsCUQEPaBG3ARIrrgH2ROkFRdLPz9ESC1cPW/cr3ZcAImT/dw1MozHGskZGD03Cvt0cfbqovNM/mEwx/+o9qHVWd0PP+ibeb2seTGuDXthZbVSePyVRPpjYh3r4dn5uTeB476Qnbqe/7Gl9X9NTwZfDSA0TmqHJocP2YRVtO09OlLsn1riET9y5SgpRTwqXak/bugOAGBYmM47pcNB8NAJh0w5+/Eq+CSm9URhEwndHoIYnkUbDoB7ZjOveQP8RvoO0u/e4W6vGd+O7IN/2c0B/jCU4SGXL0v8SOML6LZTK/5knHROUlntRP4i6MMxBpXGt7TOYtRWUoMHYoI96b1koabXw+5T0iqrKYnlHeNFjimYPoxNocaygM9gngVHyKcPY8bI8dNwPZxrefCXmRtYTGGrQ9n6v8++grJo40Sb+8JQS8vrVvRbokEchFS7zwpsPcDvQGIJVqeIiN2tCMY3FcmF13bKsgsFsegtywOL4+IeRrhb8NS47JFxRtMibklfHAIkp3w09f6YLM7cMeIWb44ukgYHuvwUVWyxRY/ShrYZRFZqKJIUJWxBeu7eAYLq/odNQ2JIAjb7kFL27+ZcC9i0EnoorkGBvD/J6l5nR7XdChupNgE2JaANbiLJsgTpwvzQMXyCMWs09oPYyF6bDgG6aGPu8+VF1T3azvp46+dycmpdIyuDhh4aSydF3lj2B/DekpQkOM0JwmkAcJbttbnzeUXE5bCJJEutt0mICiXCYHyEh5d//7WWiJNaVCsazIzdmeyUD21y7kBxZj9dPfac5mDez9MSXpS908JOzP29i+Yl9I2QlFUVsNrC52kIbuAqRsj3sBkWStDT+dRX3YZkEf7NQKkdMzAdegyKPfnl3jD3yO8WVbGmSZZF2PqNPvhu+FimYz5rsHx+CRLhStReP5AJ1M5NX6EMQjpxLuV1kqR26dKGHx1W3PeDtOzungw0Ydopxa6kGam47j/AeHum7ZVDWuxnkgSNRIZC0Ae7Cn3eWgKVYWS187gJf/dZrBBTqqYFpmQCSA18dPGfJ31AjXzy2lazwI62v5C9jeNFwdMvuwVdekUcx1nUqpK37t3oAJgVcVelR+54SQVnbZcFJszjctgFHHXgGUrbT53puJ39bIRh9YicHee8GAB7oNW0K92IxTElSpGhpaTvhRIkmnOeveY2wgx/B7gGhjworPBgbKdmN05jsGyMuZm11A4gw6x/ikZEukOqoWg4PNHgG0IyONbkQ5Dhw62aaUcBkxh9PEExIvNJMjUNTYJBxsvAGixqibKhLRf49EJLpaMCv1LYG4vB5gWsrar+Ldgf/I2YyEjAseusdalAEmRRdsdvDDbWO7JLfwaRD6e6DIfzgbKi33bgXzajv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:11.2026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22d17384-2514-454a-2e3e-08dd157c3dc3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9102 The limit updating code in amd_pstate_epp_update_limit() should not only apply to EPP updates. Move it to amd_pstate_update_min_max_limit() so other callers can benefit as well. With this move it's not necessary to have clamp_t calls anymore because the verify callback is called when setting limits. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 842e7e3c5eaf2..5ee53b45c1ca1 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -537,10 +537,6 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; - min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); - max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); max_freq = READ_ONCE(cpudata->max_limit_freq); @@ -616,11 +612,9 @@ static int amd_pstate_update_min_max_limit(struct cpufreq_policy *policy) min_limit_perf = div_u64(policy->min * max_perf, max_freq); lowest_perf = READ_ONCE(cpudata->lowest_perf); - if (min_limit_perf < lowest_perf) - min_limit_perf = lowest_perf; - if (max_limit_perf < min_limit_perf) - max_limit_perf = min_limit_perf; + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) + min_limit_perf = min(cpudata->nominal_perf, max_limit_perf); WRITE_ONCE(cpudata->max_limit_perf, max_limit_perf); WRITE_ONCE(cpudata->min_limit_perf, min_limit_perf); @@ -1562,28 +1556,18 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; - u32 max_perf, min_perf; u64 value; s16 epp; - max_perf = READ_ONCE(cpudata->highest_perf); - min_perf = READ_ONCE(cpudata->lowest_perf); amd_pstate_update_min_max_limit(policy); - max_perf = clamp_t(unsigned long, max_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); - min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, - cpudata->max_limit_perf); value = READ_ONCE(cpudata->cppc_req_cached); - if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) - min_perf = min(cpudata->nominal_perf, max_perf); - value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | AMD_PSTATE_DES_PERF_MASK); - value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, cpudata->max_limit_perf); value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); - value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, cpudata->min_limit_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value); From patchwork Thu Dec 5 22:28:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 13896081 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2071.outbound.protection.outlook.com [40.107.94.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F25C11E008E; Thu, 5 Dec 2024 22:29:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 5 Dec 2024 16:29:06 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 11/15] cpufreq/amd-pstate: Cache EPP value and use that everywhere Date: Thu, 5 Dec 2024 16:28:43 -0600 Message-ID: <20241205222847.7889-12-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A347:EE_|PH7PR12MB6884:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d07fbd9-79a5-4484-86d5-08dd157c3e00 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: tjEe1fMFYo6D7L1s7esIYSL/PokUm/bJguyW+SY6zrOAYxrl6153nQEYrT3WcZfN34eHiw/RDbdPXHjBZLfbfWLYDoAhVTICIyqAEKe+BQMPgeuLLBl3nUQN4MzATzrqDA01CHs3MoRBJv8V+8rhztEtNY+VI3K13lXipc+GJ6yWmJ73rT1HUlHzvXGvKb1SI2U3Al/+RqXCWh59uzZECuSglIInujzca7TSLNc/6ssle1GzZjYNNJGcoo2/CQFKSwmi2UgMtsIrnA8nmMRDrYTiqQCZsj4+hqrkJcsOBSBakMR1ueiqWhQtQzX3cPocsQcOMHf7uSVTAOvdaXdhC/lZ5Vk6p7Kxr9Hxnh5Ieg6PosOJF4C/UamKIY4ToQ4rg3hcPRxbgAuI1r96UEOHyXOIj5oTF9YIN1qVvIY2hv2UR2OQKJtgViUWH2Yul1hwRvmrZcRccvuy5CAb3v7+oAV3aBYnRRJHSPN2zV8szrBOYr1m8YfyYQJz7wIGU6jD9MQq5FzQ4bei9uNzZ4Brq2T/ksZ0pbssE8MGpzl/aiRhDyiP0pVvyai6lMggzB4ZreTXS17gEAZGczKJSOxIrBSR3IJRSNpCJXrJFgOxXEhr2HTBDaFWFo6yxlujcLbgHDQMLY3KWft5WpjzxUrU06AAYyMDqHLynztQOKwynhTdYMSGTemTE/fH4ndb8HdPWDlKE5LdHLVzTqz5dT6XZL3RUOXN7WpzDyBONyAe342c0unI6KodLGoJfidIVMF+qLeZ8rnlPnmP2uKUQKB0qiWrn0KaAmVyWE01EvwtzNpjrWyXgoefqCJz7Vj/igK/N8E1gBf3/TlxktgjjfHAwlMFTfPn5kIpsV9Y+JvdUhgZonFD2qloi7ERSyhKf5XB1/JunTiJpuaBxFObS7tWWuPoHB8Rt/ECxSW0KnxShPBpcj5BD9rwV3Yq7iGvD/4+OH21dA9iN1woikvHASXxeVZ2QxlmKI5qLBnKNs+lYT8xZBjLbdiikwnX2ZoRZSMQidRWYNDN/Lp5CUijaO0uTlyUdCZrOZE61jlvxdjq5VxrrWCMoPF4piCihUADW9jzSLsfyAIN9mMEpH/FhDK2v/Cgjvh+Bv8q0sZifko4rxlP4QzarGnOcn7poY43XvcN+F0Ut3EmvBXVFCVbV/3lZIHLS9LABuqkMH1FlZiiLPGfMZGrByzmLqoCplUHx6P6wJ1BvApqD6BypyjZ+cWM6XWyi6I5joHrPQxDnYmvP89tJ2K+gXV77cl96kwVQe1zqXUU1x2zD9Yc8EP3z/iO4f7k/RlwF/iWSHs2ZEb+UfUYwQc3NVDgyoCXaOfvLGO+HiwePwn49wTQOVi8wabe9aXyKuh43qok/ggEE0D/4WSh9RM1zyejVMuB8A0Lf08luzc0OZNQf5xt+S5TXFTS8qSKSeE5Vkd3pQSaxd+DKT8omMsiDHFoQm3mM5hZvV9r X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:11.5890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d07fbd9-79a5-4484-86d5-08dd157c3e00 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A347.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6884 Cache the value in cpudata->epp_cached, and use that for all callers. As all callers use cached value merge amd_pstate_get_energy_pref_index() into show_energy_performance_preference(). Check if the EPP value is changed before writing it to MSR or shared memory region. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 107 +++++++++++++++-------------------- 1 file changed, 45 insertions(+), 62 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 5ee53b45c1ca1..20de3a9fd992d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -186,29 +186,28 @@ static inline int get_mode_idx_from_str(const char *str, size_t size) static DEFINE_MUTEX(amd_pstate_limits_lock); static DEFINE_MUTEX(amd_pstate_driver_lock); -static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +static s16 msr_get_epp(struct amd_cpudata *cpudata) { + u64 value; int ret; - if (!cppc_req_cached) { - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); - if (ret < 0) { - pr_debug("Could not retrieve energy perf value (%d)\n", ret); - return ret; - } + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return ret; } - return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached); + return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, value); } DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); -static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +static inline s16 amd_pstate_get_epp(struct amd_cpudata *cpudata) { - return static_call(amd_pstate_get_epp)(cpudata, cppc_req_cached); + return static_call(amd_pstate_get_epp)(cpudata); } -static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy) +static s16 shmem_get_epp(struct amd_cpudata *cpudata) { u64 epp; int ret; @@ -222,35 +221,6 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata, u64 dummy) return (s16)(epp & 0xff); } -static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata) -{ - s16 epp; - int index = -EINVAL; - - epp = amd_pstate_get_epp(cpudata, 0); - if (epp < 0) - return epp; - - switch (epp) { - case AMD_CPPC_EPP_PERFORMANCE: - index = EPP_INDEX_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_PERFORMANCE: - index = EPP_INDEX_BALANCE_PERFORMANCE; - break; - case AMD_CPPC_EPP_BALANCE_POWERSAVE: - index = EPP_INDEX_BALANCE_POWERSAVE; - break; - case AMD_CPPC_EPP_POWERSAVE: - index = EPP_INDEX_POWERSAVE; - break; - default: - break; - } - - return index; -} - static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch) { @@ -275,19 +245,23 @@ static inline int amd_pstate_update_perf(struct amd_cpudata *cpudata, static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - u64 value = READ_ONCE(cpudata->cppc_req_cached); + u64 value, prev; int ret; + value = prev = READ_ONCE(cpudata->cppc_req_cached); value &= ~AMD_PSTATE_EPP_PERF_MASK; value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); + if (value == prev) + return 0; + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); if (ret) { pr_err("failed to set energy perf value (%d)\n", ret); return ret; } - cpudata->epp_cached = epp; + WRITE_ONCE(cpudata->epp_cached, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); return ret; @@ -305,13 +279,16 @@ static int shmem_set_epp(struct amd_cpudata *cpudata, u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; + if (epp == cpudata->epp_cached) + return 0; + perf_ctrls.energy_perf = epp; ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); if (ret) { pr_debug("failed to set energy perf value (%d)\n", ret); return ret; } - cpudata->epp_cached = epp; + WRITE_ONCE(cpudata->epp_cached, epp); return ret; } @@ -1216,9 +1193,22 @@ static ssize_t show_energy_performance_preference( struct amd_cpudata *cpudata = policy->driver_data; int preference; - preference = amd_pstate_get_energy_pref_index(cpudata); - if (preference < 0) - return preference; + switch (cpudata->epp_cached) { + case AMD_CPPC_EPP_PERFORMANCE: + preference = EPP_INDEX_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_PERFORMANCE: + preference = EPP_INDEX_BALANCE_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_POWERSAVE: + preference = EPP_INDEX_BALANCE_POWERSAVE; + break; + case AMD_CPPC_EPP_POWERSAVE: + preference = EPP_INDEX_POWERSAVE; + break; + default: + return -EINVAL; + } return sysfs_emit(buf, "%s\n", energy_perf_strings[preference]); } @@ -1503,7 +1493,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata, 0); + cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata); policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; @@ -1557,35 +1547,26 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; u64 value; - s16 epp; amd_pstate_update_min_max_limit(policy); value = READ_ONCE(cpudata->cppc_req_cached); value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | - AMD_PSTATE_DES_PERF_MASK); + AMD_PSTATE_DES_PERF_MASK | AMD_PSTATE_EPP_PERF_MASK); value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, cpudata->max_limit_perf); value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, cpudata->min_limit_perf); - /* Get BIOS pre-defined epp value */ - epp = amd_pstate_get_epp(cpudata, value); - if (epp < 0) { - /** - * This return value can only be negative for shared_memory - * systems where EPP register read/write not supported. - */ - return epp; - } - if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) - epp = 0; + WRITE_ONCE(cpudata->epp_cached, 0); + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, cpudata->epp_cached); WRITE_ONCE(cpudata->cppc_req_cached, value); if (trace_amd_pstate_epp_perf_enabled()) { - trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, + cpudata->epp_cached, cpudata->min_limit_perf, cpudata->max_limit_perf, cpudata->boost_state); @@ -1594,7 +1575,7 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, cpudata->max_limit_perf, false); - return amd_pstate_set_epp(cpudata, epp); + return amd_pstate_set_epp(cpudata, READ_ONCE(cpudata->epp_cached)); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 12/15] cpufreq/amd-pstate: Always write EPP value when updating perf Date: Thu, 5 Dec 2024 16:28:44 -0600 Message-ID: <20241205222847.7889-13-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|LV3PR12MB9167:EE_ X-MS-Office365-Filtering-Correlation-Id: 3950fe58-0c56-48e1-3b73-08dd157c3e52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: hT9Sjgcpiexn+rwtMFrqRs2t1xc1B+ifwzASJi7GxPW22/KdT6Q8M7/23UIvi4zFLQARn7OolH1fOpJ/gUXS3ygs9iB8ODcJBqfaqSIF43eP+o1ilZli87k0Ho6n1eizDPARnqsyRLSiejO1dm3KmZamT8MqnssNZ2yLBBde4e1dBjW6X1esVqlE8BIAsgV7VVJ0F0oLAz9SCq9cjVmFBKmng0aDknYFb3usMeNIkW9JIAd77kJlP1OJssW6qUSYLkFF4fgfzv6y0O6p3li0ViCwofYywuhgfKdCUFCCscUyHFp9VtFHeJ7g8Y0e9QDyNChGjjhjejvLkyAEgh2szMjGTXys2fwfp1YoK86GtSTbbmcLi6Q6CwSdscc90WyWpl8YfhzVb4XwTgoIVfOFYvF64H3fj+/ZuNDrSL14Il3VcWRilFTjrzsgnuWx9mNGkmPx5vkPAk1lFv0p9na0QNDeUVl3tNikIlQLTZS8II73QNVL7Wl1frxPrYQu+Ac3rj70NixNYMvPNAvvpIMEUL9lHZE+8GjUt18fArHk4noaq/jvtrqRVirzaFybS/tkrxHaA1mf1QzzA/CDpKMeMd47hOw3yUlpFyVYBaUeiWhZFaEBqrrKIjKrSjJBBubl/8i73OjEfy4A9ANT/e1W4SeggVOYGIx7ptYlSLaHjzljo2UnKfa0O+sufDs9MkyJy9KB+rvMruTMEwu5eZlTyWgGUma21oKyY9zCw174KtDI/WjS0cUPxNSfXYvzUjn5stcf9O8tk/kiDlvzfbWYRus65oF/JSpu4VQ9iQa3dfiN2IdnX0pIO7kJensXcONjGdwv8qDqBEgS0uS6gfD7NntL/nBWir6fNPNO3Dwrsv6AyPjdO7/Jdm4BQEPz09xluV7WVIyHU4IRuthfeotuMirwSMi1HzacmzgYGZ9uGy4jJTFkiU7yC5ozIr8EJpFJ3XArBtLqIril7nQbc3efYDMFCyZakal51HWN5YVkQ/0yMO+RD5gl/hG91Ts3doaeSNjS9okN2Kbp0MlLO7bYjKf/5JiFugr7l6QQUNFEWt0MhiyZMntKHgHN9rnnwS/tFqMvxQdQG8cpMnTVV1TovGvIM+gOpI9ZJOT0fM0jl6TM/E8ISYTzY+1ojBM4Ny7M6pKE3/HJHoL5Wb8snPJZrKUvgnr3gZ5JE+RuwdyrXQPI9xfIgO8lm2ObcB5Ha8NthnYQmyP9Jwbbtd2+FQnWmN9f+CQQAewhLkcM9Sb/2Ng8HXmHKN/7iGNJhwsbVKXMoXfsjEeQwREMOIhZRnM+8/M/hqAeBiDK/e5yFoPUp+pedzJiwyXplFtsrf+dmP+6tsQCn6ATJBOdozuBieeI5rQ//CbBBGoY277cHMi0H4rehfCg7uFlvAhPKp0vEQRZ2vGPgYNJpkbzYSzoTohYL55gDP/uCxuSQABuQlgqertUSoo7/xzRH0sh+FnGRLiC X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:12.1245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3950fe58-0c56-48e1-3b73-08dd157c3e52 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9167 For MSR systems the EPP value is in the same register as perf targets and so divding them into two separate MSR writes is wasteful. In msr_update_perf(), update both EPP and perf values in one write to MSR_AMD_CPPC_REQ, and cache them if successful. To accomplish this plumb the EPP value into the update_perf call and modify all its callers to check the return value. Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 71 ++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 20de3a9fd992d..8598f50e18b58 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -222,25 +222,36 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata) } static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, - u32 des_perf, u32 max_perf, bool fast_switch) + u32 des_perf, u32 max_perf, u32 epp, bool fast_switch) { + u64 value; + + value = READ_ONCE(cpudata->cppc_req_cached); if (fast_switch) { wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); return 0; + } else { + int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + READ_ONCE(cpudata->cppc_req_cached)); + if (ret) + return ret; } - return wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); + WRITE_ONCE(cpudata->cppc_req_cached, value); + WRITE_ONCE(cpudata->epp_cached, epp); + + return 0; } DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf); static inline int amd_pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, - u32 max_perf, bool fast_switch) + u32 max_perf, u32 epp, + bool fast_switch) { return static_call(amd_pstate_update_perf)(cpudata, min_perf, des_perf, - max_perf, fast_switch); + max_perf, epp, fast_switch); } static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) @@ -459,12 +470,19 @@ static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata) return static_call(amd_pstate_init_perf)(cpudata); } -static int shmem_update_perf(struct amd_cpudata *cpudata, - u32 min_perf, u32 des_perf, - u32 max_perf, bool fast_switch) +static int shmem_update_perf(struct amd_cpudata *cpudata, u32 min_perf, + u32 des_perf, u32 max_perf, u32 epp, bool fast_switch) { struct cppc_perf_ctrls perf_ctrls; + if (cppc_state == AMD_PSTATE_ACTIVE) { + int ret = shmem_set_epp(cpudata, epp); + + if (ret) + return ret; + WRITE_ONCE(cpudata->epp_cached, epp); + } + perf_ctrls.max_perf = max_perf; perf_ctrls.min_perf = min_perf; perf_ctrls.desired_perf = des_perf; @@ -545,10 +563,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, WRITE_ONCE(cpudata->cppc_req_cached, value); - amd_pstate_update_perf(cpudata, min_perf, des_perf, - max_perf, fast_switch); + amd_pstate_update_perf(cpudata, min_perf, des_perf, max_perf, 0, fast_switch); cpufreq_policy_put: + cpufreq_cpu_put(policy); } @@ -1547,6 +1565,7 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; u64 value; + u32 epp; amd_pstate_update_min_max_limit(policy); @@ -1559,23 +1578,19 @@ static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, cpudata->min_limit_perf); if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) - WRITE_ONCE(cpudata->epp_cached, 0); - value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, cpudata->epp_cached); - - WRITE_ONCE(cpudata->cppc_req_cached, value); + epp = 0; + else + epp = READ_ONCE(cpudata->epp_cached); if (trace_amd_pstate_epp_perf_enabled()) { - trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, - cpudata->epp_cached, + trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp, cpudata->min_limit_perf, cpudata->max_limit_perf, cpudata->boost_state); } - amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, - cpudata->max_limit_perf, false); - - return amd_pstate_set_epp(cpudata, READ_ONCE(cpudata->epp_cached)); + return amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U, + cpudata->max_limit_perf, epp, false); } static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) @@ -1606,7 +1621,7 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) return 0; } -static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +static int amd_pstate_epp_reenable(struct amd_cpudata *cpudata) { u64 max_perf; int ret; @@ -1624,17 +1639,19 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) max_perf, cpudata->boost_state); } - amd_pstate_update_perf(cpudata, 0, 0, max_perf, false); - amd_pstate_set_epp(cpudata, cpudata->epp_cached); + return amd_pstate_update_perf(cpudata, 0, 0, max_perf, cpudata->epp_cached, false); } static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; + int ret; pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); - amd_pstate_epp_reenable(cpudata); + ret = amd_pstate_epp_reenable(cpudata); + if (ret) + return ret; cpudata->suspended = false; return 0; @@ -1658,10 +1675,8 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) min_perf, min_perf, cpudata->boost_state); } - amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false); - amd_pstate_set_epp(cpudata, AMD_CPPC_EPP_BALANCE_POWERSAVE); - - return 0; + return amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, + AMD_CPPC_EPP_BALANCE_POWERSAVE, false); } static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) From patchwork Thu Dec 5 22:28:45 2024 Content-Type: text/plain; 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 13/15] cpufreq/amd-pstate: Check if CPPC request has changed before writing to the MSR or shared memory Date: Thu, 5 Dec 2024 16:28:45 -0600 Message-ID: <20241205222847.7889-14-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|DS0PR12MB8455:EE_ X-MS-Office365-Filtering-Correlation-Id: 83e8b0d1-117f-4c1b-fc14-08dd157c3eb3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: U6k3tcpt7ATCvYVZNvCQEimFn5Xn5Ddo3gN9bqbPd10guFBBdeOeP4dP3ZtP3a7vpGo3Xk5yGahZYZGPylOBQ1qgj4YOU4FOXAIre598V/Mv8onQGWREUH3do9dddjga2pqIGbk7lF8/oiy41RTv7XteoE37fDokl0EK/Op6Tb1IxVHZuqMJwMd0xVD1evNZhH7GGdZNhMw6LaX+8Qw0K5ovEqhmGHOU2B2AmMcFkWM+SaUtzh9lLXVH7EkyBmWt8KX100LpZL1lU8f+NKVu441y3/xbdZQ/HFKwfADqPiAXCiKsvC0F4+Zd6cmx9a3RvCkAOik5inXqfMVFq2aFLGD8EqFvNxDoCdzEddi2Jp7USEnb/cfIcsTWN8MZdR53lg4gL6ggI1dR1r2TrcZt15/a5K+C7Q/w48Ln9WcbFX1+Zn64kqQh0j+DZvDSa4YbacqVnHgiX2T+8UxQRRg7WCtwsYjBq97W81zeViTa8KPq6ZYBswhw2vNpazHEe2KjZKqrDkBFL6CXMmV02hK2R5D6QRUETBpNzNGoVAgY//O9ALtMzprDYJm3lwlLm6kh2wBa1/QKpGv6hj9k9TDL2XiSW67AOEbN9y3sXBInLD9ZUpAL8YJVRcwf1udB8NpVhaGqIu9O4r3d8AiYBTksKNA14BEwsHjL5D8QOdARKFtNPvF57vft3MGbG7PElJ26CmkVpa6+qfpft6T7qS6ce7iLhOiYY7XDRvrH+GQ+VxqGqa4KIExwwieQYqIRnxAw6iz7dwHZGCfUd+SDYOvJgEqGmen3/RWlHhx4vUilW3M/Ewowh4dqvlPh/NXsF3+cHy1O+TpP/+GKWhcxWZlAarHl8NswD9fXhLpwT08qRRth9PUpRvkyryT/S3jqse5ztszGkuIFC5+ZNdnizQwGLZ+MnD0BvEIT3/gKLpV74tGRuG4ATz5J6859ov5OFBeyIxozXlH8vzqYwvjcQIYhCef59oHBmCeloQkA//ETdGAi1Hs+2s0GPPBzcIFGjQs4GnCTO1+mt0in9t4NbXjE0vNmC2fc6+SoZfX5iGY/mYkqerL1khxXyx42RlJEgU2EXGWe6RTOCgZ72GbKNuQgHoRigvow9wo8CH2sO4cWmxPWDJOTnhDGRM/DEpAOM3b3ZtBohMJQ+K/zBESQyVssHwvRf/Xam48AIoi/uJwBUjhiKSeSihCE32KmwipU6yaSwDw27+B0YSVnIhZQCcVpHpW0NI4OnvVJWCKPiPlTPHCj96e9mEixO3bF8cj4Fz7tdCDXUe4WchPQFdg5RuQGAFEaHP+twiPp67ykRKddMLQOxx7M5G6b+xBP5F79+FVWKog87Es3/cohO+gsf6aY5SamJrjl/k1L6k/GoqbvB7vjpeQD7JJtdK2RHB50naVeQTv8CJ7KV6u67NW8n48lfgX4LHoVZWVDAMbTRB4MwGX3nmDVO7buMrjH6QqyA5ZZ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:12.7808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83e8b0d1-117f-4c1b-fc14-08dd157c3eb3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8455 Move the common MSR field formatting code to msr_update_perf() from its callers. Ensure that the MSR write is necessary before flushing a write out. Also drop the comparison from the passive flow tracing. Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate-trace.h | 7 +---- drivers/cpufreq/amd-pstate.c | 47 +++++++++++------------------- 2 files changed, 18 insertions(+), 36 deletions(-) diff --git a/drivers/cpufreq/amd-pstate-trace.h b/drivers/cpufreq/amd-pstate-trace.h index e2221a4b6901c..8d692415d9050 100644 --- a/drivers/cpufreq/amd-pstate-trace.h +++ b/drivers/cpufreq/amd-pstate-trace.h @@ -32,7 +32,6 @@ TRACE_EVENT(amd_pstate_perf, u64 aperf, u64 tsc, unsigned int cpu_id, - bool changed, bool fast_switch ), @@ -44,7 +43,6 @@ TRACE_EVENT(amd_pstate_perf, aperf, tsc, cpu_id, - changed, fast_switch ), @@ -57,7 +55,6 @@ TRACE_EVENT(amd_pstate_perf, __field(unsigned long long, aperf) __field(unsigned long long, tsc) __field(unsigned int, cpu_id) - __field(bool, changed) __field(bool, fast_switch) ), @@ -70,11 +67,10 @@ TRACE_EVENT(amd_pstate_perf, __entry->aperf = aperf; __entry->tsc = tsc; __entry->cpu_id = cpu_id; - __entry->changed = changed; __entry->fast_switch = fast_switch; ), - TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu freq=%llu mperf=%llu aperf=%llu tsc=%llu cpu_id=%u changed=%s fast_switch=%s", + TP_printk("amd_min_perf=%lu amd_des_perf=%lu amd_max_perf=%lu freq=%llu mperf=%llu aperf=%llu tsc=%llu cpu_id=%u fast_switch=%s", (unsigned long)__entry->min_perf, (unsigned long)__entry->target_perf, (unsigned long)__entry->capacity, @@ -83,7 +79,6 @@ TRACE_EVENT(amd_pstate_perf, (unsigned long long)__entry->aperf, (unsigned long long)__entry->tsc, (unsigned int)__entry->cpu_id, - (__entry->changed) ? "true" : "false", (__entry->fast_switch) ? "true" : "false" ) ); diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 8598f50e18b58..06464e2dd905f 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -224,15 +224,26 @@ static s16 shmem_get_epp(struct amd_cpudata *cpudata) static int msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, u32 epp, bool fast_switch) { - u64 value; + u64 value, prev; + + value = prev = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK | AMD_PSTATE_EPP_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); + + if (value == prev) + return 0; - value = READ_ONCE(cpudata->cppc_req_cached); if (fast_switch) { - wrmsrl(MSR_AMD_CPPC_REQ, READ_ONCE(cpudata->cppc_req_cached)); + wrmsrl(MSR_AMD_CPPC_REQ, value); return 0; } else { - int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - READ_ONCE(cpudata->cppc_req_cached)); + int ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (ret) return ret; } @@ -528,9 +539,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, { unsigned long max_freq; struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu); - u64 prev = READ_ONCE(cpudata->cppc_req_cached); u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); - u64 value = prev; des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); @@ -546,27 +555,14 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | - AMD_PSTATE_DES_PERF_MASK); - value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); - value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); - value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); - if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, cpudata->cur.mperf, cpudata->cur.aperf, cpudata->cur.tsc, - cpudata->cpu, (value != prev), fast_switch); + cpudata->cpu, fast_switch); } - if (value == prev) - goto cpufreq_policy_put; - - WRITE_ONCE(cpudata->cppc_req_cached, value); - amd_pstate_update_perf(cpudata, min_perf, des_perf, max_perf, 0, fast_switch); -cpufreq_policy_put: - cpufreq_cpu_put(policy); } @@ -1564,19 +1560,10 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; - u64 value; u32 epp; amd_pstate_update_min_max_limit(policy); - value = READ_ONCE(cpudata->cppc_req_cached); - - value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | - AMD_PSTATE_DES_PERF_MASK | AMD_PSTATE_EPP_PERF_MASK); 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Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello Subject: [PATCH 14/15] cpufreq/amd-pstate: Drop ret variable from amd_pstate_set_energy_pref_index() Date: Thu, 5 Dec 2024 16:28:46 -0600 Message-ID: <20241205222847.7889-15-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|DM4PR12MB7598:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c24f16d-0314-4b24-6fb7-08dd157c3ee8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: g8FqVJwsEe+Jg3vZNPLVPKsADXK5o8zK7TXe79Tm/O7JK6my3cBVLvbrahwd3jbrbREVKMtUIrY5XR0JVCburanosiga6MXwnb1zG8cc7kuZYyw+5yDo9wAtxrEmvkKJqzuLlqxwGjmo5/m3Vj7GOOjZHH1tqVVQ6CYpkS2BFn4DO4cxqcgmk6tGgKqCAq8ieSOLNTXxudVf/NQ+7HwXz0SW0QAYcLKPyuE8h2fzDrrW28XXvIDsNdtDlk3WGzOjvPBR9nmCzRq86Po9v40S2WVKh2+wBT4BwELFS4ESTyS8J7JVReQ7lmrqmkwyQPZJv7YG8ZfTTsbsHemHmd3KGaoaM7N5fXmfdxglAoaz6JKj91i6SJ72ScqcjcsZhEz3Y9+8/xQzD3vWTt23WGKb0ZWr1hEz4FqPOCI08W6CzEpQMfc8On2ObWwyTWQdLW4tvk6m3nrSXgPdVMmcPniUS1NjAFMV/37nyogYji/pkIEoV2zpC3My+5jeIEVz0NvOMSc7F2Li5/7n2zmyDW2Enj2EnT9I9tbhSw40gCjCvftUtORfhJYuC0sfebUEGV+hzSQHNEKLaEQZIIlrouhUPGMsyhYd+w5Ni8LIobE7fJJzFj5j/lUYMtePL+uw7BRA2YQ9CU+zLRrjtS3aZI6dBMD2yy37HkR1rzXhEGjdKPEwUBsS7vZq775duSYjamT1G/71/bFkP1QWVFcXd6ZQGDM0odslRUUMXkGQMlcPdU1hHMvlfyqStf/zbqdgsCLOwlq1pDKEgJE2rs5nIWlmSPD2W0bU1gAMOgEw6TK4coCgBn2JbgoZMhCAf5SZ1ljUAaBquiVTl/68iK7y9WpC1abWidQrv0AsKeYrjFDWkCiRJHdCf4sJhezhClLjl39ypohxZCRvyzm+V9ZSkDfs2ktIlFBTRkye8FjGyFW7VA5o5T+Tx+oo1YPICTWLtzz/Q2zgcPGaotE6KfIn6p9DIDVKITe3YCGntDb5YS/QvhQZSiBl8gRBB/yJnHjqmgli8qDXYUzR9IHvjEUYzkFn5nlKva5zVOzrCzP5C6Sm+cIhGmEM02HUmScnk/QKSa7dyfWZSC8yi4w3HKDC8OSi03TFcSCIrutAiWFS3eKiGl2ur0tW4/ejMo7Dz6oDCWuQx2Ttm6U/NUNW2oZ7EMzt52CQg14ItPj2ewTgjiwtHdodfLtHj0+18BfsORQcfKB4hnWxfuOBSwQxIpDwnd/EbiHviFUNJ9IiOidGUSNlNcABCP3WRGRJOb4AHSmc4cA05H8rqc2Ez5t1bv9rgYSy3eBUyMin/GzY8pxImsePriHx5Z6L56rmB2RZyK4BpTLP4+gDthvdII/oP+68T72U/8aRirYDsmINPMD3gFQdU+w8T2mwNidKFb43Py3fqsrxS6stOYNN8fg+89KmAcIzlIQdv3ZacKf3UfKdO6GTvIGMLUKEdEELrJ6zRHkcpyMB X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:13.1245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c24f16d-0314-4b24-6fb7-08dd157c3ee8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7598 The ret variable is not necessary. Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 06464e2dd905f..b361e691fd33e 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -318,13 +318,11 @@ static int shmem_set_epp(struct amd_cpudata *cpudata, u32 epp) static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, int pref_index) { - int epp = -EINVAL; - int ret; + int epp; if (!pref_index) epp = cpudata->epp_default; - - if (epp == -EINVAL) + else epp = epp_values[pref_index]; if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { @@ -340,9 +338,7 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, cpudata->boost_state); } - ret = amd_pstate_set_epp(cpudata, epp); - - return ret; + return amd_pstate_set_epp(cpudata, epp); } static inline int msr_cppc_enable(bool enable) From patchwork Thu Dec 5 22:28:47 2024 Content-Type: text/plain; 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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000A349.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8230.7 via Frontend Transport; Thu, 5 Dec 2024 22:29:13 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Dec 2024 16:29:07 -0600 From: Mario Limonciello To: "Gautham R . Shenoy" CC: Perry Yuan , , , Dhananjay Ugwekar , Mario Limonciello , "Artem S . Tashkinov" Subject: [PATCH 15/15] cpufreq/amd-pstate: Set different default EPP policy for Epyc and Ryzen Date: Thu, 5 Dec 2024 16:28:47 -0600 Message-ID: <20241205222847.7889-16-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205222847.7889-1-mario.limonciello@amd.com> References: <20241205222847.7889-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A349:EE_|SN7PR12MB7348:EE_ X-MS-Office365-Filtering-Correlation-Id: 200e15fe-2277-49a3-93e6-08dd157c3f2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: z32Kn31Z4oA2HO9n440mKw3S7fs6TrY60vDGrgzkXNgrWCClzmrDBoPOFr7Y3Au1UKQXru0U9QPhQwQebZUQvInp6u6kgTQFrMGs2KfeADOnUXI8ke4sduDwmg0yTJHeDKatU4wZlweUUUt3RH5MvQxqxDWxgtKVPdbYpNkCk9TceE2SbuBgJh1BDQuWUHLhBjjgv72y+RHlBZbwF6nVARthEY5UFgeffb7Cb9JWIdwUk8ykoKkIBOamYCfrC1/tZhLiruECsVi2UNXsPDz3PenSoSi51XZi5fVgZXHnqAawLED0QlGwAa/90G1hERgSRd9MCB6pnT2pP+Mk5uObryZwJxinos5lYz8xxszG0fA6nOXTKrwZNPk8R/uUaDUIJh53R06+jpL06nalCwOJy1wUXvaNZV/aeEWQf4G1Ne2zoMdTeXmx2AXn6JVXDGJbbnDFbtTkcchsuFfRP9a1y8HRR4Ht1lh0VzA9AntgCtv+S1DZ8udT0CND0yJNxkNP9qAQQWOUEWvnNWz2tx5PGVc+nH4mlmomYp8P3pu/shBk9goeFs60VyIJUeQ7sqVCS2yYcl69pOI8vi1lF8/pRZZzSsOKuTq3K3gWI1h5BgCvdovwwvEXdn8P+1oIdW+3bzWnbQ39Zsas58d7H+HqLLTO2aQLMu3eH9E6PHXNIcMbb7f0L1tXPse7nB+ZLnpvTuesH3j0NaqbqSSmSU2jeyD8O5wCm7B8o+HXcxBtFNljZK+qnLAbWSB+u2NVwjs1L8ZLXoHrSI4CrzZ8M3ZwJ4A0rtLfe2+WGHj8SVdkBXnh17K3FqRzuBrKlEpC59RhL4nkJq4Jz0xC7GaiZFSWsbrT7t84dWnPBb5BRpenn2gJkqWJivCEZrEEDFlJZdE+3Np9DZJrTLLp8ggdS+1xn3zzYoYIcyJfwjDnpLQQB8+SNa4q6iO13xFrw7jhrkTlmPXrNTKvEMkVfXldd2up8ArJ9pE8YgV9TSdRlgI4NQxOJMiUNyKG7JJQKcCpZk3zLENhxaQLfdB2yP2mL5Tz4Sv74j0uOEi+yR+TluHOnDWcRu0vq8UqepTFuR+Feh7m2AH2zzOfiVf2D3p1uFT+PLPyCwulJDqcGudEsAk8JkRSj1O5m4l6xaG4v5dWBk2P7wsbTfX8RVlOe1UImTg0h1cVBjfC0U69YjMgcs1IbnTa8gCX+x+N6H1n7idOSeSOFGcbYUQ8tzSzBag0vlPYz1mk8GPEH4di5Ua9/omKQfWOWZlu1PDdCYj9jACGo1Pb36JWskCo5yzDBzA82nsg/2BF2xo+H8rp+Vq+XQXQgDHxvELl1J0H/J9iWzRdq5sqxVM8x6DrAzHbAGFLnaWPdaZ39XJaUb/2cd9g+PgUO2OYws1jpf8GCdh56T9jSqEn0ZovRY0tgbx3xbQXKe+6G2ZaGDLFwEvJnh5SPmsDCRO70FxJcIWg8tAc93Kv6nf+ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Dec 2024 22:29:13.5620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 200e15fe-2277-49a3-93e6-08dd157c3f2d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A349.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7348 For Ryzen systems the EPP policy set by the BIOS is generally configured to performance as this is the default register value for the CPPC request MSR. If a user doesn't use additional software to configure EPP then the system will default biased towards performance and consume extra battery. Instead configure the default to "balanced_performance" for this case. Suggested-by: Artem S. Tashkinov Closes: https://bugzilla.kernel.org/show_bug.cgi?id=219526 Signed-off-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index b361e691fd33e..57775839a1c44 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1503,8 +1503,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata); - policy->min = policy->cpuinfo.min_freq; policy->max = policy->cpuinfo.max_freq; @@ -1515,10 +1513,13 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) * the default cpufreq governor is neither powersave nor performance. */ if (amd_pstate_acpi_pm_profile_server() || - amd_pstate_acpi_pm_profile_undefined()) + amd_pstate_acpi_pm_profile_undefined()) { policy->policy = CPUFREQ_POLICY_PERFORMANCE; - else + cpudata->epp_default = amd_pstate_get_epp(cpudata); + } else { policy->policy = CPUFREQ_POLICY_POWERSAVE; + cpudata->epp_default = AMD_CPPC_EPP_BALANCE_PERFORMANCE; + } if (cpu_feature_enabled(X86_FEATURE_CPPC)) { ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); @@ -1531,6 +1532,9 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } + ret = amd_pstate_set_epp(cpudata, cpudata->epp_default); + if (ret) + return ret; current_pstate_driver->adjust_perf = NULL;