From patchwork Thu Dec 5 11:40:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13896174 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62F8020322 for ; Fri, 6 Dec 2024 01:01:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.0.225.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733446874; cv=none; b=M5BgVd64Ci4gp/vn7yYo0dk0wdjHn1IVjD0nUrv/cFizA6zxj0stgUrSDDrJddOfcmW2fS5qjkZkQMQBLwlMUXsnAIDn5IAR+KzNurG7AOgxuhYTbfkmOMQ9otP950MYrmXnjpJ/hPY2axxdztheECkIL4QQoIqMO8dKtbFmZZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733446874; c=relaxed/simple; bh=BZDWQsHtRy44rkEInZidbrfQIqeEZfyRGi0P6saJo4U=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=scRYy29bUnQttnVPKrDsmLZ+1crhL04gk9q/vapuJqy4BY8tT06iVpN/wP1tTbcmDTQlq7Y0s/U+Y4AMxrbQObKJcmztrawZq/dTQJAshN9SHzcYoDPPmu1mL1JS7tFTafoeMccZQvjEu3Qi6Yad1JqpVaU5eDT2b9SZ3oSr07Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com; spf=pass smtp.mailfrom=zhaoxin.com; arc=none smtp.client-ip=210.0.225.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1733446120-086e2312d8235b0001-0c9NHn Received: from ZXSHMBX3.zhaoxin.com (ZXSHMBX3.zhaoxin.com [10.28.252.165]) by mx1.zhaoxin.com with ESMTP id jxbgTCABAZk6K1vs (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Fri, 06 Dec 2024 08:48:40 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXSHMBX1.zhaoxin.com (10.28.252.163) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Fri, 6 Dec 2024 08:48:39 +0800 Received: from ZXSHMBX1.zhaoxin.com ([fe80::3066:e339:e3d6:5264]) by ZXSHMBX1.zhaoxin.com ([fe80::3066:e339:e3d6:5264%7]) with mapi id 15.01.2507.039; Fri, 6 Dec 2024 08:48:39 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from xin.lan (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 5 Dec 2024 19:40:50 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v4 1/3] ACPI/APEI: Add hest_parse_pcie_aer() Date: Thu, 5 Dec 2024 19:40:46 +0800 X-ASG-Orig-Subj: [PATCH v4 1/3] ACPI/APEI: Add hest_parse_pcie_aer() Message-ID: <20241205114048.60291-2-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205114048.60291-1-LeoLiu-oc@zhaoxin.com> References: <20241205114048.60291-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 12/6/2024 8:48:38 AM X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1733446120 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 4332 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.134151 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc The purpose of the function apei_hest_parse_aer() is used to parse and extract register value from HEST PCIe AER structures. This applies to all hardware platforms that has a PCI Express AER structure in HEST. Signed-off-by: LeoLiuoc --- drivers/acpi/apei/hest.c | 77 ++++++++++++++++++++++++++++++++++++++-- include/acpi/apei.h | 17 +++++++++ 2 files changed, 92 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c index 20d757687e3d..13075f5aea25 100644 --- a/drivers/acpi/apei/hest.c +++ b/drivers/acpi/apei/hest.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -132,9 +133,81 @@ static bool is_ghes_assist_struct(struct acpi_hest_header *hest_hdr) return false; } -typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); +#ifdef CONFIG_ACPI_APEI +static bool hest_match_pci_devfn(struct acpi_hest_aer_common *p, + struct pci_dev *dev) +{ + return ACPI_HEST_SEGMENT(p->bus) == pci_domain_nr(dev->bus) && + ACPI_HEST_BUS(p->bus) == dev->bus->number && + p->device == PCI_SLOT(dev->devfn) && + p->function == PCI_FUNC(dev->devfn); +} + +static bool hest_source_is_pcie_aer(struct acpi_hest_header *hest_hdr, + struct pci_dev *dev) +{ + u16 hest_type = hest_hdr->type; + u8 pcie_type = pci_pcie_type(dev); + struct acpi_hest_aer_common *common; + + common = (struct acpi_hest_aer_common *)(hest_hdr + 1); + + switch (hest_type) { + case ACPI_HEST_TYPE_AER_ROOT_PORT: + if (pcie_type != PCI_EXP_TYPE_ROOT_PORT) + return false; + break; + case ACPI_HEST_TYPE_AER_ENDPOINT: + if (pcie_type != PCI_EXP_TYPE_ENDPOINT) + return false; + break; + case ACPI_HEST_TYPE_AER_BRIDGE: + if (pcie_type != PCI_EXP_TYPE_PCI_BRIDGE && + pcie_type != PCI_EXP_TYPE_PCIE_BRIDGE) + return false; + break; + default: + return false; + break; + } + + if (common->flags & ACPI_HEST_GLOBAL) + return true; + + if (hest_match_pci_devfn(common, dev)) + return true; + + return false; +} + +int hest_parse_pcie_aer(struct acpi_hest_header *hest_hdr, void *data) +{ + struct hest_parse_aer_info *info = data; + + if (!hest_source_is_pcie_aer(hest_hdr, info->pci_dev)) + return 0; + + switch (hest_hdr->type) { + case ACPI_HEST_TYPE_AER_ROOT_PORT: + info->hest_aer_root_port = (struct acpi_hest_aer_root *)hest_hdr; + return 1; + break; + case ACPI_HEST_TYPE_AER_ENDPOINT: + info->hest_aer_endpoint = (struct acpi_hest_aer *)hest_hdr; + return 1; + break; + case ACPI_HEST_TYPE_AER_BRIDGE: + info->hest_aer_bridge = (struct acpi_hest_aer_bridge *)hest_hdr; + return 1; + break; + default: + return 0; + break; + } +} +#endif -static int apei_hest_parse(apei_hest_func_t func, void *data) +int apei_hest_parse(apei_hest_func_t func, void *data) { struct acpi_hest_header *hest_hdr; int i, rc, len; diff --git a/include/acpi/apei.h b/include/acpi/apei.h index dc60f7db5524..82d3cdf53e22 100644 --- a/include/acpi/apei.h +++ b/include/acpi/apei.h @@ -23,6 +23,15 @@ enum hest_status { HEST_NOT_FOUND, }; +#ifdef CONFIG_ACPI_APEI +struct hest_parse_aer_info { + struct pci_dev *pci_dev; + struct acpi_hest_aer *hest_aer_endpoint; + struct acpi_hest_aer_root *hest_aer_root_port; + struct acpi_hest_aer_bridge *hest_aer_bridge; +}; +#endif + extern int hest_disable; extern int erst_disable; #ifdef CONFIG_ACPI_APEI_GHES @@ -33,10 +42,18 @@ void __init acpi_ghes_init(void); static inline void acpi_ghes_init(void) { } #endif +typedef int (*apei_hest_func_t)(struct acpi_hest_header *hest_hdr, void *data); +int apei_hest_parse(apei_hest_func_t func, void *data); + #ifdef CONFIG_ACPI_APEI void __init acpi_hest_init(void); +int hest_parse_pcie_aer(struct acpi_hest_header *hest_hdr, void *data); #else static inline void acpi_hest_init(void) { } +static inline int hest_parse_pcie_aer(struct acpi_hest_header *hest_hdr, void *data) +{ + return 0; +} #endif int erst_write(const struct cper_record_header *record); From patchwork Thu Dec 5 11:40:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13896163 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BC071EEF9 for ; Fri, 6 Dec 2024 00:48:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 5 Dec 2024 19:40:51 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v4 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Date: Thu, 5 Dec 2024 19:40:47 +0800 X-ASG-Orig-Subj: [PATCH v4 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Message-ID: <20241205114048.60291-3-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205114048.60291-1-LeoLiu-oc@zhaoxin.com> References: <20241205114048.60291-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 12/6/2024 8:48:41 AM X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1733446123 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1196 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.134151 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification r1.0, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Signed-off-by: LeoLiuoc --- include/uapi/linux/pci_regs.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 1601c7ed5fab..e0581a084fea 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -808,6 +808,9 @@ #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 From patchwork Thu Dec 5 11:40:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LeoLiu-oc X-Patchwork-Id: 13896164 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68F992BCFF for ; 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Thu, 5 Dec 2024 19:40:53 +0800 From: LeoLiu-oc To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v4 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params() Date: Thu, 5 Dec 2024 19:40:48 +0800 X-ASG-Orig-Subj: [PATCH v4 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params() Message-ID: <20241205114048.60291-4-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241205114048.60291-1-LeoLiu-oc@zhaoxin.com> References: <20241205114048.60291-1-LeoLiu-oc@zhaoxin.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Moderation-Data: 12/6/2024 8:48:45 AM X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1733446126 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5221 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.134151 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- From: LeoLiuoc Call the func pci_acpi_program_hest_aer_params() for every PCIe device, the purpose of this function is to extract register value from HEST PCIe AER structures and program them into AER Capabilities. This function applies to all hardware platforms that has a PCI Express AER structure in HEST. Signed-off-by: LeoLiuoc --- drivers/pci/pci-acpi.c | 103 +++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 9 ++++ drivers/pci/probe.c | 1 + 3 files changed, 113 insertions(+) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index af370628e583..6e29af8e6cc4 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "pci.h" /* @@ -806,6 +807,108 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) return -ENODEV; } +#ifdef CONFIG_ACPI_APEI +/* + * program_hest_aer_common() - configure AER common registers for Root Ports, + * Endpoints and PCIe to PCI/PCI-X bridges + */ +static void program_hest_aer_common(struct acpi_hest_aer_common aer_common, + struct pci_dev *dev, int pos) +{ + u32 uncor_mask; + u32 uncor_severity; + u32 cor_mask; + u32 adv_cap; + + uncor_mask = aer_common.uncorrectable_mask; + uncor_severity = aer_common.uncorrectable_severity; + cor_mask = aer_common.correctable_mask; + adv_cap = aer_common.advanced_capabilities; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity); + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask); + pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap); +} + +static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, + struct pci_dev *dev, int pos) +{ + u32 root_err_cmd; + + root_err_cmd = aer_root->root_error_command; + + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd); +} + +static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge, + struct pci_dev *dev, int pos) +{ + u32 uncor_mask2; + u32 uncor_severity2; + u32 adv_cap2; + + uncor_mask2 = hest_aer_bridge->uncorrectable_mask2; + uncor_severity2 = hest_aer_bridge->uncorrectable_severity2; + adv_cap2 = hest_aer_bridge->advanced_capabilities2; + + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2); + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2); +} + +static void program_hest_aer_params(struct hest_parse_aer_info info) +{ + struct pci_dev *dev; + int port_type; + int pos; + struct acpi_hest_aer_root *hest_aer_root; + struct acpi_hest_aer *hest_aer_endpoint; + struct acpi_hest_aer_bridge *hest_aer_bridge; + + dev = info.pci_dev; + port_type = pci_pcie_type(dev); + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (!pos) + return; + + switch (port_type) { + case PCI_EXP_TYPE_ROOT_PORT: + hest_aer_root = info.hest_aer_root_port; + program_hest_aer_common(hest_aer_root->aer, dev, pos); + program_hest_aer_root(hest_aer_root, dev, pos); + break; + case PCI_EXP_TYPE_ENDPOINT: + hest_aer_endpoint = info.hest_aer_endpoint; + program_hest_aer_common(hest_aer_endpoint->aer, dev, pos); + break; + case PCI_EXP_TYPE_PCI_BRIDGE: + hest_aer_bridge = info.hest_aer_bridge; + program_hest_aer_common(hest_aer_bridge->aer, dev, pos); + program_hest_aer_bridge(hest_aer_bridge, dev, pos); + break; + default: + return; + break; + } +} + +int pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + struct hest_parse_aer_info info = { + .pci_dev = dev + }; + + if (!pci_is_pcie(dev)) + return -ENODEV; + + if (apei_hest_parse(hest_parse_pcie_aer, &info) == 1) + program_hest_aer_params(info); + + return 0; +} +#endif + /** * pciehp_is_native - Check whether a hotplug port is handled by the OS * @bridge: Hotplug port to check diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2e40fc63ba31..78bdc121c905 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -897,6 +897,15 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { } static inline void pci_restore_aer_state(struct pci_dev *dev) { } #endif +#ifdef CONFIG_ACPI_APEI +int pci_acpi_program_hest_aer_params(struct pci_dev *dev); +#else +static inline int pci_acpi_program_hest_aer_params(struct pci_dev *dev) +{ + return 0; +} +#endif + #ifdef CONFIG_ACPI bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); int pci_acpi_program_hp_params(struct pci_dev *dev); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2e81ab0f5a25..33b8b46ca554 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2304,6 +2304,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_serr(dev); pci_acpi_program_hp_params(dev); + pci_acpi_program_hest_aer_params(dev); } static void pci_release_capabilities(struct pci_dev *dev)