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Fri, 06 Dec 2024 06:51:59 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 4B66pxNA004130; Fri, 6 Dec 2024 06:51:59 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-chandna-hyd.qualcomm.com [10.147.242.90]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 4B66px12004129; Fri, 06 Dec 2024 06:51:59 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2303763) id 6363E500F44; Fri, 6 Dec 2024 12:21:58 +0530 (+0530) From: Sahil Chandna To: kernel@quicinc.com, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_nkumarsi@quicinc.com, quic_akdwived@quicinc.com, quic_kkotecha@quicinc.com, quic_chandna@quicinc.com Subject: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add industrial mezzanine Date: Fri, 6 Dec 2024 12:21:56 +0530 Message-Id: <20241206065156.2573-1-quic_chandna@quicinc.com> X-Mailer: git-send-email 2.17.1 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: cgkWU0IZdBITAI6amq1kEExpT_1Usf2r X-Proofpoint-GUID: cgkWU0IZdBITAI6amq1kEExpT_1Usf2r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 clxscore=1011 malwarescore=0 suspectscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060047 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The industrial mezzanine kit enhances the capabilities of QCS6490 rb3gen2 core kit. Add support for industrial mezzanine board. Signed-off-by: Sahil Chandna --- arch/arm64/boot/dts/qcom/Makefile | 3 ++ .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 44 +++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6ca8db4b8afe..6fe5a5ccd950 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -111,6 +111,9 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb + +qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo + dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso new file mode 100644 index 000000000000..74f2f782d166 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ +/* + +/dts-v1/; +/plugin/; + +#include "pm7250b.dtsi" +#include "sc7280.dtsi" + +&pm7250b_gpios { + gpio5_tpm_dig_out { + gpio5_dig_out_default: gpio5_dig_out_default { + pins = "gpio5"; + function = "normal"; + power-source = <1>; + output-high; + input-disable; + bias-pull-up; + qcom,drive-strength = <3>; + }; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&spi11 { + status = "okay"; + + st33htpm0: st33htpm@0 { + compatible = "st,st33htpm-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio5_dig_out_default>; + status="okay"; + }; +};