From patchwork Fri Aug 17 14:18:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568779 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98BD7139A for ; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89B832B23A for ; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7E0242B2A2; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3A6702B23A for ; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B0B8E6E634; Fri, 17 Aug 2018 14:03:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 670DE6E62A; Fri, 17 Aug 2018 14:03:35 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194191" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:29 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:44 +0530 Message-Id: <1534515531-20599-2-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 1/8] drm: Add Enhanced Gamma LUT precision structure X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Existing LUT precision structure is having only 16 bit precision. This is not enough for upcoming enhanced hardwares and advance usecases like HDR processing. Hence added a new structure with 32 bit precision values. Also added the code, for extracting the same from values passed from userspace. v4: Rebase Signed-off-by: Uma Shankar Reviewed-by: Alexandru Gheorghe --- drivers/gpu/drm/drm_plane.c | 19 +++++++++++++++++++ include/uapi/drm/drm_mode.h | 15 +++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 6153cbd..cd71fd0 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -430,6 +430,25 @@ void drm_plane_force_disable(struct drm_plane *plane) } EXPORT_SYMBOL(drm_plane_force_disable); +/* + * Added to accommodate enhanced LUT precision. + * Max LUT precision is 32 bits. + */ +uint32_t drm_color_lut_extract_ext(uint32_t user_input, uint32_t bit_precision) +{ + uint32_t val = user_input; + uint32_t max = 0xffffffff >> (32 - bit_precision); + + /* Round only if we're not using full precision. */ + if (bit_precision < 32) { + val += 1UL << (32 - bit_precision - 1); + val >>= 32 - bit_precision; + } + + return clamp_val(val, 0, max); +} +EXPORT_SYMBOL(drm_color_lut_extract_ext); + /** * drm_mode_plane_set_obj_prop - set the value of a property * @plane: drm plane object to set property value for diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 8d67243..874407b 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -629,6 +629,21 @@ struct drm_color_lut { __u16 reserved; }; +/* + * Creating 32 bit palette entries for better data + * precision. This will be required for HDR and + * similar color processing usecases. + */ +struct drm_color_lut_ext { + /* + * Data is U0.32 fixed point format. + */ + __u32 red; + __u32 green; + __u32 blue; + __u32 reserved; +}; + #define DRM_MODE_PAGE_FLIP_EVENT 0x01 #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 #define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4 From patchwork Fri Aug 17 14:18:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80881139A for ; Fri, 17 Aug 2018 14:03:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7005D2B23A for ; Fri, 17 Aug 2018 14:03:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 63CED2B2A2; Fri, 17 Aug 2018 14:03:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 74DB22B23A for ; Fri, 17 Aug 2018 14:03:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DE236E62A; Fri, 17 Aug 2018 14:03:36 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8CE386E62B; Fri, 17 Aug 2018 14:03:35 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194208" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:32 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:45 +0530 Message-Id: <1534515531-20599-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 2/8] drm: Add Plane Degamma properties X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add Plane Degamma as a blob property and plane degamma size as a range property. v2: Rebase v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested by Daniel, Vetter. v4: Rebase Signed-off-by: Uma Shankar Reviewed-by: Alexandru Gheorghe --- Documentation/gpu/drm-kms.rst | 9 +++++++++ drivers/gpu/drm/drm_atomic.c | 13 +++++++++++++ drivers/gpu/drm/drm_atomic_helper.c | 6 ++++++ drivers/gpu/drm/drm_plane.c | 35 +++++++++++++++++++++++++++++++++++ include/drm/drm_plane.h | 24 ++++++++++++++++++++++++ 5 files changed, 87 insertions(+) diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 5dee6b8..8b10b12 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -551,6 +551,15 @@ Color Management Properties .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c :export: +Plane Color Management Properties +--------------------------- + +.. kernel-doc:: drivers/gpu/drm/drm_plane.c + :doc: degamma_lut_property + +.. kernel-doc:: drivers/gpu/drm/drm_plane.c + :doc: degamma_lut_size_property + Tile Group Property ------------------- diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 3eb061e..f8cad9b 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -857,6 +857,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, { struct drm_device *dev = plane->dev; struct drm_mode_config *config = &dev->mode_config; + bool replaced = false; + int ret; if (property == config->prop_fb_id) { struct drm_framebuffer *fb = drm_framebuffer_lookup(dev, NULL, val); @@ -908,6 +910,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->color_encoding = val; } else if (property == plane->color_range_property) { state->color_range = val; + } else if (property == plane->degamma_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->degamma_lut, + val, -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (plane->funcs->atomic_set_property) { return plane->funcs->atomic_set_property(plane, state, property, val); @@ -976,6 +985,9 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, *val = state->color_encoding; } else if (property == plane->color_range_property) { *val = state->color_range; + } else if (property == plane->degamma_lut_property) { + *val = (state->degamma_lut) ? + state->degamma_lut->base.id : 0; } else if (plane->funcs->atomic_get_property) { return plane->funcs->atomic_get_property(plane, state, property, val); } else { @@ -1116,6 +1128,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, drm_get_color_encoding_name(state->color_encoding)); drm_printf(p, "\tcolor-range=%s\n", drm_get_color_range_name(state->color_range)); + drm_printf(p, "\tcolor_mgmt_changed=%d\n", state->color_mgmt_changed); if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 38ce9a3..67c5b51 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3613,6 +3613,10 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, state->fence = NULL; state->commit = NULL; + + if (state->degamma_lut) + drm_property_blob_get(state->degamma_lut); + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); @@ -3657,6 +3661,8 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) if (state->commit) drm_crtc_commit_put(state->commit); + + drm_property_blob_put(state->degamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index cd71fd0..03e0560 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -478,6 +478,41 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane, } EXPORT_SYMBOL(drm_mode_plane_set_obj_prop); +/** + * DOC: degamma_lut_property + * + * degamma_lut_property: + * Blob property which allows a userspace to provide LUT values + * to apply degamma curve using the h/w plane degamma processing + * engine, thereby making the content as linear for further color + * processing. + * + * degamma_lut_size_property: + * Range Property to indicate size of the plane degamma LUT. + */ +int drm_plane_color_create_prop(struct drm_device *dev, + struct drm_plane *plane) +{ + struct drm_property *prop; + + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, + "PLANE_DEGAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + plane->degamma_lut_property = prop; + + prop = drm_property_create_range(dev, + DRM_MODE_PROP_IMMUTABLE, + "PLANE_DEGAMMA_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + plane->degamma_lut_size_property = prop; + + return 0; +} +EXPORT_SYMBOL(drm_plane_color_create_prop); + int drm_mode_getplane_res(struct drm_device *dev, void *data, struct drm_file *file_priv) { diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 8a152dc..28357ac 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -174,6 +174,14 @@ struct drm_plane_state { */ bool visible; + /* @degamma_lut: + * + * Lookup table for converting framebuffer pixel data before apply the + * color conversion matrix @ctm. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *degamma_lut; + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. @@ -184,6 +192,8 @@ struct drm_plane_state { /** @state: backpointer to global drm_atomic_state */ struct drm_atomic_state *state; + + u8 color_mgmt_changed : 1; }; static inline struct drm_rect @@ -676,6 +686,18 @@ struct drm_plane { * See drm_plane_create_color_properties(). */ struct drm_property *color_range_property; + + /** + * @degamma_lut_property: Optional Plane property to set the LUT + * used to convert the framebuffer's colors to linear gamma. + */ + struct drm_property *degamma_lut_property; + + /** + * @degamma_lut_size_property: Optional Plane property for the + * size of the degamma LUT as supported by the driver (read-only). + */ + struct drm_property *degamma_lut_size_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) @@ -725,6 +747,8 @@ static inline u32 drm_plane_mask(const struct drm_plane *plane) int drm_mode_plane_set_obj_prop(struct drm_plane *plane, struct drm_property *property, uint64_t value); +int drm_plane_color_create_prop(struct drm_device *dev, + struct drm_plane *plane); /** * drm_plane_find - find a &drm_plane From patchwork Fri Aug 17 14:18:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568789 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F233D14BD for ; Fri, 17 Aug 2018 14:03:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E203B2B23A for ; Fri, 17 Aug 2018 14:03:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D63AB2B2A2; Fri, 17 Aug 2018 14:03:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7C9892B23A for ; Fri, 17 Aug 2018 14:03:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 687216E646; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 498106E636; Fri, 17 Aug 2018 14:03:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194224" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:35 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:46 +0530 Message-Id: <1534515531-20599-4-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 3/8] drm: Add Plane CTM property X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add a blob property for plane CSC usage. v2: Rebase v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested by Daniel, Vetter. v4: Rebase Signed-off-by: Uma Shankar Reviewed-by: Alexandru Gheorghe --- Documentation/gpu/drm-kms.rst | 3 +++ drivers/gpu/drm/drm_atomic.c | 10 ++++++++++ drivers/gpu/drm/drm_atomic_helper.c | 4 ++++ drivers/gpu/drm/drm_plane.c | 12 ++++++++++++ include/drm/drm_plane.h | 15 +++++++++++++++ 5 files changed, 44 insertions(+) diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 8b10b12..16d6d8d 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -560,6 +560,9 @@ Plane Color Management Properties .. kernel-doc:: drivers/gpu/drm/drm_plane.c :doc: degamma_lut_size_property +.. kernel-doc:: drivers/gpu/drm/drm_plane.c + :doc: ctm_property + Tile Group Property ------------------- diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index f8cad9b..ddda935 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -917,6 +917,14 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->ctm_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->ctm, + val, + sizeof(struct drm_color_ctm), -1, + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (plane->funcs->atomic_set_property) { return plane->funcs->atomic_set_property(plane, state, property, val); @@ -988,6 +996,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, } else if (property == plane->degamma_lut_property) { *val = (state->degamma_lut) ? state->degamma_lut->base.id : 0; + } else if (property == plane->ctm_property) { + *val = (state->ctm) ? state->ctm->base.id : 0; } else if (plane->funcs->atomic_get_property) { return plane->funcs->atomic_get_property(plane, state, property, val); } else { diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 67c5b51..866181f 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3616,6 +3616,9 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, if (state->degamma_lut) drm_property_blob_get(state->degamma_lut); + if (state->ctm) + drm_property_blob_get(state->ctm); + state->color_mgmt_changed = false; } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); @@ -3663,6 +3666,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_crtc_commit_put(state->commit); drm_property_blob_put(state->degamma_lut); + drm_property_blob_put(state->ctm); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 03e0560..97520b1 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -489,6 +489,11 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane, * * degamma_lut_size_property: * Range Property to indicate size of the plane degamma LUT. + * + * ctm_property: + * Blob property which allows a userspace to provide CTM coefficients + * to do color space conversion or any other enhancement by doing a + * matrix multiplication using the h/w CTM processing engine */ int drm_plane_color_create_prop(struct drm_device *dev, struct drm_plane *plane) @@ -509,6 +514,13 @@ int drm_plane_color_create_prop(struct drm_device *dev, return -ENOMEM; plane->degamma_lut_size_property = prop; + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, + "PLANE_CTM", 0); + if (!prop) + return -ENOMEM; + plane->ctm_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_color_create_prop); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 28357ac..5143277 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -183,6 +183,14 @@ struct drm_plane_state { struct drm_property_blob *degamma_lut; /** + * @ctm: + * + * Color transformation matrix. See drm_plane_enable_color_mgmt(). The + * blob (if not NULL) is a &struct drm_color_ctm. + */ + struct drm_property_blob *ctm; + + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. * @@ -698,6 +706,13 @@ struct drm_plane { * size of the degamma LUT as supported by the driver (read-only). */ struct drm_property *degamma_lut_size_property; + + /** + * @plane_ctm_property: Optional Plane property to set the + * matrix used to convert colors after the lookup in the + * degamma LUT. + */ + struct drm_property *ctm_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) From patchwork Fri Aug 17 14:18:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568787 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A6E3C139A for ; Fri, 17 Aug 2018 14:03:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 963212B23A for ; Fri, 17 Aug 2018 14:03:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 89C4B2B2A2; Fri, 17 Aug 2018 14:03:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1AF912B23A for ; Fri, 17 Aug 2018 14:03:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 514486E645; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 385176E643; Fri, 17 Aug 2018 14:03:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194249" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:38 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:47 +0530 Message-Id: <1534515531-20599-5-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 4/8] drm: Add Plane Gamma properties X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Add plane gamma as blob property and size as a range property. v2: Rebase v3: Fixed Sean, Paul's review comments. Moved the property from mode_config to drm_plane. Created a helper function to instantiate these properties and removed from drm_mode_create_standard_properties Added property documentation as suggested by Daniel, Vetter. v4: Rebase Signed-off-by: Uma Shankar Reviewed-by: Alexandru Gheorghe --- Documentation/gpu/drm-kms.rst | 6 ++++++ drivers/gpu/drm/drm_atomic.c | 9 +++++++++ drivers/gpu/drm/drm_atomic_helper.c | 3 +++ drivers/gpu/drm/drm_plane.c | 23 +++++++++++++++++++++++ include/drm/drm_plane.h | 22 ++++++++++++++++++++++ 5 files changed, 63 insertions(+) diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 16d6d8d..bcf9a86 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -563,6 +563,12 @@ Plane Color Management Properties .. kernel-doc:: drivers/gpu/drm/drm_plane.c :doc: ctm_property +.. kernel-doc:: drivers/gpu/drm/drm_plane.c + :doc: gamma_lut_property + +.. kernel-doc:: drivers/gpu/drm/drm_plane.c + :doc: gamma_lut_size_property + Tile Group Property ------------------- diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index ddda935..8b0bf14 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -925,6 +925,13 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, &replaced); state->color_mgmt_changed |= replaced; return ret; + } else if (property == plane->gamma_lut_property) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->gamma_lut, + val, -1, sizeof(struct drm_color_lut), + &replaced); + state->color_mgmt_changed |= replaced; + return ret; } else if (plane->funcs->atomic_set_property) { return plane->funcs->atomic_set_property(plane, state, property, val); @@ -998,6 +1005,8 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, state->degamma_lut->base.id : 0; } else if (property == plane->ctm_property) { *val = (state->ctm) ? state->ctm->base.id : 0; + } else if (property == plane->gamma_lut_property) { + *val = (state->gamma_lut) ? state->gamma_lut->base.id : 0; } else if (plane->funcs->atomic_get_property) { return plane->funcs->atomic_get_property(plane, state, property, val); } else { diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 866181f..f524255 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -3618,6 +3618,8 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, drm_property_blob_get(state->degamma_lut); if (state->ctm) drm_property_blob_get(state->ctm); + if (state->gamma_lut) + drm_property_blob_put(state->gamma_lut); state->color_mgmt_changed = false; } @@ -3667,6 +3669,7 @@ void __drm_atomic_helper_plane_destroy_state(struct drm_plane_state *state) drm_property_blob_put(state->degamma_lut); drm_property_blob_put(state->ctm); + drm_property_blob_put(state->gamma_lut); } EXPORT_SYMBOL(__drm_atomic_helper_plane_destroy_state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 97520b1..d0bf10b 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -494,6 +494,15 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane, * Blob property which allows a userspace to provide CTM coefficients * to do color space conversion or any other enhancement by doing a * matrix multiplication using the h/w CTM processing engine + * + * gamma_lut_property: + * Blob property which allows a userspace to provide LUT values + * to apply gamma/tone-mapping curve using the h/w plane gamma + * processing engine, thereby making the content as non-linear + * or to perform any tone mapping operation for HDR usecases. + * + * gamma_lut_size_property: + * Range Property to indicate size of the plane gamma LUT. */ int drm_plane_color_create_prop(struct drm_device *dev, struct drm_plane *plane) @@ -521,6 +530,20 @@ int drm_plane_color_create_prop(struct drm_device *dev, return -ENOMEM; plane->ctm_property = prop; + prop = drm_property_create(dev, + DRM_MODE_PROP_BLOB, + "PLANE_GAMMA_LUT", 0); + if (!prop) + return -ENOMEM; + plane->gamma_lut_property = prop; + + prop = drm_property_create_range(dev, + DRM_MODE_PROP_IMMUTABLE, + "PLANE_GAMMA_LUT_SIZE", 0, UINT_MAX); + if (!prop) + return -ENOMEM; + plane->gamma_lut_size_property = prop; + return 0; } EXPORT_SYMBOL(drm_plane_color_create_prop); diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 5143277..fb466b1 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -191,6 +191,15 @@ struct drm_plane_state { struct drm_property_blob *ctm; /** + * @gamma_lut: + * + * Lookup table for converting pixel data after the color conversion + * matrix @ctm. See drm_plane_enable_color_mgmt(). The blob (if not + * NULL) is an array of &struct drm_color_lut_ext. + */ + struct drm_property_blob *gamma_lut; + + /** * @commit: Tracks the pending commit to prevent use-after-free conditions, * and for async plane updates. * @@ -713,6 +722,19 @@ struct drm_plane { * degamma LUT. */ struct drm_property *ctm_property; + + /** + * @plane_gamma_lut_property: Optional Plane property to set the LUT + * used to convert the colors, after the CTM matrix, to the common + * gamma space chosen for blending. + */ + struct drm_property *gamma_lut_property; + + /** + * @plane_gamma_lut_size_property: Optional Plane property for the size + * of the gamma LUT as supported by the driver (read-only). + */ + struct drm_property *gamma_lut_size_property; }; #define obj_to_plane(x) container_of(x, struct drm_plane, base) From patchwork Fri Aug 17 14:18:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DFC7614BD for ; Fri, 17 Aug 2018 14:03:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF4552B24F for ; Fri, 17 Aug 2018 14:03:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C01742B23A; Fri, 17 Aug 2018 14:03:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6EC252B23A for ; Fri, 17 Aug 2018 14:03:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 35A176E649; Fri, 17 Aug 2018 14:03:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 27C386E644; Fri, 17 Aug 2018 14:03:44 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194271" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:41 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:48 +0530 Message-Id: <1534515531-20599-6-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 5/8] drm: Define helper function for plane color enabling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Define helper function to enable Plane color features to attach plane color properties to plane structure. v2: Rebase v3: Modiefied the function to use updated property names. v4: Rebase Signed-off-by: Uma Shankar Reviewed-by: Alexandru Gheorghe --- drivers/gpu/drm/drm_plane.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/drm/drm_color_mgmt.h | 5 +++++ 2 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index d0bf10b..d1b4ac1 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -144,6 +144,48 @@ static int create_in_format_blob(struct drm_device *dev, struct drm_plane *plane } /** + * drm_plane_enable_color_mgmt - enable color management properties + * @plane: DRM Plane + * @plane_degamma_lut_size: the size of the degamma lut (before CSC) + * @plane_has_ctm: whether to attach ctm_property for CSC matrix + * @plane_gamma_lut_size: the size of the gamma lut (after CSC) + * + * This function lets the driver enable the color correction + * properties on a plane. This includes 3 degamma, csc and gamma + * properties that userspace can set and 2 size properties to inform + * the userspace of the lut sizes. Each of the properties are + * optional. The gamma and degamma properties are only attached if + * their size is not 0 and ctm_property is only attached if has_ctm is + * true. + */ +void drm_plane_enable_color_mgmt(struct drm_plane *plane, + uint plane_degamma_lut_size, + bool plane_has_ctm, + uint plane_gamma_lut_size) +{ + if (plane_degamma_lut_size) { + drm_object_attach_property(&plane->base, + plane->degamma_lut_property, 0); + drm_object_attach_property(&plane->base, + plane->degamma_lut_size_property, + plane_degamma_lut_size); + } + + if (plane_has_ctm) + drm_object_attach_property(&plane->base, + plane->ctm_property, 0); + + if (plane_gamma_lut_size) { + drm_object_attach_property(&plane->base, + plane->gamma_lut_property, 0); + drm_object_attach_property(&plane->base, + plane->gamma_lut_size_property, + plane_gamma_lut_size); + } +} +EXPORT_SYMBOL(drm_plane_enable_color_mgmt); + +/** * drm_universal_plane_init - Initialize a new universal plane object * @dev: DRM device * @plane: plane object to init diff --git a/include/drm/drm_color_mgmt.h b/include/drm/drm_color_mgmt.h index 44f04233..9b8e566 100644 --- a/include/drm/drm_color_mgmt.h +++ b/include/drm/drm_color_mgmt.h @@ -68,4 +68,9 @@ int drm_plane_create_color_properties(struct drm_plane *plane, u32 supported_ranges, enum drm_color_encoding default_encoding, enum drm_color_range default_range); + +void drm_plane_enable_color_mgmt(struct drm_plane *plane, + uint plane_degamma_lut_size, + bool plane_has_ctm, + uint plane_gamma_lut_size); #endif From patchwork Fri Aug 17 14:18:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E0CA14BD for ; Fri, 17 Aug 2018 14:04:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DEE82B24F for ; Fri, 17 Aug 2018 14:04:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 21C532BB07; Fri, 17 Aug 2018 14:04:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CD32E2B24F for ; Fri, 17 Aug 2018 14:04:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E7476E655; Fri, 17 Aug 2018 14:03:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1970A6E647; Fri, 17 Aug 2018 14:03:47 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194281" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:44 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:49 +0530 Message-Id: <1534515531-20599-7-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 6/8] drm/i915: Enable plane color features X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Enable and initialize plane color features. v2: Rebase and some cleanup v3: Updated intel_plane_color_init to call drm_plane_color_create_prop function, which will in turn create plane color properties. v4: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_drv.h | 5 +++++ drivers/gpu/drm/i915/intel_color.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_device_info.h | 5 +++++ drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ 4 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5fa1388..dddb1c3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -455,6 +455,11 @@ struct drm_i915_display_funcs { void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); void (*load_luts)(struct drm_crtc_state *crtc_state); + /* Add Plane Color callbacks */ + void (*load_plane_csc_matrix)(const struct drm_plane_state + *plane_state); + void (*load_plane_luts)(const struct drm_plane_state + *plane_state); }; #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index c6a7bea..fb8402f 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -642,6 +642,20 @@ int intel_color_check(struct drm_crtc *crtc, return -EINVAL; } +void intel_plane_color_init(struct drm_plane *plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->dev); + + drm_plane_color_create_prop(plane->dev, plane); + + /* Enable color management support when we have degamma & gamma LUTs. */ + if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 && + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) + drm_plane_enable_color_mgmt(plane, + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size, + true, INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size); +} + void intel_color_init(struct drm_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 6eecd64..71132ad 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -182,6 +182,11 @@ struct intel_device_info { u16 degamma_lut_size; u16 gamma_lut_size; } color; + + struct plane_color_luts { + u16 plane_degamma_lut_size; + u16 plane_gamma_lut_size; + } plane_color; }; struct intel_driver_caps { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 7b984ae..3850a5b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -535,6 +535,14 @@ struct intel_plane_state { */ int scaler_id; + /* + * Use reduced/limited/broadcast rbg range, compressing from the full + * range fed into the crtcs. + */ + bool limited_color_range; + /* Gamma mode programmed on the plane */ + uint32_t gamma_mode; + struct drm_intel_sprite_colorkey ckey; }; @@ -2170,6 +2178,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state); void intel_color_set_csc(struct drm_crtc_state *crtc_state); void intel_color_load_luts(struct drm_crtc_state *crtc_state); +void intel_plane_color_init(struct drm_plane *plane); /* intel_lspcon.c */ bool lspcon_init(struct intel_digital_port *intel_dig_port); From patchwork Fri Aug 17 14:18:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9C3EC14BD for ; Fri, 17 Aug 2018 14:04:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D5F52B23A for ; Fri, 17 Aug 2018 14:04:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 815512BAE3; Fri, 17 Aug 2018 14:04:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1416C2B23A for ; Fri, 17 Aug 2018 14:04:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B2A66E652; Fri, 17 Aug 2018 14:03:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12B416E647; Fri, 17 Aug 2018 14:03:50 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194290" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:47 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:50 +0530 Message-Id: <1534515531-20599-8-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 7/8] drm/i915: Implement Plane Gamma for Bdw and Gen9 platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Implement Plane Gamma feature for BDW and Gen9 platforms. v2: Used newly added drm_color_lut_ext structure for enhanced precision for Gamma LUT entries. v3: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_pci.c | 5 +++- drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++ drivers/gpu/drm/i915/intel_color.c | 58 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_display.c | 4 +++ drivers/gpu/drm/i915/intel_sprite.c | 4 +++ 5 files changed, 95 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e931b48..40de78c 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -54,7 +54,10 @@ .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } #define BDW_COLORS \ - .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } + .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \ + .plane_color = { .plane_degamma_lut_size = 0, \ + .plane_gamma_lut_size = 16 } + #define CHV_COLORS \ .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } #define GLK_COLORS \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0c9f03d..2db6a84 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -172,6 +172,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) +/* Plane Gamma Registers */ +#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) +#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) + #define __MASKED_FIELD(mask, value) ((mask) << 16 | (value)) #define _MASKED_FIELD(mask, value) ({ \ if (__builtin_constant_p(mask)) \ @@ -9713,6 +9717,27 @@ enum skl_power_gate { #define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A, _PRE_CSC_GAMC_INDEX_B) #define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B) +/* Plane Gamma in Gen9+ */ +#define _PLANE_GAMC_1_A 0x701d0 +#define _PLANE_GAMC_1_B 0x711d0 +#define _PLANE_GAMC_2_A 0x702d0 +#define _PLANE_GAMC_2_B 0x712d0 +#define _PLANE_GAMC_1(pipe) _PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B) +#define _PLANE_GAMC_2(pipe) _PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B) +#define PLANE_GAMC(pipe, plane, i) \ + _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe)) + +#define _PLANE_GAMC16_1_A 0x70210 +#define _PLANE_GAMC16_1_B 0x71210 +#define _PLANE_GAMC16_2_A 0x70310 +#define _PLANE_GAMC16_2_B 0x71310 +#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \ + _PLANE_GAMC16_1_B) +#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \ + _PLANE_GAMC16_2_B) +#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \ + _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe)) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index fb8402f..2b5c0cd 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -492,6 +492,59 @@ static void broadwell_load_luts(struct drm_crtc_state *state) I915_WRITE(PREC_PAL_INDEX(pipe), 0); } +static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state, + u32 offset) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + enum pipe pipe = to_intel_plane(state->plane)->pipe; + enum plane_id plane = to_intel_plane(state->plane)->id; + uint32_t i, lut_size = + INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size; + + if (state->gamma_lut) { + struct drm_color_lut_ext *lut = + (struct drm_color_lut_ext *) state->gamma_lut->data; + + for (i = 0; i < lut_size; i++) { + uint32_t word = + (drm_color_lut_extract(lut[i].red, 10) << 20) | + (drm_color_lut_extract(lut[i].green, 10) << 10) | + drm_color_lut_extract(lut[i].blue, 10); + + I915_WRITE(PLANE_GAMC(pipe, plane, i), word); + } + + /* Program the max register to clamp values > 1.0. */ + i = lut_size - 1; + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), + drm_color_lut_extract(lut[i].red, 16)); + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), + drm_color_lut_extract(lut[i].green, 16)); + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), + drm_color_lut_extract(lut[i].blue, 16)); + } else { + for (i = 0; i < lut_size; i++) { + uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); + + I915_WRITE(PLANE_GAMC(pipe, plane, i), + (v << 20) | (v << 10) | v); + } + + I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1); + I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1); + I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1); + } +} + +/* Loads the palette/gamma unit for the CRTC on Broadwell+. */ +static void broadwell_load_plane_luts(const struct drm_plane_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->plane->dev); + + bdw_load_plane_gamma_lut(state, + INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size); +} + static void glk_load_degamma_lut(struct drm_crtc_state *state) { struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); @@ -648,6 +701,11 @@ void intel_plane_color_init(struct drm_plane *plane) drm_plane_color_create_prop(plane->dev, plane); + if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || + IS_BROXTON(dev_priv)) { + dev_priv->display.load_plane_luts = broadwell_load_plane_luts; + } + /* Enable color management support when we have degamma & gamma LUTs. */ if (INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size != 0 && INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size != 0) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 690e1e8..2d15ac2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -13803,6 +13803,10 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv, DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); + /* Add Plane Color properties */ + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + intel_plane_color_init(&primary->base); + drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); return primary; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f7026e8..0eeb1d3 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1650,6 +1650,10 @@ struct intel_plane * DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE); + /* Add Plane Color properties */ + if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + intel_plane_color_init(&intel_plane->base); + drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); return intel_plane; From patchwork Fri Aug 17 14:18:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10568805 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0A53D139A for ; Fri, 17 Aug 2018 14:04:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE46F2B24F for ; Fri, 17 Aug 2018 14:04:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E24EA2BB07; Fri, 17 Aug 2018 14:04:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 99DAA2B24F for ; Fri, 17 Aug 2018 14:04:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C13A6E651; Fri, 17 Aug 2018 14:03:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 03C666E651; Fri, 17 Aug 2018 14:03:52 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 07:03:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,251,1531810800"; d="scan'208";a="82194302" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.25.28]) by fmsmga001.fm.intel.com with ESMTP; 17 Aug 2018 07:03:50 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Fri, 17 Aug 2018 19:48:51 +0530 Message-Id: <1534515531-20599-9-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> References: <1534515531-20599-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [RFC v4 8/8] drm/i915: Load plane color luts from atomic flip X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dcastagna@chromium.org, seanpaul@chromium.org, ville.syrjala@intel.com, harry.wentland@amd.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Load plane color luts as part of atomic plane updates. This will be done only if the plane color luts are changed. v4: Rebase Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_atomic_plane.c | 4 ++++ drivers/gpu/drm/i915/intel_color.c | 8 ++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index dcba645..abc9051 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -224,6 +224,10 @@ static void intel_plane_atomic_update(struct drm_plane *plane, intel_atomic_get_new_plane_state(state, intel_plane); struct drm_crtc *crtc = new_plane_state->base.crtc ?: old_state->crtc; + if (new_plane_state->base.color_mgmt_changed) { + intel_color_load_plane_luts(&new_plane_state->base); + } + if (new_plane_state->base.visible) { const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, to_intel_crtc(crtc)); diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 2b5c0cd..de28d6b 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -666,6 +666,14 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state) dev_priv->display.load_luts(crtc_state); } +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state) +{ + struct drm_device *dev = plane_state->plane->dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + dev_priv->display.load_plane_luts(plane_state); +} + int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3850a5b..fea772b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2179,6 +2179,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ void intel_color_set_csc(struct drm_crtc_state *crtc_state); void intel_color_load_luts(struct drm_crtc_state *crtc_state); void intel_plane_color_init(struct drm_plane *plane); +void intel_color_load_plane_luts(const struct drm_plane_state *plane_state); /* intel_lspcon.c */ bool lspcon_init(struct intel_digital_port *intel_dig_port);