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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.36.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:36:58 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 01/11] hvf: Add facility for initialisation code prior to first vCPU run Date: Mon, 9 Dec 2024 21:36:19 +0100 Message-Id: <20241209203629.74436-2-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::62a; envelope-from=phil@philjordan.eu; helo=mail-ej1-x62a.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan Some VM state required for fully configuring vCPUs is only available after all devices have been through their init phase. This extra function, called just before each vCPU makes its first VM entry, allows us to perform such architecture-specific initialisation. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Alexander Graf --- accel/hvf/hvf-accel-ops.c | 5 +++++ include/sysemu/hvf_int.h | 1 + target/arm/hvf/hvf.c | 4 ++++ target/i386/hvf/hvf.c | 4 ++++ 4 files changed, 14 insertions(+) diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index d60874d3e6..c17a9a10de 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -442,6 +442,11 @@ static void *hvf_cpu_thread_fn(void *arg) cpu_thread_signal_created(cpu); qemu_guest_random_seed_thread_part2(cpu->random_seed); + if (!cpu_can_run(cpu)) { + qemu_wait_io_event(cpu); + } + hvf_vcpu_before_first_run(cpu); + do { if (cpu_can_run(cpu)) { r = hvf_vcpu_exec(cpu); diff --git a/include/sysemu/hvf_int.h b/include/sysemu/hvf_int.h index 42ae18433f..2775bd82d7 100644 --- a/include/sysemu/hvf_int.h +++ b/include/sysemu/hvf_int.h @@ -67,6 +67,7 @@ const char *hvf_return_string(hv_return_t ret); int hvf_arch_init(void); hv_return_t hvf_arch_vm_create(MachineState *ms, uint32_t pa_range); int hvf_arch_init_vcpu(CPUState *cpu); +void hvf_vcpu_before_first_run(CPUState *cpu); void hvf_arch_vcpu_destroy(CPUState *cpu); int hvf_vcpu_exec(CPUState *); hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index ca7ea92774..0b334c268e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1061,6 +1061,10 @@ int hvf_arch_init_vcpu(CPUState *cpu) return 0; } +void hvf_vcpu_before_first_run(CPUState *cpu) +{ +} + void hvf_kick_vcpu_thread(CPUState *cpu) { cpus_kick_thread(cpu); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index c5d025d557..3b6ee79fb2 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -338,6 +338,10 @@ int hvf_arch_init_vcpu(CPUState *cpu) return 0; } +void hvf_vcpu_before_first_run(CPUState *cpu) +{ +} + static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) { X86CPU *x86_cpu = X86_CPU(cpu); From patchwork Mon Dec 9 20:36:20 2024 Content-Type: text/plain; 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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.36.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:36:59 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 02/11] arm/hvf: Initialise GICv3 state just before first vCPU run Date: Mon, 9 Dec 2024 21:36:20 +0100 Message-Id: <20241209203629.74436-3-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::629; envelope-from=phil@philjordan.eu; helo=mail-ej1-x629.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan Initialising the vCPU PFR0_EL1 system register with the GIC flag in hvf_arch_init_vcpu() does not actually work because the GIC state is not yet available at that time. If we set this flag just before running each vCPU for the first time, the GIC will definitely be fully initialised at that point. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Alexander Graf --- target/arm/hvf/hvf.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0b334c268e..bc431f25cc 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -993,7 +993,6 @@ int hvf_arch_init_vcpu(CPUState *cpu) CPUARMState *env = &arm_cpu->env; uint32_t sregs_match_len = ARRAY_SIZE(hvf_sreg_match); uint32_t sregs_cnt = 0; - uint64_t pfr; hv_return_t ret; int i; @@ -1042,12 +1041,6 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->mp_affinity); assert_hvf_ok(ret); - ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); - assert_hvf_ok(ret); - pfr |= env->gicv3state ? (1 << 24) : 0; - ret = hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, pfr); - assert_hvf_ok(ret); - /* We're limited to underlying hardware caps, override internal versions */ ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64MMFR0_EL1, &arm_cpu->isar.id_aa64mmfr0); @@ -1063,6 +1056,16 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_vcpu_before_first_run(CPUState *cpu) { + uint64_t pfr; + hv_return_t ret; + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + + ret = hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_ID_AA64PFR0_EL1, &pfr); + assert_hvf_ok(ret); + pfr |= env->gicv3state ? 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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:00 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 03/11] i386/hvf: Don't send signal to thread when kicking Date: Mon, 9 Dec 2024 21:36:21 +0100 Message-Id: <20241209203629.74436-4-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::636; envelope-from=phil@philjordan.eu; helo=mail-ej1-x636.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan This seems to be entirely superfluous and is costly enough to show up in profiling. hv_vcpu_interrupt() has been demonstrated to very reliably cause VM exits - even if the target vCPU isn't even running, it will immediately exit on entry. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/hvf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 3b6ee79fb2..936c31dbdd 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -214,7 +214,7 @@ static inline bool apic_bus_freq_is_known(CPUX86State *env) void hvf_kick_vcpu_thread(CPUState *cpu) { - cpus_kick_thread(cpu); + cpu->thread_kicked = true; hv_vcpu_interrupt(&cpu->accel->fd, 1); } From patchwork Mon Dec 9 20:36:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900370 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D3E97E7717D for ; Mon, 9 Dec 2024 20:37:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tKkVB-0006Gl-Md; Mon, 09 Dec 2024 15:37:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tKkV7-0006De-W5 for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:06 -0500 Received: from mail-ej1-x634.google.com ([2a00:1450:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tKkV5-0003DC-IA for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:05 -0500 Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-aa560a65fd6so870330866b.0 for ; Mon, 09 Dec 2024 12:37:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1733776622; x=1734381422; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hi0SZTNhz11ho3vCY2FYS+EKuGIwlKWvrSV2lPVozDU=; b=LytLI0b4iJMT6mfRLDoHGMDH0C/XjYWsXujFYX1U/r/nifkvCkEQrUpeSjpEynhl5w Rsw8EIEnoTSjoODXWu0r7B538DG+pUEYzUib68JvFku+aO/NBQnU/iJ5jyljwwyTHsbj XsBmgSilDfCx+17WxR9GPNvMpkm7Syd/MURkGTjk2Z1qhTdslzolfu9R1kmtCSI0fpTs H4Oz4WyrA8YSghBAC3P2LFwzEvXlltk9dqGTLGuVEwx+OU8weo1fjLIvznbYML+vc/mn sP8e98AtqT/FQlTOtiXzDvODgmWtGKfxMv7ZZPgibqvwJHxsR6INqVTx2806Qgx9vojs N9MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733776622; x=1734381422; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hi0SZTNhz11ho3vCY2FYS+EKuGIwlKWvrSV2lPVozDU=; b=mklPMLx4q8YKAPKYF+9UIcee5uzOIOOpyr6cigUKsZKJI9USR8Q0VWaMLUkvkA/iY1 WpKhgCzwBBZ0feGcHXl8/tab6QlwndPd45v8GSa2CH8YjWPySVka4CbqkGXjM1lI4vvk ilYSXDsc/BpnH2x8MZ6i/oow9D1vmr6SEriVyl23shlp61DoKZ3tf3P30+5l6o0prqfA eh41uYocxnQiw4ml2yLT2DnlE5adi1DOsbNLfxWE1w2pgk02hPfLhML8TO4uCSNmSpNg 5KqeddzYOoNVc8hAx6VxmzcSbeGzB1qeFY5soSxjyUnXqsz7fcYp6v2dm6RoaEFuip6l 8r3A== X-Gm-Message-State: AOJu0YxWUTyGCbtgGtb6X7f30vZuT0TivWAVAYvhFpOvzK/anPPvvOjs N1xGo5ZRq8kTPzA3uFcbL7AcFUSenGZdaK03lRrIagWld02V8DQjsoLq6+hfOb58h42CqFGk7ft OZw== X-Gm-Gg: ASbGncsAxUhc1YAvOd1NzHjsvrDCp+mWmtCAH7oZYFzzSKSoive3+3+G9yP/5WxczmZ vgtba7CRxET9ZN0kXClTkoT/BRpXzrgo6JxIE78i/UKubuTJtH98sJck1bsCkU0Se0sZXHveoBK p6AjnjNM4HlzamF5p6m/rMWRypXuKgoRxAaADOUJGpcaUlWtgBld83v1/57gr0FUMlBKB1bWgUj CCVUOyUjEyLH2ZxzI+Yh4vS5wT08deAtAi3/XST6gH3VhEu4shpvQAcd4ok74e4fbe5CFhWdmr+ s4+rHI9vLh4AVTEXFKA6QHsaAHN0+w== X-Google-Smtp-Source: AGHT+IF97ZP4nL6Caxhy2PrICmPoNEio8MDbDpQr48YBwj0h6+Tmb9xVPRXPbfzgKVgW2Kg/0c4fyg== X-Received: by 2002:a17:907:3f11:b0:aa6:42d8:afac with SMTP id a640c23a62f3a-aa6a01bea0bmr85134066b.15.1733776621756; Mon, 09 Dec 2024 12:37:01 -0800 (PST) Received: from localhost.localdomain (h082218084190.host.wavenet.at. [82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:01 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 04/11] i386/hvf: Pre-fetch emulated instructions Date: Mon, 9 Dec 2024 21:36:22 +0100 Message-Id: <20241209203629.74436-5-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::634; envelope-from=phil@philjordan.eu; helo=mail-ej1-x634.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan The HVF x86 instruction decoder has previously read each instruction component a few bytes at a time. The HVF vCPU VM exit reports the length of the faulted instruction, so we can just pre-fetch the memory for the whole thing in one go, saving extra round-trips for most instructions. The old code path is retained in case there is a race between VM exit and another thread overwriting the faulted instruction. In this case, the instruction length could be wrong, so we allow fetching additional instruction bytes the traditional way if the prefetched bytes are overrun. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/hvf.c | 6 +++--- target/i386/hvf/x86_decode.c | 18 +++++++++++++++--- target/i386/hvf/x86_decode.h | 5 ++++- 3 files changed, 22 insertions(+), 7 deletions(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 936c31dbdd..095f934923 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -522,7 +522,7 @@ int hvf_vcpu_exec(CPUState *cpu) struct x86_decode decode; load_regs(cpu); - decode_instruction(env, &decode); + decode_instruction(env, &decode, ins_len); exec_instruction(env, &decode); store_regs(cpu); break; @@ -562,7 +562,7 @@ int hvf_vcpu_exec(CPUState *cpu) struct x86_decode decode; load_regs(cpu); - decode_instruction(env, &decode); + decode_instruction(env, &decode, ins_len); assert(ins_len == decode.len); exec_instruction(env, &decode); store_regs(cpu); @@ -667,7 +667,7 @@ int hvf_vcpu_exec(CPUState *cpu) struct x86_decode decode; load_regs(cpu); - decode_instruction(env, &decode); + decode_instruction(env, &decode, ins_len); exec_instruction(env, &decode); store_regs(cpu); break; diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index a4a28f113f..79dfc30408 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -73,8 +73,13 @@ static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode, VM_PANIC_EX("%s invalid size %d\n", __func__, size); break; } - target_ulong va = linear_rip(env_cpu(env), env->eip) + decode->len; - vmx_read_mem(env_cpu(env), &val, va, size); + + if (decode->len + size < decode->prefetch_len) { + memcpy(&val, decode->prefetch_buf + decode->len, size); + } else { + target_ulong va = linear_rip(env_cpu(env), env->eip) + decode->len; + vmx_read_mem(env_cpu(env), &val, va, size); + } decode->len += size; return val; @@ -2099,9 +2104,16 @@ static void decode_opcodes(CPUX86State *env, struct x86_decode *decode) } } -uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode) +uint32_t decode_instruction(CPUX86State *env, x86_decode *decode, + uint32_t ins_len) { memset(decode, 0, sizeof(*decode)); + + target_ulong va = linear_rip(env_cpu(env), env->eip); + uint32_t prefetch_len = MIN(ins_len, sizeof(sizeof(decode->prefetch_buf))); + vmx_read_mem(env_cpu(env), decode->prefetch_buf, va, prefetch_len); + decode->prefetch_len = prefetch_len; + decode_prefix(env, decode); set_addressing_size(env, decode); set_operand_size(env, decode); diff --git a/target/i386/hvf/x86_decode.h b/target/i386/hvf/x86_decode.h index a2d7a2a27b..0ff368210b 100644 --- a/target/i386/hvf/x86_decode.h +++ b/target/i386/hvf/x86_decode.h @@ -297,11 +297,14 @@ typedef struct x86_decode { bool is_fpu; uint32_t flags_mask; + uint8_t prefetch_buf[16]; + uint16_t prefetch_len; } x86_decode; uint64_t sign(uint64_t val, int size); -uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode); +uint32_t decode_instruction(CPUX86State *env, x86_decode *decode, + uint32_t ins_len); target_ulong get_reg_ref(CPUX86State *env, int reg, int rex_present, int is_extended, int size); From patchwork Mon Dec 9 20:36:23 2024 Content-Type: text/plain; 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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:02 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 05/11] i386/hvf: Decode APIC access x86 instruction outside BQL Date: Mon, 9 Dec 2024 21:36:23 +0100 Message-Id: <20241209203629.74436-6-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::631; envelope-from=phil@philjordan.eu; helo=mail-ej1-x631.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan The HVF accelerator suffers from severe BQL contention under common practical workloads. x86 instruction decoding for software-emulating faulted instructions is a somewhat expensive operation, and there is no need to hold the BQL while performing it. Except in very unusual edge cases, only an RCU read lock is acquired during the instruction fetch from memory. This change therefore moves instruction decoding for APIC access VM exits to before the BQL is acquired. This improves performance on APIC-heavy workloads. It would be nice to eventually move instruction decoding outside the BQL for MMIO EPT faults as well, but that case is more complicated as not every EPT fault exit needs decoding/executing. Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/hvf.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 095f934923..3f1ff0f013 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -444,6 +444,7 @@ int hvf_vcpu_exec(CPUState *cpu) CPUX86State *env = &x86_cpu->env; int ret = 0; uint64_t rip = 0; + struct x86_decode decode; if (hvf_process_events(cpu)) { return EXCP_HLT; @@ -481,6 +482,11 @@ int hvf_vcpu_exec(CPUState *cpu) rip = rreg(cpu->accel->fd, HV_X86_RIP); env->eflags = rreg(cpu->accel->fd, HV_X86_RFLAGS); + if (exit_reason == EXIT_REASON_APIC_ACCESS) { + load_regs(cpu); + decode_instruction(env, &decode, ins_len); + } + bql_lock(); update_apic_tpr(cpu); @@ -519,8 +525,6 @@ int hvf_vcpu_exec(CPUState *cpu) slot = hvf_find_overlap_slot(gpa, 1); /* mmio */ if (ept_emulation_fault(slot, gpa, exit_qual)) { - struct x86_decode decode; - load_regs(cpu); decode_instruction(env, &decode, ins_len); exec_instruction(env, &decode); @@ -559,7 +563,6 @@ int hvf_vcpu_exec(CPUState *cpu) macvm_set_rip(cpu, rip + ins_len); break; } - struct x86_decode decode; load_regs(cpu); decode_instruction(env, &decode, ins_len); @@ -664,10 +667,6 @@ int hvf_vcpu_exec(CPUState *cpu) break; } case EXIT_REASON_APIC_ACCESS: { /* TODO */ - struct x86_decode decode; - - load_regs(cpu); - decode_instruction(env, &decode, ins_len); exec_instruction(env, &decode); store_regs(cpu); break; From patchwork Mon Dec 9 20:36:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 259A9E7717D for ; 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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:03 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 06/11] i386/hvf: APIC access exit with fast-path for common mov cases Date: Mon, 9 Dec 2024 21:36:24 +0100 Message-Id: <20241209203629.74436-7-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::62e; envelope-from=phil@philjordan.eu; helo=mail-ej1-x62e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan The implementation of the EXIT_REASON_APIC_ACCESS vm exit handler has so far been essentially the same as a regular EPT fault handler, performing a full simulation of the faulted instruction. The code path has also not been used at all because the APIC base address setter in Hypervisor.framework was never called. This change improves the former. In particular, the APIC_ACCESS exit provides us some additional metadata which in many cases allows us to avoid a full instruction emulation. There is no need to walk the memory hierarchy, because exit_qual contains the APIC MMIO offset. It also tells us whether it's an MMIO read or write. So we can detect common mov instructions and directly call the relevant APIC accessor functions. For more complex instructions, we can fall back to the usual instruction emulation. Signed-off-by: Phil Dennis-Jordan --- hw/intc/apic.c | 4 +- include/hw/i386/apic.h | 2 + meson.build | 1 + target/i386/hvf/hvf.c | 18 +++++++- target/i386/hvf/trace-events | 9 ++++ target/i386/hvf/trace.h | 1 + target/i386/hvf/x86_emu.c | 84 ++++++++++++++++++++++++++++++++++++ target/i386/hvf/x86_emu.h | 2 + 8 files changed, 117 insertions(+), 4 deletions(-) create mode 100644 target/i386/hvf/trace-events create mode 100644 target/i386/hvf/trace.h diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 4186c57b34..add99f01e5 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -788,7 +788,7 @@ static void apic_timer(void *opaque) apic_timer_update(s, s->next_time); } -static int apic_register_read(int index, uint64_t *value) +int apic_register_read(int index, uint64_t *value) { DeviceState *dev; APICCommonState *s; @@ -936,7 +936,7 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } -static int apic_register_write(int index, uint64_t val) +int apic_register_write(int index, uint64_t val) { DeviceState *dev; APICCommonState *s; diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h index eb606d6076..47946e5581 100644 --- a/include/hw/i386/apic.h +++ b/include/hw/i386/apic.h @@ -20,6 +20,8 @@ void apic_designate_bsp(DeviceState *d, bool bsp); int apic_get_highest_priority_irr(DeviceState *dev); int apic_msr_read(int index, uint64_t *val); int apic_msr_write(int index, uint64_t val); +int apic_register_read(int index, uint64_t *value); +int apic_register_write(int index, uint64_t val); bool is_x2apic_mode(DeviceState *d); /* pc.c */ diff --git a/meson.build b/meson.build index 147097c652..0846c09bdb 100644 --- a/meson.build +++ b/meson.build @@ -3606,6 +3606,7 @@ if have_system or have_user 'target/arm/hvf', 'target/hppa', 'target/i386', + 'target/i386/hvf', 'target/i386/kvm', 'target/loongarch', 'target/mips/tcg', diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 3f1ff0f013..2a13a9e49b 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -75,6 +75,7 @@ #include "qemu/main-loop.h" #include "qemu/accel.h" #include "target/i386/cpu.h" +#include "trace.h" static Error *invtsc_mig_blocker; @@ -666,8 +667,21 @@ int hvf_vcpu_exec(CPUState *cpu) store_regs(cpu); break; } - case EXIT_REASON_APIC_ACCESS: { /* TODO */ - exec_instruction(env, &decode); + case EXIT_REASON_APIC_ACCESS: { + bool is_load = (exit_qual & 0x1000) == 0; + uint32_t apic_register_idx = (exit_qual & 0xff0) >> 4; + + if (simulate_fast_path_apic_mmio(is_load, apic_register_idx, + env, &decode)) { + env->eip += ins_len; + } else { + trace_hvf_x86_vcpu_exec_apic_access_slowpath( + is_load ? "load from" : "store to", apic_register_idx, + ins_len, decode.prefetch_buf[0], decode.prefetch_buf[1], + decode.prefetch_buf[2], decode.prefetch_buf[3], + decode.prefetch_buf[4], decode.prefetch_buf[5]); + exec_instruction(env, &decode); + } store_regs(cpu); break; } diff --git a/target/i386/hvf/trace-events b/target/i386/hvf/trace-events new file mode 100644 index 0000000000..7d0230fb37 --- /dev/null +++ b/target/i386/hvf/trace-events @@ -0,0 +1,9 @@ +# See docs/devel/tracing.rst for syntax documentation. + +# hvf.c +hvf_x86_vcpu_exec_apic_access_slowpath(const char *access_type, uint32_t apic_register_idx, uint32_t ins_len, uint8_t ins_byte_0, uint8_t ins_byte_1, uint8_t ins_byte_2, uint8_t ins_byte_3, uint8_t ins_byte_4, uint8_t ins_byte_5) "xAPIC %s register 0x%" PRIx32" taking slow path; instruction length: %" PRIu32 ", bytes: %02x %02x %02x %02x %02x %02x ..." + +# x86_emu.c +hvf_x86_emu_mmio_load_instruction_fastpath(int cmd, int operand_size, int opcode_len, uint8_t opcode_byte_0, uint8_t opcode_byte_1, uint8_t opcode_byte_2) "slow path apic load: cmd = %d, operand_size = %u, opcode_len = %u, opcode = [ %02x %02x %02x ... ]" +hvf_x86_emu_mmio_store_instruction_fastpath(int cmd, int operand_size, int opcode_len, uint8_t opcode_byte_0, uint8_t opcode_byte_1, uint8_t opcode_byte_2) "slow path apic store: cmd = %d, operand_size = %u, opcode_len = %u, opcode = [ %02x %02x %02x ... ]" +hvf_x86_fast_path_apic_mmio_failed(const char *access_type, uint32_t apic_register_idx, uint64_t value, int result) "xAPIC %s register 0x%"PRIx32", value 0x%"PRIx64" returned error %d from APIC" diff --git a/target/i386/hvf/trace.h b/target/i386/hvf/trace.h new file mode 100644 index 0000000000..14f15a752a --- /dev/null +++ b/target/i386/hvf/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386_hvf.h" diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 015f760acb..197fa155a0 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -44,6 +44,7 @@ #include "x86_flags.h" #include "vmcs.h" #include "vmx.h" +#include "trace.h" void hvf_handle_io(CPUState *cs, uint16_t port, void *data, int direction, int size, uint32_t count); @@ -897,6 +898,89 @@ static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) env->eip += decode->len; } +static bool mmio_load_instruction_fastpath(x86_decode *decode, CPUX86State *env, + int *load_dest_reg) +{ + if (decode->cmd == X86_DECODE_CMD_MOV && decode->operand_size == 4 + && decode->opcode_len == 1) { + if (decode->opcode[0] == 0x8b) { + g_assert(decode->op[0].type == X86_VAR_REG); + g_assert(decode->op[1].type == X86_VAR_RM); + + *load_dest_reg = decode->op[0].reg | (decode->rex.r ? R_R8 : 0); + return true; + } else if (decode->opcode[0] == 0xa1) { + *load_dest_reg = R_EAX; + return true; + } + } + + trace_hvf_x86_emu_mmio_load_instruction_fastpath( + decode->cmd, decode->operand_size, decode->opcode_len, + decode->opcode[0], decode->opcode[1], decode->opcode[2]); + + return false; +} + +static bool mmio_store_instruction_fastpath(x86_decode *decode, CPUX86State *env, + uint64_t *store_val) +{ + if (decode->cmd == X86_DECODE_CMD_MOV && decode->operand_size == 4 && + decode->opcode_len == 1) { + if (decode->opcode[0] == 0x89) { /* mov DWORD PTR [reg0+off],reg1 */ + g_assert(decode->op[1].type == X86_VAR_REG); + g_assert(decode->op[0].type == X86_VAR_RM); + + *store_val = RRX(env, decode->op[1].reg | (decode->rex.r ? R_R8 : 0)); + return true; + } else if (decode->opcode[0] == 0xc7) { /* mov DWORD PTR [reg0+off],imm*/ + g_assert(decode->op[0].type == X86_VAR_RM); + g_assert(decode->op[1].type == X86_VAR_IMMEDIATE); + *store_val = decode->op[1].val; + return true; + } else if (decode->opcode[0] == 0xa3) { /* movabs ds:immaddr,eax */ + *store_val = RRX(env, R_EAX); + return true; + } + } + + trace_hvf_x86_emu_mmio_store_instruction_fastpath( + decode->cmd, decode->operand_size, decode->opcode_len, + decode->opcode[0], decode->opcode[1], decode->opcode[2]); + return false; +} + + +bool simulate_fast_path_apic_mmio(bool is_load, uint32_t apic_register_idx, + CPUX86State *env, x86_decode* decode) +{ + uint64_t value; + int load_dest_reg; + int res; + + if (is_load) { + if (!mmio_load_instruction_fastpath(decode, env, &load_dest_reg)) { + return false; + } + res = apic_register_read(apic_register_idx, &value); + if (res == 0) { + RRX(env, load_dest_reg) = value; + } + } else { + if (!mmio_store_instruction_fastpath(decode, env, &value)) { + return false; + } + res = apic_register_write(apic_register_idx, value); + } + + if (res != 0) { + trace_hvf_x86_fast_path_apic_mmio_failed( + is_load ? "load from" : "store to", apic_register_idx, value, res); + raise_exception(env, EXCP0D_GPF, 0); + } + return true; +} + /* * flag: * 0 - bt, 1 - btc, 2 - bts, 3 - btr diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 8bd97608c4..6726ca2240 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -31,6 +31,8 @@ void store_regs(CPUState *cpu); void simulate_rdmsr(CPUX86State *env); void simulate_wrmsr(CPUX86State *env); +bool simulate_fast_path_apic_mmio(bool is_load, uint32_t apic_register_idx, + CPUX86State *env, x86_decode* decode); target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); From patchwork Mon Dec 9 20:36:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6824FE7717D for ; Mon, 9 Dec 2024 20:39:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tKkVE-0006J8-NA; Mon, 09 Dec 2024 15:37:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tKkVA-0006FH-9U for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:08 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tKkV8-0003ES-Ks for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:08 -0500 Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-a9f1c590ecdso885673266b.1 for ; Mon, 09 Dec 2024 12:37:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1733776625; x=1734381425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xw6Nq/8rslxJnUqkSeXiT5oto8WsRm37mAQv6Zrh7Zo=; b=10BtnBuKV4kcVgE0DHwEefoen9gFWctr/d3uBG9O7EByyHzpVxQzesF7Pg5mFXMOPf FEhsP8kG99qJNyTx0aPJpsFSLSKFEcPwkKfOFE2s5nxFcux16gmU0xV3UMjP/Ki8Tca5 Zu5I/VNbG5F14JZCPGujjnXW3aMSYIG4XVXob9rycbkG9Ec2ivok9bhQLRb/fECDEqxy lSXhT8k/uzJzDBzx6euLGnWV92XpdT/40REo/zpwQcgXKvfO3GMl1XvMqC5nA0TVSJQy J+Z2+XnGt0iLYiNeemp/qIluX4ArIh1cSqjk4Ia6AbYFyK2Nj62PRG60eeUvYYnHXKoL xjdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733776625; x=1734381425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xw6Nq/8rslxJnUqkSeXiT5oto8WsRm37mAQv6Zrh7Zo=; b=kIJl6RbyJ76mA2elpCECbGMWn1I7fUMQJ4RYlllYEyWpWLWIJE1MdRp6PvtNbyUr6W /wiDr5H951vJEkLtXoMETa5kizu9qyoiS8JM4QZ0zcNWH9/KQjV9XmBEerQWN3oDowBJ JBBfBrzP17TcSBIlf9aJ6cpPVtSJWMV4EvfFo5mtExb+VrMNlWkj4AOZssDnBNMbyNYV 1iUkF/vfId/8QtyxJVdlZgkdnfwK3y2Xi8mwbgNNpY9Jn8GygPS/i6YLRV7l23LAy+Sl EhkVkeo/PsJVBjr66cr5ArWwcguwcJ6H8mDVd0EmmVh93YWYi4jEsWoZz1PO5rsTy+fL V/+Q== X-Gm-Message-State: AOJu0YwI74v73fzWDoZaQZGy/GtqwZWiP25iwFX8BU/wftZ4VocyZLUm 3M5RKnn+xwr6UngY+3sPRLkTxxxSX+aXRbUlhvx9PNTq5WC3al+ljppPvu/9L77mk/Rj+t3T8HM e1g== X-Gm-Gg: ASbGncsaDy1vs5DUi4qyncum+fPxrGCVYoM/CcUZ0+Bn6vnHPM6lKokF46mrhEPOYSP r1P2R4G0Sz1Ic0iK8igpUsa8pDAjfjMtLKeyEXsDXAY+GorPVdmmTJRA7o3KcFrdZc+f9QvAhbV 9S4oEjkEBEXW7p+dNwifX5y45gAo6ktLDhwUXJ4iiCgAyjaTxLzIbOxNW29sf6+jIbxWOL7Zvzh VgeTmh1D0K4j5OFDFz7yNgXMtBLeJeA26fNadrMO9wjJVOTfwa2NeGWjrq4OlQLu/b0gCYjQQ/i e1z74pn1dRlms7CfhYz1PP6aT4WdLQ== X-Google-Smtp-Source: AGHT+IHMg8u6xatM3JB2nocPT1UsXkGcZR+sI4zYs81yAcFM4A0d7QHtdMwFv1r1VAuu+oR+0IFR5A== X-Received: by 2002:a17:907:1dc4:b0:aa6:6c08:dc71 with SMTP id a640c23a62f3a-aa69cd8131emr196188866b.23.1733776624887; Mon, 09 Dec 2024 12:37:04 -0800 (PST) Received: from localhost.localdomain (h082218084190.host.wavenet.at. [82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:04 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 07/11] i386/hvf: Enables APIC_ACCESS VM exits by setting APICBASE Date: Mon, 9 Dec 2024 21:36:25 +0100 Message-Id: <20241209203629.74436-8-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::62f; envelope-from=phil@philjordan.eu; helo=mail-ej1-x62f.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan This change activates virtualised APIC access VM exits so the new fast-pathed implementation will be taken. Two parts are required for enabling APIC_ACCESS exits rather than falling back to "regular" MMIO EPT faults: Hypervisor.framework needs to know the current APIC base address, and the APIC access virtualisation ctl, VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES, must be set in the VMCS. The latter has already been set in QEMU's HVF accel, but setting the APIC base address has been missing. This change calls hv_vmx_vcpu_set_apic_address() before a vCPU runs for the first time, and whenever the APICBASE MSR is modified and the xAPIC is enabled. Additionally, the APIC access ctl is toggled when the APIC is enabled or disabled, or changes mode. In addition to making APIC access VM exits occur at all, it also makes APIC relocation work, at least on the fast path. (QEMU does not currently support different address spaces per vCPU, which is why the purely EPT fault based software APIC - and thus the slow path - does not properly support relocation.) Signed-off-by: Phil Dennis-Jordan --- target/i386/hvf/hvf.c | 11 +++++++++++ target/i386/hvf/x86_emu.c | 18 ++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 2a13a9e49b..a7b8d124bb 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -341,6 +341,17 @@ int hvf_arch_init_vcpu(CPUState *cpu) void hvf_vcpu_before_first_run(CPUState *cpu) { + X86CPU *x86_cpu = X86_CPU(cpu); + hv_vcpuid_t vcpu = cpu->accel->fd; + uint64_t apic_base; + hv_return_t apicbase_result; + + if (cpu_is_apic_enabled(x86_cpu->apic_state) + && !is_x2apic_mode(x86_cpu->apic_state)) { + apic_base = MSR_IA32_APICBASE_BASE & cpu_get_apic_base(x86_cpu->apic_state); + apicbase_result = hv_vmx_vcpu_set_apic_address(vcpu, apic_base); + assert_hvf_ok(apicbase_result); + } } static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 197fa155a0..88a946cb0f 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -797,10 +797,28 @@ void simulate_wrmsr(CPUX86State *env) break; case MSR_IA32_APICBASE: { int r; + hv_return_t res; r = cpu_set_apic_base(cpu->apic_state, data); if (r < 0) { raise_exception(env, EXCP0D_GPF, 0); + } else { + uint64_t pbc = rvmcs(cs->accel->fd, VMCS_SEC_PROC_BASED_CTLS); + uint64_t new_pbc; + if (cpu_is_apic_enabled(cpu->apic_state) + && !is_x2apic_mode(cpu->apic_state)) { + res = hv_vmx_vcpu_set_apic_address(cs->accel->fd, + data & MSR_IA32_APICBASE_BASE); + assert_hvf_ok(res); + + new_pbc = pbc | VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES; + } else { + new_pbc = pbc & ~VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES; + } + if (new_pbc != pbc) { + wvmcs(cs->accel->fd, VMCS_SEC_PROC_BASED_CTLS, + cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2, new_pbc)); + } } break; From patchwork Mon Dec 9 20:36:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900372 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0BD3EE77182 for ; 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[82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:05 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 08/11] i386/hvf: Variable type fixup in decoder Date: Mon, 9 Dec 2024 21:36:26 +0100 Message-Id: <20241209203629.74436-9-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::636; envelope-from=phil@philjordan.eu; helo=mail-ej1-x636.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan decode_bytes reads 1, 2, 4, or 8 bytes at a time. The destination variable should therefore be a uint64_t, not a target_ulong. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Philippe Mathieu-Daudé --- target/i386/hvf/x86_decode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 79dfc30408..6c7cfc820f 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -61,8 +61,8 @@ uint64_t sign(uint64_t val, int size) static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode, int size) { - target_ulong val = 0; - + uint64_t val = 0; + switch (size) { case 1: case 2: From patchwork Mon Dec 9 20:36:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7BC4AE77181 for ; Mon, 9 Dec 2024 20:39:11 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tKkVT-0006QJ-Lk; Mon, 09 Dec 2024 15:37:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tKkVC-0006Hw-J9 for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:10 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tKkVB-0003FT-8E for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:10 -0500 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-5d3e829ff44so3836739a12.0 for ; Mon, 09 Dec 2024 12:37:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1733776628; x=1734381428; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NYJPKkgcbTXxdsXMNMCRcjhKt+ms1PoytQbmmSrV3F4=; b=MSSrHX2CDFbQUas3w06xQuH9T1mlo9XqCRYGf4YhlI1fXwwiv9acm1GZ4Wr+Ps/Ts/ 7UwT4PvtlGC8H08sFOdXDPJ7jO9kiFHh9i8ahFNbfE8kMqaCBMMj1PjWAGm0aY27AKug C0+0ez6sNused4lLL0uAsW5i29pKMRky9Tpzd6Eec6QuesCtNKFXSTYXuDBdmirtUUIl eXeIcDcfkkz4U1yhOOMphXtAu3B9c5i06/s5rKi8q8rFFcZe6UwRwSD6F/qJTVWyexFf kmrsTW/RWyLd+teiK2Cpq638Eiulztr7anmi4+fuKjAMnpvlKbh+lnxiV8d/l5banm/9 vcNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733776628; x=1734381428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NYJPKkgcbTXxdsXMNMCRcjhKt+ms1PoytQbmmSrV3F4=; b=TVWPp6D3aSnBmLL7pv8NMylfTqipg6jZo70dQOtTgwUQ/h7AqfeHthQqRFWVMSBNU4 9LFPakorZDZrHAdJudD0nz1yjBvOxJ+i8lW5TrwkYDAfiVCZjjMTWExThxtk+t0XNSip tjRrM48eQOm6RFp5+vVNlOOLLfoHpkKyiIo0ty1UKWkPJNvngBED/YrGfzHlMcRs548Y 6QQ004jqzGkAf9g1M/0xEuPh+jCFTOE8usIwZXxeSH9/vke/PY9z9nWr3pjMqiPRCbnL 6aKrmjEQ/6n6UKlM6rj259fuC4qlWjYEwxKhU4yzPy5U6R13HTSvv6etV6xPnlQS4kSx VcSA== X-Gm-Message-State: AOJu0YyDmHRfLhNcOPabkQU/PLtxmXHb6u41UmrkElaza1ov4v6KKC7S 8ZAZ3WTrKMMh1cZwhuTaOLSzFSWuxpDftfwSPxGMdqJXKJpC08yEgLqSFvje3AowDeGu6HmHJRA TYA== X-Gm-Gg: ASbGncvJUeEGK6Qsds5A9JEtXSGadfLX+eE2+3S2jR/N0ajxep/VMgc45+w+WScN1bd WbhkFNS/nh9cizaWE6cK39auWcF8M73iRiMWAm8Qro2tfY+nUKEVSToQCvUHiOkHcJ/vft0UPhI MAcmieZABf7CbPVYvV8R/cYO0Zn9v7xk01lxad3RDczIINmkojXjmRYFp1RLmilRpoJeOLmQohb XJjQiTFjuUMOPKsIrLMJ6odRhxYn9cZlnC0xXihCClfzEHrAmBBRvIiyCntg7KoNDFNAiyQ6OtV oXtKVITUP2q9qaCrD0vHQE3m8B/EAg== X-Google-Smtp-Source: AGHT+IHB8k/H2RYEWOrL0OQQ9Gp9k12FNItyZBOVZ8YhOP0e7vqWuWpx893ffQORrlO+5JsHVKcYdA== X-Received: by 2002:a17:907:1c85:b0:aa6:7ff9:d248 with SMTP id a640c23a62f3a-aa6a006e645mr65933966b.8.1733776627709; Mon, 09 Dec 2024 12:37:07 -0800 (PST) Received: from localhost.localdomain (h082218084190.host.wavenet.at. [82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:07 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 09/11] i386/hvf: Print hex pairs for each opcode byte in decode error Date: Mon, 9 Dec 2024 21:36:27 +0100 Message-Id: <20241209203629.74436-10-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::52d; envelope-from=phil@philjordan.eu; helo=mail-ed1-x52d.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan Printing a sequence of bytes as hex with leading zeroes omitted just looks odd. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Philippe Mathieu-Daudé --- target/i386/hvf/x86_decode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/hvf/x86_decode.c b/target/i386/hvf/x86_decode.c index 6c7cfc820f..f8d37f2d53 100644 --- a/target/i386/hvf/x86_decode.c +++ b/target/i386/hvf/x86_decode.c @@ -30,7 +30,7 @@ static void decode_invalid(CPUX86State *env, struct x86_decode *decode) { printf("%llx: failed to decode instruction ", env->eip); for (int i = 0; i < decode->opcode_len; i++) { - printf("%x ", decode->opcode[i]); + printf("%02x ", decode->opcode[i]); } printf("\n"); VM_PANIC("decoder failed\n"); From patchwork Mon Dec 9 20:36:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03EB5E7717D for ; Mon, 9 Dec 2024 20:38:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tKkVe-0006Vi-9R; Mon, 09 Dec 2024 15:37:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tKkVE-0006Iu-DS for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:12 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tKkVC-0003G3-V0 for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:12 -0500 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-5d3f28881d6so2271940a12.1 for ; Mon, 09 Dec 2024 12:37:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1733776629; x=1734381429; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IDfEUP5t3qEfB5+/2Qs/ja/PBzmRbPZf8EVWTjWrIGc=; b=J+4JuwqyJBLIFpUlJf+k1RJFDlmTO2jp2tnxbO6P2rE4Cumv1nMMq/EaF0jzwJP1Fh Bw57UNf/M8cOishB4aSvIgRoAK7FGI5SOyCObsaSCXolqOTxWC2HRHxF0j61ADmyySCB bI9EKk/Weqlr4PNiVcDO2TyTmJuwTdzb9SVe9Stgfz9T8fw9Qu2D7JYM2c439nOO0bCL thsaxMtPNkvILwY5z11cG4PzcQw3PYjEfWpQvlpWegq2tR/G5a8XXvFSWLRXgWNzsdJr Zmdn+vK6gGHG4pm1NYdOrQq1R0STw+OBPDZyaDhfbLyimVDwrLarGPqlCqPV9LDzI7EX xTTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733776629; x=1734381429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IDfEUP5t3qEfB5+/2Qs/ja/PBzmRbPZf8EVWTjWrIGc=; b=IF651jSxuXVTa6PIH0JxpVVPf5AIUapt5vVrX5p/nxIF8uWC7rTfVr4eADp/HC5Jjh e/eDoaywfF6tUbcnsv5FJ2oydykJnIjmTSyv9ehgebjR0GWDvw/s/FXUfBgXWakQfs7F 1BLkdx2YyVQjvUYIlxXL8Q7u4PAMS7Qp3pUcTKJnMm9CzMuL9SCoAV6SvTWqM/BOa6XC DxRxd9mWXaW+X1C1xlh6+yiOozWap/TdnO7eGvRcRAADLf/WIjz9090m72mO/BJfuxbd kUxGTzgMRJPFXK10Eq8bZ5pXMxYj5J2ZVrBKs9YbtoVE6t99BA/m7vIiBP353SAs7bII U5Zg== X-Gm-Message-State: AOJu0YwaRfYB5xLY64JtBSl9fGnz9VwUeKYqPjLC4CWDa0AlcYzJj2xF NfDIGoMGueIJM3AiawlfDj3jcjHk8kK8IxQb0NfE1C4PytREkNtNvEGzYLW1Yl6G7FvLJMvBHoW 3Zg== X-Gm-Gg: ASbGncvccQVy1G6aWLzKO3+jBAobqw9JUrfubR6KqXsotNxyvo132KBWR43EyfORSPn lCVJNHR790jr2wpL68hd4burJJc5m4g0tu4Ae6R+Lfd8czub3dRpjs+oJg/1+Mk0qf9Xyu+FE3y tXsW91qoxjBZEKeHUQ1xVM43HtUyUQAa0YAEZC61eZq7yUcJGDC8f7b7pLkz62cFHOz19jnV9hS RHGV0eEzwBC2d7CmpQyk19sNiY9Yj43dSs3t7sUQpyy5JPiLqU+BfDJK/jUFQyXrS702uUBEv9G HpLRU13Pd2zYHYOabeiqrQcAgYfExQ== X-Google-Smtp-Source: AGHT+IGezn1JeAQQGfTDfs4KzWxtxZbySAwO0G3EdUJAYJ3BKTlm3vY5tOvZ4e3J/Irwk4yXruunsA== X-Received: by 2002:a05:6402:3490:b0:5d0:d2ed:ebb with SMTP id 4fb4d7f45d1cf-5d4184dd0e0mr5226880a12.3.1733776629471; Mon, 09 Dec 2024 12:37:09 -0800 (PST) Received: from localhost.localdomain (h082218084190.host.wavenet.at. [82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:09 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 10/11] hw/intc/apic: Fixes magic number use, removes outdated comment Date: Mon, 9 Dec 2024 21:36:28 +0100 Message-Id: <20241209203629.74436-11-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::532; envelope-from=phil@philjordan.eu; helo=mail-ed1-x532.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan This changes replaces the use of an explicit literal constant for the APIC base address mask with the existing symbolic constant intended for this purpose. Additionally, we remove the comment about not being able to re-enable the APIC after disabling it. This is no longer the case after the APIC implementation's state machine was modified in 9.0. Signed-off-by: Phil Dennis-Jordan Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/apic.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index add99f01e5..d72cbb2a8f 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -350,9 +350,8 @@ static int apic_set_base(APICCommonState *s, uint64_t val) return -1; } - s->apicbase = (val & 0xfffff000) | + s->apicbase = (val & MSR_IA32_APICBASE_BASE) | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); - /* if disabled, cannot be enabled again */ if (!(val & MSR_IA32_APICBASE_ENABLE)) { s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; cpu_clear_apic_feature(&s->cpu->env); From patchwork Mon Dec 9 20:36:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Dennis-Jordan X-Patchwork-Id: 13900371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8FB00E77180 for ; Mon, 9 Dec 2024 20:38:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tKkVg-0006Wx-F2; Mon, 09 Dec 2024 15:37:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tKkVG-0006Jh-W7 for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:24 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tKkVD-0003GQ-R8 for qemu-devel@nongnu.org; Mon, 09 Dec 2024 15:37:13 -0500 Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-aa69077b93fso166530166b.0 for ; Mon, 09 Dec 2024 12:37:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=philjordan-eu.20230601.gappssmtp.com; s=20230601; t=1733776630; x=1734381430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IE9WDOVCTTfWbFzrWk3+NYB4k57W0Vt5GpleV+hnMAc=; b=R0ihLEGWWAL5uHJvgsajQpWguyLaiG7k/vnXDE1D66vUfYtYmX2WhfqEWwBuwtdZN+ zYi1+M34YX6/FFVCLWSmEmLdaNfIHyiwRRjtfXeojFx3PZ3yQX2h5ihvTTUHIpw1Ham9 1bWtivv4fbXOE2lqugSSpOwbzO6ZaTcDZterXSm9RhaqWSPIVNHAqq7FGKJOz85F4GM3 H66ZBf7RLI75jrMOwGHki2oEwRvcS0K+20WQJ4quCxp+qigrAbQ4chQKuLI5cTTFS1+D ZzK4PiuatXqwg0NNOKdj3HZpWn8xi9PL2Kjb2eAxWRq1RodnWrligqJk/thePaYYMLXj YR3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733776630; x=1734381430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IE9WDOVCTTfWbFzrWk3+NYB4k57W0Vt5GpleV+hnMAc=; b=awMVC/lNhELI5yhw0lm8kkTtiiSiV392jis3+wdsRym9Mxa31kruxlYo/qynYAL3yx yXYinOsCkl+5L2T4ffTgewlc5/tmkC3UdJCl4ZCxE6Heqdork/G1VoW8EmTRvkT3JWgf vgtSEdcUNkZw+xestwBd23NdTkPyIZKDp7EGytW8euryjua8+ln2z5nv8FNih1NhbDaE DTrBnCkCbeC0a7MvVjMkSwLe4TtU9NZKw//wyhsnQYv1QlwdtAMQ2cF0XIM6hMsOoIpD CM51FCCtCQo4REXcC5DStNNt5av0wUvWCevs4bAtvFeeM4hm4RTquU1Q63hT0rzKMRz+ qLnA== X-Gm-Message-State: AOJu0YwWMyHHBZexDbmWFT6gNUZXvyxfK8aam2aRs4adXkw8DNnD+d7g gucgUw2fXRZsNsMT3Bst4+/T1U80PoBlw8nKHpOWQC5xK3Bwyq0XS+s/zOGWstqaCBU9bLMj6Wr 4eQ== X-Gm-Gg: ASbGncv5q1dqU4jh3UmlYKDpodIEoZFmV9A+Hc9L6jQAUSEaBNW/yFz6dT2lv+ukY5Z BtsTHYVxjshKQVdRqxwvb5js3qVbWiB0NiTnFihJjaLVRSAKn7Gs7UDOM2XtiBRLGSW1lIjKQXo 0wA+s+EI81KymkXED9P5wpn6SJdifPXdKPirx5h8fEBzjDnGvuJjYLX9HdHVlSuFzL+eDJwOFT6 Wy/5B6H8gnH5JRJ8spo6OLTkRpg7d01oWer/S80WZhORuqvYbIKpE4yrfoa2e1kQn1E+8bYsjs4 gottLzOdf6hlPgrPy6r/r8OnsmveTQ== X-Google-Smtp-Source: AGHT+IGswOYxVOkMA+XvzQnaKOD/7lVr+xcvNSKvz9rdbJJ/otbRBczcyzE8RbzHYCp8ocDjO+jPEg== X-Received: by 2002:a17:906:4ca:b0:aa6:2d86:bd2c with SMTP id a640c23a62f3a-aa63a0ed36cmr1178144466b.21.1733776630516; Mon, 09 Dec 2024 12:37:10 -0800 (PST) Received: from localhost.localdomain (h082218084190.host.wavenet.at. [82.218.84.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa692e4e9d5sm141783566b.129.2024.12.09.12.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Dec 2024 12:37:10 -0800 (PST) From: phil@philjordan.eu To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Roman Bolshakov , "Michael S. Tsirkin" , Paolo Bonzini , Marcel Apfelbaum , Alexander Graf , Peter Maydell , qemu-arm@nongnu.org, Phil Dennis-Jordan Subject: [PATCH 11/11] hw/intc/apic: Raise exception when setting reserved APICBASE bits Date: Mon, 9 Dec 2024 21:36:29 +0100 Message-Id: <20241209203629.74436-12-phil@philjordan.eu> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241209203629.74436-1-phil@philjordan.eu> References: <20241209203629.74436-1-phil@philjordan.eu> MIME-Version: 1.0 Received-SPF: neutral client-ip=2a00:1450:4864:20::629; envelope-from=phil@philjordan.eu; helo=mail-ej1-x629.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Phil Dennis-Jordan Signed-off-by: Phil Dennis-Jordan --- hw/intc/apic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index d72cbb2a8f..83e626a45e 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -309,6 +309,11 @@ bool is_x2apic_mode(DeviceState *dev) static int apic_set_base_check(APICCommonState *s, uint64_t val) { + /* Refuse to set reserved bits */ + if (val & MSR_IA32_APICBASE_RESERVED) { + return -1; + } + /* Enable x2apic when x2apic is not supported by CPU */ if (!cpu_has_x2apic_feature(&s->cpu->env) && val & MSR_IA32_APICBASE_EXTD) {