From patchwork Tue Dec 10 04:08:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Daisuke Kobayashi (Fujitsu)" X-Patchwork-Id: 13900838 X-Patchwork-Delegate: kw@linux.com Received: from esa1.hc1455-7.c3s2.iphmx.com (esa1.hc1455-7.c3s2.iphmx.com [207.54.90.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D5F92248AF for ; Tue, 10 Dec 2024 04:10:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=207.54.90.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733803810; cv=none; b=CnTssDgihoGPBuS/ezbRN+8MgcAl/qRWQUL5G8xEM3P0Iq204kwPi0j9FU0cgMwSHMvWTn/GaUqhkfkZx9s1nO2UqySnuTdoxxBm3hF5bfWZFFjv6GhrTz6snI2yecGOdzl1Gvr95L8knqQlaHzDbwqsk/IFNVvke9YjVVepP/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733803810; c=relaxed/simple; bh=S0MfjnLwqEwNLx8UWprx0QI2LjUg7NHVI991Am1rHrY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o8e3lcffJSAdrMzsdog39WVlkClmlI7EbdN9/vFO475SCWp2RP6QdiB/xNvxhJ5VEdiPBzj0OMgRgwNCK8SQ2jjwbtnWGyiT6Wd9hHtYnqfTo1+eoQhH6Rhfz9vgJdx3ojHb3VBzkjg4wIge+ziLlS7Qj8ZXxyWoWqzN/hrTySs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=fujitsu.com; spf=pass smtp.mailfrom=fujitsu.com; dkim=pass (2048-bit key) header.d=fujitsu.com header.i=@fujitsu.com header.b=LrNwwb0M; arc=none smtp.client-ip=207.54.90.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=fujitsu.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fujitsu.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fujitsu.com header.i=@fujitsu.com header.b="LrNwwb0M" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=fujitsu.com; i=@fujitsu.com; q=dns/txt; s=fj2; t=1733803808; x=1765339808; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S0MfjnLwqEwNLx8UWprx0QI2LjUg7NHVI991Am1rHrY=; b=LrNwwb0MLcxBGf2diCw12dHQ7csrUZv+pHteBN94gPmVpXLt8sPPi7AY wf/6Sq1K96pV94Z4EM7dVnwQ4tbnM4MxuAZzt63jqFdV5sjD+6JAl7KzK UHCV6/wDfxaWJs95UXSeidt+Y6rpGx5GMACgBH5FYThBw8TICWJ+oIfsU u7XCCvdit0gyYOvgTPI+WRmncxFYpTgeqgF279OF4jzs8O8Uf7KgoVfNq aQKNUt4t1YBDSwYNOjYF9CI/NwQOLd1AG3ieCTEAtEICHHtzNig/woqXA yOW/biRLxnt/7jn+M3K8XXExW9eyrn/6FlNoe5QfQw2L1LK84h1BOyyTA A==; X-CSE-ConnectionGUID: 6w0ZCRIBRNS3aEbpgyN63w== X-CSE-MsgGUID: 3IToyVgJSmyEgTb1Dm43ZQ== X-IronPort-AV: E=McAfee;i="6700,10204,11281"; a="183194435" X-IronPort-AV: E=Sophos;i="6.12,221,1728918000"; d="scan'208";a="183194435" Received: from unknown (HELO oym-r3.gw.nic.fujitsu.com) ([210.162.30.91]) by esa1.hc1455-7.c3s2.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 13:08:47 +0900 Received: from oym-m4.gw.nic.fujitsu.com (oym-nat-oym-m4.gw.nic.fujitsu.com [192.168.87.61]) by oym-r3.gw.nic.fujitsu.com (Postfix) with ESMTP id 1A6E2C2260 for ; Tue, 10 Dec 2024 13:08:45 +0900 (JST) Received: from m3002.s.css.fujitsu.com (msm3.b.css.fujitsu.com [10.128.233.104]) by oym-m4.gw.nic.fujitsu.com (Postfix) with ESMTP id E5498D4C11 for ; Tue, 10 Dec 2024 13:08:44 +0900 (JST) Received: from cxl-test.. (unknown [10.118.236.45]) by m3002.s.css.fujitsu.com (Postfix) with ESMTP id AEFB42020FA6; Tue, 10 Dec 2024 13:08:44 +0900 (JST) From: "Kobayashi,Daisuke" To: kobayashi.da-06@jp.fujitsu.com, kw@linux.com, linux-pci@vger.kernel.org Cc: "Kobayashi,Daisuke" Subject: [PATCH v5 1/2] Add helper functions for Power Budgeting Extended Capability Date: Tue, 10 Dec 2024 13:08:20 +0900 Message-ID: <20241210040826.11402-2-kobayashi.da-06@fujitsu.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241210040826.11402-1-kobayashi.da-06@fujitsu.com> References: <20241210040826.11402-1-kobayashi.da-06@fujitsu.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add functions to return a text description of the supplied power_budget scale/base power/rail. Export these functions so they can be used by modules. Signed-off-by: "Kobayashi,Daisuke" --- drivers/pci/pci.h | 3 ++ drivers/pci/probe.c | 66 +++++++++++++++++++++++++++++++++++ include/uapi/linux/pci_regs.h | 3 +- 3 files changed, 71 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..967b53996694 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -374,6 +374,9 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) } const char *pci_speed_string(enum pci_bus_speed speed); +const char *pci_power_budget_scale_string(u8 num); +const char *pci_power_budget_alt_encode_string(u8 num); +const char *pci_power_budget_rail_string(u8 num); enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev); enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev); void __pcie_print_link_status(struct pci_dev *dev, bool verbose); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index f1615805f5b0..18a920527f69 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -748,6 +748,72 @@ void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) } EXPORT_SYMBOL_GPL(pcie_update_link_speed); +const char *pci_power_budget_rail_string(u8 num) +{ + /* Indexed by the rail number */ + static const char *rail_strings[] = { + "Power(12V)", /* 0x00 */ + "Power(3.3V)", /* 0x01 */ + "Power(1.5Vor1.8V)", /* 0x02 */ + "Power(48V)", /* 0x03 */ + "Power(5V)", /* 0x04 */ + "Thermal", /* 0x05 */ + }; + + if (num < ARRAY_SIZE(rail_strings)) + return rail_strings[num]; + return "Unknown"; +} +EXPORT_SYMBOL_GPL(pci_power_budget_rail_string); + +const char *pci_power_budget_scale_string(u8 num) +{ + /* Indexed by the scale number */ + static const char *scale_strings[] = { + "x1.0", /* 0x00 */ + "x0.1", /* 0x01 */ + "x0.01", /* 0x02 */ + "x0.001", /* 0x03 */ + "x10", /* 0x04 */ + "x100", /* 0x05 */ + }; + + if (num < ARRAY_SIZE(scale_strings)) + return scale_strings[num]; + return "Unknown"; +} +EXPORT_SYMBOL_GPL(pci_power_budget_scale_string); + +const char *pci_power_budget_alt_encode_string(u8 num) +{ + u8 n; + n = num & 0x0f; + /* Indexed by the Base Power number */ + static const char *Power_strings[] = { + "> 239 W and ≤ 250 W Slot Power Limit", /* 0xF0 */ + "> 250 W and ≤ 275 W Slot Power Limit", /* 0xF1 */ + "> 275 W and ≤ 300 W Slot Power Limit", /* 0xF2 */ + "> 300 W and ≤ 325 W Slot Power Limit", /* 0xF3 */ + "> 325 W and ≤ 350 W Slot Power Limit", /* 0xF4 */ + "> 350 W and ≤ 375 W Slot Power Limit", /* 0xF5 */ + "> 375 W and ≤ 400 W Slot Power Limit", /* 0xF6 */ + "> 400 W and ≤ 425 W Slot Power Limit", /* 0xF7 */ + "> 425 W and ≤ 450 W Slot Power Limit", /* 0xF8 */ + "> 450 W and ≤ 475 W Slot Power Limit", /* 0xF9 */ + "> 475 W and ≤ 500 W Slot Power Limit", /* 0xFA */ + "> 500 W and ≤ 525 W Slot Power Limit", /* 0xFB */ + "> 525 W and ≤ 550 W Slot Power Limit", /* 0xFC */ + "> 550 W and ≤ 575 W Slot Power Limit", /* 0xFD */ + "> 575 W and ≤ 600 W Slot Power Limit", /* 0xFE */ + "Greater than 600 W", /* 0xFF */ + }; + + if (n < ARRAY_SIZE(Power_strings)) + return Power_strings[n]; + return "Unknown"; +} +EXPORT_SYMBOL_GPL(pci_power_budget_alt_encode_string); + static unsigned char agp_speeds[] = { AGP_UNKNOWN, AGP_1X, diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 12323b3334a9..3a5e238b98d8 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -842,11 +842,12 @@ #define PCI_PWR_DSR 0x04 /* Data Select Register */ #define PCI_PWR_DATA 0x08 /* Data Register */ #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ -#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ +#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale[1:0] */ #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ +#define PCI_PWR_DATA_SCALE_UP(x) (((x) >> 21) & 1) /* Data Scale[2] */ #define PCI_PWR_CAP 0x0c /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ #define PCI_EXT_CAP_PWR_SIZEOF 0x10 From patchwork Tue Dec 10 04:08:21 2024 Content-Type: text/plain; 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(unknown [10.118.236.45]) by m3002.s.css.fujitsu.com (Postfix) with ESMTP id 810F02020FA6; Tue, 10 Dec 2024 13:08:49 +0900 (JST) From: "Kobayashi,Daisuke" To: kobayashi.da-06@jp.fujitsu.com, kw@linux.com, linux-pci@vger.kernel.org Cc: "Kobayashi,Daisuke" Subject: [PATCH v5 2/2] Export Power Budgeting Extended Capability into pci-bus-sysfs Date: Tue, 10 Dec 2024 13:08:21 +0900 Message-ID: <20241210040826.11402-3-kobayashi.da-06@fujitsu.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241210040826.11402-1-kobayashi.da-06@fujitsu.com> References: <20241210040826.11402-1-kobayashi.da-06@fujitsu.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for PBEC (Power Budgeting Extended Capability) output to the PCIe driver. PBEC is defined in the PCIe specification(PCIe r6.0, sec 7.8.1) and is a standard method for obtaining device power consumption information. Signed-off-by: "Kobayashi,Daisuke" --- Documentation/ABI/testing/sysfs-bus-pci | 62 ++++++++ drivers/pci/pci-sysfs.c | 179 ++++++++++++++++++++++++ 2 files changed, 241 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 7f63c7e97773..ec417ae20bc1 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -572,3 +572,65 @@ Description: enclosure-specific indications "specific0" to "specific7", hence the corresponding led class devices are unavailable if the DSM interface is used. + +What: /sys/bus/pci/devices/.../power_budget +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This file provides information about the PCIe power budget + for the device. It is a read-only file that outputs the values + of the Power Budgeting Data Register for each power state as a + series of 32-bit hexadecimal values. Each line represents a + single Power Budgeting Data register entry, containing the + power budget for a specific power state. + + The specific interpretation of these values depends on the + device and the PCIe specification. Refer to the PCIe + specification for detailed information about the Power + Budgeting Data register, including the encoding of power + states and the interpretation of Base Power and Data Scale. + +What: /sys/bus/pci/devices/.../power_budget/power_budget_data_select +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This is an 8-bit read/write register that selects the DWORD of + power budgeting data that will be displayed in the + Power Budgeting Data. The value starts at zero and incrementing + the index value selects the next DWORD. + +What: /sys/bus/pci/devices/.../power_budget/power_budget_power +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This file provides the power consumption calculated by + multiplying the base power by the data scale. + + +What: /sys/bus/pci/devices/.../power_budget/power_budget_pm_state +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This file specifies the power management state of the operating + condition. + +What: /sys/bus/pci/devices/.../power_budget/power_budget_pm_substate +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This file specifies the power management sub state of the + operating condition. + +What: /sys/bus/pci/devices/.../power_budget/power_budget_type +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This file specifies the type of the operating condition. + + +What: /sys/bus/pci/devices/.../power_budget/power_budget_rail +Date: December 2024 +Contact: Kobayashi Daisuke +Description: + This file Specifies the thermal load or power rail of the + operating condition. diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 5d0f4db1cab7..89909633ad02 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -238,6 +238,155 @@ static ssize_t current_link_width_show(struct device *dev, } static DEVICE_ATTR_RO(current_link_width); +static ssize_t power_budget_data_select_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos; + u8 val; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + if (kstrtou8(buf, 0, &val) < 0) + return -EINVAL; + + pci_write_config_byte(pci_dev, pos + PCI_PWR_DSR, val); + + return count; +} + +static ssize_t power_budget_data_select_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos, err; + u8 data; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + err = pci_read_config_byte(pci_dev, pos + PCI_PWR_DSR, &data); + if (err) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", data); +} + +static DEVICE_ATTR_RW(power_budget_data_select); + +static ssize_t power_budget_power_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos, err; + u32 data; + u8 base, scale_up, scale_low, scale; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + err = pci_read_config_dword(pci_dev, pos + PCI_PWR_DATA, &data); + if (err) + return -EINVAL; + + base = PCI_PWR_DATA_BASE(data); + scale_up = PCI_PWR_DATA_SCALE_UP(data); + scale_low = PCI_PWR_DATA_SCALE(data); + scale = scale_up << 2 | scale_low; + if (scale == 0 && base >= 0xF0) + return sysfs_emit(buf, "%s\n",pci_power_budget_alt_encode_string(data)); + + return sysfs_emit(buf, "%u%s\n", base, pci_power_budget_scale_string(scale)); +} +static DEVICE_ATTR_RO(power_budget_power); + +static ssize_t power_budget_pm_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos, err; + u32 data; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + err = pci_read_config_dword(pci_dev, pos + PCI_PWR_DATA, &data); + if (err) + return -EINVAL; + + return sysfs_emit(buf, "D%u\n", PCI_PWR_DATA_PM_STATE(data)); +} +static DEVICE_ATTR_RO(power_budget_pm_state); + +static ssize_t power_budget_pm_substate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos, err; + u8 substate; + u32 data; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + err = pci_read_config_dword(pci_dev, pos + PCI_PWR_DATA, &data); + if (err) + return -EINVAL; + + substate = PCI_PWR_DATA_PM_SUB(data); + if (substate == 0) + return sysfs_emit(buf, "Default Sub State\n"); + + return sysfs_emit(buf, "Device Specific Sub State\n"); +} +static DEVICE_ATTR_RO(power_budget_pm_substate); + +static ssize_t power_budget_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos, err; + u32 data; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + err = pci_read_config_dword(pci_dev, pos + PCI_PWR_DATA, &data); + if (err) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", PCI_PWR_DATA_TYPE(data)); +} +static DEVICE_ATTR_RO(power_budget_type); + +static ssize_t power_budget_rail_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + int pos, err; + u32 data; + + pos = pci_find_ext_capability(pci_dev, PCI_EXT_CAP_ID_PWR); + if (!pos) + return -EINVAL; + + err = pci_read_config_dword(pci_dev, pos + PCI_PWR_DATA, &data); + if (err) + return -EINVAL; + + return sysfs_emit(buf, "%s\n", + pci_power_budget_rail_string(PCI_PWR_DATA_RAIL(data))); +} +static DEVICE_ATTR_RO(power_budget_rail); + static ssize_t secondary_bus_number_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -636,6 +785,16 @@ static struct attribute *pcie_dev_attrs[] = { NULL, }; +static struct attribute *pcie_pbec_attrs[] = { + &dev_attr_power_budget_data_select.attr, + &dev_attr_power_budget_power.attr, + &dev_attr_power_budget_pm_state.attr, + &dev_attr_power_budget_pm_substate.attr, + &dev_attr_power_budget_rail.attr, + &dev_attr_power_budget_type.attr, + NULL, +}; + static struct attribute *pcibus_attrs[] = { &dev_attr_bus_rescan.attr, &dev_attr_cpuaffinity.attr, @@ -1610,6 +1769,19 @@ static umode_t pcie_dev_attrs_are_visible(struct kobject *kobj, return 0; } +static umode_t pcie_pbec_attrs_are_visible(struct kobject *kobj, + struct attribute *a, int n) +{ + struct device *dev = kobj_to_dev(kobj); + struct pci_dev *pdev = to_pci_dev(dev); + + if (pci_is_pcie(pdev) && + pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PWR)) + return a->mode; + + return 0; +} + static const struct attribute_group pci_dev_group = { .attrs = pci_dev_attrs, }; @@ -1652,6 +1824,12 @@ static const struct attribute_group pcie_dev_attr_group = { .is_visible = pcie_dev_attrs_are_visible, }; +static const struct attribute_group pcie_pbec_attr_group = { + .name = "power_budget", + .attrs = pcie_pbec_attrs, + .is_visible = pcie_pbec_attrs_are_visible, +}; + const struct attribute_group *pci_dev_attr_groups[] = { &pci_dev_attr_group, &pci_dev_hp_attr_group, @@ -1661,6 +1839,7 @@ const struct attribute_group *pci_dev_attr_groups[] = { #endif &pci_bridge_attr_group, &pcie_dev_attr_group, + &pcie_pbec_attr_group, #ifdef CONFIG_PCIEAER &aer_stats_attr_group, #endif