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Mon, 09 Dec 2024 20:48:24 -0800 (PST) Received: from sholland-0826.internal.sifive.com ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3a9c9da809dsm17022405ab.4.2024.12.09.20.48.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Dec 2024 20:48:24 -0800 (PST) From: Samuel Holland To: kvm@vger.kernel.org Cc: Samuel Holland Subject: [kvm-unit-tests PATCH 1/3] riscv: Add Image header to flat binaries Date: Mon, 9 Dec 2024 22:44:40 -0600 Message-Id: <20241210044442.91736-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241210044442.91736-1-samuel.holland@sifive.com> References: <20241210044442.91736-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This allows flat binaries to be understood by U-Boot's booti command and its PXE boot flow. Signed-off-by: Samuel Holland --- riscv/cstart.S | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/riscv/cstart.S b/riscv/cstart.S index b7ee9b9c..106737a1 100644 --- a/riscv/cstart.S +++ b/riscv/cstart.S @@ -39,15 +39,29 @@ * The hartid of the current core is in a0 * The address of the devicetree is in a1 * - * See Linux kernel doc Documentation/riscv/boot.rst + * See Linux kernel doc Documentation/arch/riscv/boot.rst and + * Documentation/arch/riscv/boot-image-header.rst */ .global start start: + j 1f + .balign 8 + .dword 0 // text offset + .dword stacktop - ImageBase // image size + .dword 0 // flags + .word (0 << 16 | 2 << 0) // version + .word 0 // res1 + .dword 0 // res2 + .ascii "RISCV\0\0\0" // magic + .ascii "RSC\x05" // magic2 + .word 0 // res3 + /* * Stash the hartid in scratch and shift the dtb address into a0. * thread_info_init() will later promote scratch to point at thread * local storage. */ +1: csrw CSR_SSCRATCH, a0 mv a0, a1 From patchwork Tue Dec 10 04:44:41 2024 Content-Type: text/plain; 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Mon, 09 Dec 2024 20:48:25 -0800 (PST) Received: from sholland-0826.internal.sifive.com ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3a9c9da809dsm17022405ab.4.2024.12.09.20.48.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Dec 2024 20:48:25 -0800 (PST) From: Samuel Holland To: kvm@vger.kernel.org Cc: Samuel Holland Subject: [kvm-unit-tests PATCH 2/3] riscv: Rate limit UART output to avoid FIFO overflows Date: Mon, 9 Dec 2024 22:44:41 -0600 Message-Id: <20241210044442.91736-3-samuel.holland@sifive.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241210044442.91736-1-samuel.holland@sifive.com> References: <20241210044442.91736-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This is necessary when running tests on bare metal. Signed-off-by: Samuel Holland --- lib/riscv/io.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/riscv/io.c b/lib/riscv/io.c index b3f587bb..8d684ccd 100644 --- a/lib/riscv/io.c +++ b/lib/riscv/io.c @@ -13,6 +13,9 @@ #include #include +#define UART_LSR_OFFSET 5 +#define UART_LSR_THRE 0x20 + /* * Use this guess for the uart base in order to make an attempt at * having earlier printf support. We'll overwrite it with the real @@ -76,8 +79,11 @@ void io_init(void) void puts(const char *s) { spin_lock(&uart_lock); - while (*s) + while (*s) { + while (!(readb(uart0_base + UART_LSR_OFFSET) & UART_LSR_THRE)) + ; writeb(*s++, uart0_base); + } spin_unlock(&uart_lock); } From patchwork Tue Dec 10 04:44:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 13900859 Received: from mail-il1-f182.google.com (mail-il1-f182.google.com [209.85.166.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01BC8226172 for ; Tue, 10 Dec 2024 04:48:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733806110; cv=none; b=MqxozBaGt5zNSedTyL+U74BdGlPmuxBzQw5UjeALlsFdHv/55/GijlTdly9oNZ/yRRxP/ESYb735pJE7wPVzEF/AxQA976f1stelolmOmHJcrvp1ErOl4gSr7EG6dxwsWbSYQhBK04O3glGsUPdJxLOiTedWwIBqWazdtgSLNf4= ARC-Message-Signature: i=1; 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Mon, 09 Dec 2024 20:48:26 -0800 (PST) Received: from sholland-0826.internal.sifive.com ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3a9c9da809dsm17022405ab.4.2024.12.09.20.48.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Dec 2024 20:48:26 -0800 (PST) From: Samuel Holland To: kvm@vger.kernel.org Cc: Samuel Holland Subject: [kvm-unit-tests PATCH 3/3] riscv: Support UARTs with different I/O widths Date: Mon, 9 Dec 2024 22:44:42 -0600 Message-Id: <20241210044442.91736-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20241210044442.91736-1-samuel.holland@sifive.com> References: <20241210044442.91736-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Integration of ns16550-compatible UARTs is often done with 16 or 32-bit wide registers. Add support for these using the standard DT properties. Signed-off-by: Samuel Holland --- lib/riscv/io.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/lib/riscv/io.c b/lib/riscv/io.c index 8d684ccd..011b5b1d 100644 --- a/lib/riscv/io.c +++ b/lib/riscv/io.c @@ -25,8 +25,34 @@ */ #define UART_EARLY_BASE ((u8 *)(unsigned long)CONFIG_UART_EARLY_BASE) static volatile u8 *uart0_base = UART_EARLY_BASE; +static u32 uart0_reg_shift = 1; +static u32 uart0_reg_width = 1; static struct spinlock uart_lock; +static u32 uart0_read(u32 num) +{ + u32 offset = num << uart0_reg_shift; + + if (uart0_reg_width == 1) + return readb(uart0_base + offset); + else if (uart0_reg_width == 2) + return readw(uart0_base + offset); + else + return readl(uart0_base + offset); +} + +static void uart0_write(u32 num, u32 val) +{ + u32 offset = num << uart0_reg_shift; + + if (uart0_reg_width == 1) + writeb(val, uart0_base + offset); + else if (uart0_reg_width == 2) + writew(val, uart0_base + offset); + else + writel(val, uart0_base + offset); +} + static void uart0_init_fdt(void) { const char *compatible[] = {"ns16550a"}; @@ -50,6 +76,17 @@ static void uart0_init_fdt(void) abort(); } } else { + const fdt32_t *val; + int len; + + val = fdt_getprop(dt_fdt(), ret, "reg-shift", &len); + if (len == sizeof(*val)) + uart0_reg_shift = fdt32_to_cpu(*val); + + val = fdt_getprop(dt_fdt(), ret, "reg-io-width", &len); + if (len == sizeof(*val)) + uart0_reg_width = fdt32_to_cpu(*val); + ret = dt_pbus_translate_node(ret, 0, &base); assert(ret == 0); } @@ -80,9 +117,9 @@ void puts(const char *s) { spin_lock(&uart_lock); while (*s) { - while (!(readb(uart0_base + UART_LSR_OFFSET) & UART_LSR_THRE)) + while (!(uart0_read(UART_LSR_OFFSET) & UART_LSR_THRE)) ; - writeb(*s++, uart0_base); + uart0_write(0, *s++); } spin_unlock(&uart_lock); }