From patchwork Wed Dec 11 01:02:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902676 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C0173A8CB; Wed, 11 Dec 2024 01:04:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879069; cv=none; b=Sr/0DsPSXV1jmvgx1tRBhNlK6sWBCUqb6XAOgdMJ7m6YjxJzgwO4Cxf2nMTcnQRjxGNzCDXdc41s8vI0zWjPuZBOZ1fc2oYyLiwzv9A5Ub/CPv9+ZvZB3Jb2BUQI0M4AWoEjdArHExvjUvxCk6VrThbjK1hQIrENL7SEupPO9l0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879069; c=relaxed/simple; bh=JZ5YG/ZPtu0+rE3J++aCFRB1wnbLT9/tbF2mceWYsQI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hAYYMFdRd19sS7SIgKL2zFCyLSotDdEW2ZisAmHfkVZCs7Ag4QvISPi7j1Z62QQ84r5Srpimv/t5/NsQJ+/5erVk+c5OQ/XJvdGcb8go5YMOhI5QzWbR0lWA3pyhv+zspJZVhMQ04SBh9AVp0j4Y1vgBRLmPpi9F5ZzIvcVXGhA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Wh3XVNlK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Wh3XVNlK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8481AC4CEE2; Wed, 11 Dec 2024 01:04:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879068; bh=JZ5YG/ZPtu0+rE3J++aCFRB1wnbLT9/tbF2mceWYsQI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Wh3XVNlKH9j7aWMeMKMS2zglc1MDzb3cNC3P3ZVhKF1a/2Vw0HuF1nvrtu8PcbhdQ vzxGzsKJL8j+3EVbYjpNZUvkbOUslBar8YVfHs61E0BGXh8PQ6EOsJBFy9CyC9kIUY cwSEJ9Vt2TYNUnPYeGiZ5opuHm+Qg9eqiU1bCy+g4eWiEMpUKYNeY1yDwMg02s8GD5 khF0m9ou4Dt9I5W9iDzeBAopue0CfpNT1oSIb2tvVptRFg4RxY55Q2ruXTmCu1DLkG LKB6oO44s3ICHPWJe3SKq8vd6bKtpclik3tEpp4MfgfLOg/4OZZcSPswlX3rcZ8m3L uJG6mu8yV3e2Q== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:46 +0000 Subject: [PATCH v4 1/9] arm64/sysreg: Update ID_AA64PFR2_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-1-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=771; i=broonie@kernel.org; h=from:subject:message-id; bh=JZ5YG/ZPtu0+rE3J++aCFRB1wnbLT9/tbF2mceWYsQI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUPKGYKMBg6LVTy4ZKj00alAeR2T1/6KyqDXfuC v2nAsb2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlDwAKCRAk1otyXVSH0GAcB/ 9A9ZssLa2ITwyImdrKFofGZHRFhONgiad1DSNOH8rRWAAp3W91RDBwqlRz57TxQsbHGRX38JV1qTiD n5KbKtyzjNrEPrz/apU6rQW5r/Jdk6xV53nqDZUmWEsxWdUvv7X8LkU9UK+sBqtMi+afHPXTFdjv/G QWccbqd+SHpQsA0gShWPpVdbeoBY44svHIkOaff5/pDoPn1geub7iah+SFjS0/U+6zSeuasxG224rC pVdfvxaJmLCHCxSEZ6MTEpVc4eG+Cfy782fLZGJH3mK8Pd21Li41PIpifmK76xQyLaeeUcv3hpwtUw 7BtchhuJ3OkZoHPhYBKMYBaRKwVuS+ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 defines a new feature flags in ID_AA64PFR2_EL1 describing support for injecting UNDEF exceptions, update sysreg to include this. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b081b54d6d227ed8300a6f129896647316f0b673..911f16c82ebd3ee98ffed965b02a5c6b153bc50c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1010,7 +1010,12 @@ UnsignedEnum 35:32 FPMR 0b0000 NI 0b0001 IMP EndEnum -Res0 31:12 +Res0 31:20 +UnsignedEnum 19:16 UINJ + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 15:12 UnsignedEnum 11:8 MTEFAR 0b0000 NI 0b0001 IMP From patchwork Wed Dec 11 01:02:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902677 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 820891494CC; Wed, 11 Dec 2024 01:04:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879071; cv=none; b=DGKhxN/oLX1397C3hsLh4jy2XONRxJ1bcfX2MioiAbbCUuLQJLNncowLRMCovfspUasBOzFUkb+H108n901q5zO+gxCQpkjfo0Alv5Tnmz+nAFMvKMJEZSlfcUN32Jo4XtgHvyUa9Shnj4qn8aqF8y83BG84c46IC7nWzD1ZJiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879071; c=relaxed/simple; bh=+YQiNGxuReZbhRyHsK58fKXnEHlrUTfoqeBLUdyrvis=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LjBLTNqG4i+p3oab1J+4LqxxZ9brqhyZ7/vL3unw0sMaA+zfxHohZJyV2L/ESAAE6VrzjSbfD7tj1cT9mNNkTDexI4xe9XOwmg09LIgP5DFJNcecn/EjMmNve2kvI4crByhLi4QtfHoLi46Z8+S1XIGsEZtDcK/tZduARGKqicU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YXs6NC4+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YXs6NC4+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7CC8FC4CEDF; Wed, 11 Dec 2024 01:04:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879071; bh=+YQiNGxuReZbhRyHsK58fKXnEHlrUTfoqeBLUdyrvis=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YXs6NC4+lw95Qtea2tDdeLyYZjrmzDf7dE0QQBYikfky4j9y2GANmtaw8gty4xY6c QtgUSU7EM6rbJWWA3gIGOl+Q9n4yMFa9VZ6HxJ/uxc4uczU3zyLn9DyzyDS0p80dAS R2Xk9/rkpCTNOXVRQwfGr1LbqhJt1kBH9fIl5CQLGLqlhxYJme+Lphlcsv90zBHAek 4hePp9W79W/EeNQbUBRUyhrQT/iAxH2fq2nNvbB3VKwJjXmC5Zgbd3xKjDsAYBjHiW OKkWco9WWQRR8C3480D+D/3FzI7a3szGoGkVxsPDYJ1cGTe/VFy9C0F8tG8czcwLUY YTGeDr7G2WMrA== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:47 +0000 Subject: [PATCH v4 2/9] arm64/sysreg: Update ID_AA64ISAR3_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-2-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=944; i=broonie@kernel.org; h=from:subject:message-id; bh=+YQiNGxuReZbhRyHsK58fKXnEHlrUTfoqeBLUdyrvis=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUQ80C4Zub4NZs2VfYDJhImH82ICyjvpEDJbvB7 SG7v4NSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlEAAKCRAk1otyXVSH0EC6B/ 0RFPGutI+vIH8jF5EGtW53cB1rpdiueDzb2YaCdcmLCEeHrVcXPhy9KfpTuHIs8/8yAdMarcNbH1nJ 33zwvJ/vpMdTP4n8uUAo4U0vnlYBf5QsoVaHrbzwYsG34N6BtnZsQoNG0upCM8xWMzAeClowxv6aWM K7W7JKC7GIj2sZOGIpIYXJdDLIr3eocL//sF1KCGQYqvQHMyi8vc6j4YlEtjr0Ler+zemOhnr98vs/ FV9AFIl8uA8hQfiV4d+sGXE5rb9aKRH6RRxxitYpq1mLAcf1Zlsm1q+Bg6Ia5x6DleEHtoBa46iKd0 pVEadGgrT5qQjFTf9HSWqdyo9MMqB9 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 defines several new feature flags in ID_AA64ISAR3_EL1, update our description in sysreg to reflect these. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 911f16c82ebd3ee98ffed965b02a5c6b153bc50c..6273068fd4fdef145cb7dd49e2d9bee4db467975 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1566,7 +1566,23 @@ EndEnum EndSysreg Sysreg ID_AA64ISAR3_EL1 3 0 0 6 3 -Res0 63:16 +Res0 63:32 +UnsignedEnum 31:28 FPRCVT + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 27:24 LSUI + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 23:20 OCCMO + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 19:16 LSFE + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 15:12 PACM 0b0000 NI 0b0001 TRIVIAL_IMP From patchwork Wed Dec 11 01:02:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902678 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E38D175D4F; Wed, 11 Dec 2024 01:04:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879074; cv=none; b=Nftioe4HDkB5zqdgqfQ21LcoE6O22plxrPomUVT9wuzm7JEmPHuCInoW8jwzmWL+DMy0W605KxTExdvH2o6EcVmzekBv/fS6xgW/PNppk9uWiXPqptaaHktaCRnqBlLdethrA0+xciJyW5D3ad0Rp4TeU6v96AXj6PkuSGld6EY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879074; c=relaxed/simple; bh=tQADLfY41IKkZA7AF+bwW0vqWMNKD/LB1TwUvRuOyFw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kf2RveaokNvvIz/GF4ufvUWSfH+nUlHyBR0MC6IOb1rl+ae7LkPQeESHhCwqRRwqIpEvI1iNt5dy+IBczekq4VUkhKK/TO00FrrkiPG5jEemabwPBU5u5ivPUtz1shlikz4OdL3XzwRg4uH7KAYH2dwjEScsBGIrlFaxbMmgOEg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ekEfOa+D; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ekEfOa+D" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76626C4CEE0; Wed, 11 Dec 2024 01:04:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879074; bh=tQADLfY41IKkZA7AF+bwW0vqWMNKD/LB1TwUvRuOyFw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ekEfOa+D7gTQPfXr5Lye5GpRK+oVf9lwGrZT14PftSwovtc8ztssd4YCoIvMd13oA 26PUmg+8tFb/n6rbePs78HsPAY7101P65l8CWESgaz9uIABnIe/hHNaFkPbMr62aUq 1X2F5RimLEHgXwo7mhNhgNLZvo6ltr3zpyJ0YPaADIsrMKRp0OzeezzaRcg7Z7g6sY eV3qxSf18W4MK6+zMBVQVK9gHt3E8pyz4fdSjBJC+JaC7E+9flV9OXz4k8xb5QivCP btNQsv6xBcdbx+odrTszf3xwUfv0TG4W8WSChv5VYmjIpsnxUmuTBgql5JLEa/l0J/ xWyb0JFbhECmg== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:48 +0000 Subject: [PATCH v4 3/9] arm64/sysreg: Update ID_AA64FPFR0_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-3-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=766; i=broonie@kernel.org; h=from:subject:message-id; bh=tQADLfY41IKkZA7AF+bwW0vqWMNKD/LB1TwUvRuOyFw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUQ9vSB2ZButDKT3O5CIq700NkB8Wdk1iHpnq9v +9T4qgeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlEAAKCRAk1otyXVSH0JlHB/ 4pmcGhkRMFoqxjd8JK/sPpRwDExvNZGBH1O8DfXZMGJxyelW4V0/BcJHCVWTzHwe5XvPatleecP2rt p/mThbtjJKP+gWZBSzqo4smYVgADT5nLO55IYsEsOf2tOaLy4lUrnLsiSm2DMejN089x9gjChr/Ylo 5x7C/yukXmmGyuPP7eGmb20amBiJ2a5+om/3isx6F0r0+6YXyiW0MAV5EDNZHjqNoJX1Hr9kpagq3t 4k/zHG3ZMAxcD5+mi4/6XtcvViQGsTAz1Y4BHstmmc1wZIS4XPCpYC18cyT79OEfQoXBR8oQ8fc9lt xIt/gPh6BQY/NCDv5soD3WUOOSZY+t X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 defines two new feature flags in ID_AA64FPFR0_EL1 describing new FP8 operations, describe them in sysreg. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6273068fd4fdef145cb7dd49e2d9bee4db467975..14284a120a5796bb510a0382984236eba9bf73ab 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1180,7 +1180,15 @@ UnsignedEnum 28 F8DP2 0b0 NI 0b1 IMP EndEnum -Res0 27:2 +UnsignedEnum 27 F8MM8 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 26 F8MM4 + 0b0 NI + 0b1 IMP +EndEnum +Res0 25:2 UnsignedEnum 1 F8E4M3 0b0 NI 0b1 IMP From patchwork Wed Dec 11 01:02:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902679 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66EA4189B8B; Wed, 11 Dec 2024 01:04:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879077; cv=none; b=SO5k7QSmaocUlVZHa+xvu60cJQNJS6VKVp54e2PULK/Z3IyH553/syqXeOVH+05Vayrzq81MRQiZ2v7WaX7riIDJYtGgmhoVDY4wzpRYy45v4GjP6NKclCcI2NoGcC+aLIp0dtoyNunj3DlClIQBm8jSktKEPro9TRGS8rBxT1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879077; c=relaxed/simple; bh=cqa9T0MNY7qNBa8+pChF2cmZR6wFtD7tZyVA8NOA6J4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lHIhNSfp23X2m/dTCFN9uEpmihH3GNz41TyzlKuPoxCbWN1tSCAVhfIjoq+37jMTT06JFX+hHuH4EyqQZ7Vyfk/++lJzqn0bRo8+WKPe7wE+YAtLWqxkopbfdTjGKur19ZciN3iIqxdP/wsgNsrrgJkIWweWQ8nBid1KD1J/tRE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qDiDvLos; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qDiDvLos" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70FBDC4CED6; Wed, 11 Dec 2024 01:04:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879077; bh=cqa9T0MNY7qNBa8+pChF2cmZR6wFtD7tZyVA8NOA6J4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qDiDvLosMAeoUxr9SihZ3ILKudU/BVJh4lLGBAugsc/KHPXGnx+G9DtCAg4R8vHPW j88hA7fFwNEAG300xv32mQWoTRLHXmcfveTF+YIBzPecpdCI9C4WVbNlJ5OQ5VwCKD haS28GDVs/x4GSfJy76lp0R1/w5qTTsbLhA46X1A0B2u2N7sxIJKWW0woWm7jjRWna dxqHYnltFlZXKrHXIMzXF0btDPg8+QB1jFvVPNYosB3A1ZQ+9VGOjVAXLm++qW6O2X uj9p2HxG9Sqy+JdV9SbrxxAGvxCzdHJLwWz86wThB2aqamlj5fsMC9yk9lbyIYOLJ8 Rw6b/DJOxMFRA== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:49 +0000 Subject: [PATCH v4 4/9] arm64/sysreg: Update ID_AA64ZFR0_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-4-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1302; i=broonie@kernel.org; h=from:subject:message-id; bh=cqa9T0MNY7qNBa8+pChF2cmZR6wFtD7tZyVA8NOA6J4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOURA0EIxA9EPjbiIzbTF6VFtD542aCt4lwFY1dz Hjf1NxuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlEQAKCRAk1otyXVSH0OyGB/ 9PoRZOcDRzdK5RkE64k95GMgMXaKq4noetvS+e48Gk5VG/GQ+go7FE4LWN2OwC4d0VckiFO2Ao2dJm uMyo9FPEEf8T1/Da6MrYnX4TeJCbb6h2kGB8sWf2WPY0csMfdlHrK/1ZAL1IWsoVxIADPFmMHpgkIa OGF3HnscxDl6pv7++vOj1cPoMP3ouKipg5YjQsqLdtYaO/F/Ubo1HAiOqtI+/x4PsSd3GNGozaORTX U6U36tdqpx32O6rlZ1GmYonRcnEXqosreEwZeSwT5oF5d8McPLT9vW3mXlNREZPJzWtz35SoZXt6Br 7XMfsyvLJNWXTPDzGOdhPbN7PBT2I5 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 introduces SVE 2.2 as well as a few new optional features, update sysreg to reflect the changes in ID_AA64ZFR0_EL1 enumerating them. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 14284a120a5796bb510a0382984236eba9bf73ab..c792bd3b0afbb5fb7e438a4d760d9f2d15621eee 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1040,7 +1040,10 @@ UnsignedEnum 55:52 F32MM 0b0000 NI 0b0001 IMP EndEnum -Res0 51:48 +UnsignedEnum 51:48 F16MM + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 47:44 I8MM 0b0000 NI 0b0001 IMP @@ -1058,6 +1061,7 @@ Res0 31:28 UnsignedEnum 27:24 B16B16 0b0000 NI 0b0001 IMP + 0b0010 BFSCALE EndEnum UnsignedEnum 23:20 BF16 0b0000 NI @@ -1068,16 +1072,22 @@ UnsignedEnum 19:16 BitPerm 0b0000 NI 0b0001 IMP EndEnum -Res0 15:8 +UnsignedEnum 15:12 EltPerm + 0b0000 NI + 0b0001 IMP +EndEnum +Res0 11:8 UnsignedEnum 7:4 AES 0b0000 NI 0b0001 IMP 0b0010 PMULL128 + 0b0011 AES2 EndEnum UnsignedEnum 3:0 SVEver 0b0000 IMP 0b0001 SVE2 0b0010 SVE2p1 + 0b0011 SVE2p2 EndEnum EndSysreg From patchwork Wed Dec 11 01:02:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902680 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B9018A6D3; Wed, 11 Dec 2024 01:04:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879080; cv=none; b=k0uenUHYx4SZkDHa2zZ6FYXUGk0MqFR88bqpyW0Ex3L0nGtSByyYJMyrfUeFyOiBGJz62wnmXhLamNgiDGSWd6AgcuOWpCIWhFj6qCHEzcCubYNie1maSGbHpdnNU2/edTA30R0CMHSg9oOf856MVqYtukyvHnCixaowz/br7AU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879080; c=relaxed/simple; bh=D+ekxMaZJ4bu/QgKDMmDwTyVaCHyF9h+lu4yMHG3Fr4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ajUiC3kaUnJRzKIr4AqvTFU5Yq+jIGHUXzeSXUSIXB+A0ljCZu+9uqkJE6fw3d9eCooezBYcGHLI+CAmZWOxbBDjbC+Msd4ASje7GavzpSh2Kw1WNC7gfuDhj+qkmOyBphqoqUUQyJeYVN54eXrKZ55NMHpV/LRo4chd2cNSF0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Jig45qAH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Jig45qAH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 67295C4CEE4; Wed, 11 Dec 2024 01:04:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879079; bh=D+ekxMaZJ4bu/QgKDMmDwTyVaCHyF9h+lu4yMHG3Fr4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Jig45qAHCAYtmBYE5+CE8fxYhV7h9nuGy4oR8pubfZPFYILkV4+w9Zir+jn+PhZPK yCHF6/atwf8RvI2VTgFcwLWFe3EajnCCcO4PveBPCOT5vE0I/17CvH2kNoSMt0iAWK V8uJcYnvkW6dk0RsaHT3K/Lqjs1zsXfju9yl8BmtpRY8fMsRtw/yiKmyGPXOFSeK90 sBCCCGVau37CC7dlAj4F1zERyWIMlZ9U/nWltds0u3GUoD2ThF9SET1YuAx3OxonS9 4M3BWbFyjWXAj80jpNcB+XumEmPs+p388geiSwBl2p9PKbSrt7yZyt+jS344M3CxxT 9+Jc6mUs9nYiA== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:50 +0000 Subject: [PATCH v4 5/9] arm64/sysreg: Update ID_AA64SMFR0_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-5-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1279; i=broonie@kernel.org; h=from:subject:message-id; bh=D+ekxMaZJ4bu/QgKDMmDwTyVaCHyF9h+lu4yMHG3Fr4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUSn+pwvZbrPc/XVepAvxg2ayGL41bDZ0s6gR6C sj1dDx6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlEgAKCRAk1otyXVSH0EPtB/ 4hlGPRUu3sTAj3l0XPBJMqa0ifeT7VpAlUyazSgpagYgW8DUrwk4EhQ3EwS3wWdomSWQMgnMRnkDJr UwQyraELpVHC/G9wz+yWJ+7pTvInAojunLezWZ71QuQfa8CzbV9L3xhAuGcCHleOasEmU5QPOvxHjx klDQmsu1PaBM4Pb3MHzX0wSjBS65zhMPpAGU2cf+ysCV/x3d/uA4TBN2yQ5iDBfNk0tiYxYFiIeVyo 4w2z4iX9vy1p3k1yFbwlv+mtBlOXLo2XWU4x/ylbu/HxFeQ6iEszRqy6UZvo53XKeWP5jDNZd3BNS8 +enXEwH6APpaictQCWKmxhHj10+8yZ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 introduces SME 2.2 as well as a few new optional features, update sysreg to reflect the changes in ID_AA64SMFR0_EL1 enumerating them. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c792bd3b0afbb5fb7e438a4d760d9f2d15621eee..d78b12c59658b480739ae797f5ea2c2f14d8d765 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1105,6 +1105,7 @@ UnsignedEnum 59:56 SMEver 0b0000 SME 0b0001 SME2 0b0010 SME2p1 + 0b0011 SME2p2 0b0000 IMP EndEnum UnsignedEnum 55:52 I16I64 @@ -1169,7 +1170,36 @@ UnsignedEnum 28 SF8DP2 0b0 NI 0b1 IMP EndEnum -Res0 27:0 +UnsignedEnum 27 SF8MM8 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 26 SF8MM4 + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 25 SBitPerm + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 24 AES + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 23 SFEXPA + 0b0 NI + 0b1 IMP +EndEnum +Res0 22:17 +UnsignedEnum 16 STMOP + 0b0 NI + 0b1 IMP +EndEnum +Res0 15:1 +UnsignedEnum 0 SMOP4 + 0b0 NI + 0b1 IMP +EndEnum EndSysreg Sysreg ID_AA64FPFR0_EL1 3 0 0 4 7 From patchwork Wed Dec 11 01:02:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902681 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D9271A2643; Wed, 11 Dec 2024 01:04:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879083; cv=none; b=JyoU7tue8KHpX/Z2JqNiuhNKMB9+3K3AFahCemxUYGLBdLbMw8bCRcDVpHa1gluohPAHW6AaIX+fN7tNvC6dqb0mKCdRF9hO9tRJR8qzyfAYRilSB2q/5CP8wFy69pStnLWpyMR2O4q21E8N7yzqvWJ+N/SxxzpXh9Hn1aUt6yo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879083; c=relaxed/simple; bh=TIHTphWBuVOkUDtoZBC1frDZIcBdWo09SQC7mFjqspw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=svlpULQgCzPDjfgibtd6VxnZnkJyZdjufgNCr269MaBeIxVd51H23fCDdpHeyb4xdS01GCQmMN0Qv1hMpz5NP3kMT336Q/qKkj61fveJNmkQV16WQb0rlKjegPnATg0EbROYHPy4MtRjpiHTIvsWzJ8sHZBy91yGuw1gINu/IwA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RJIzxGO9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RJIzxGO9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D76FC4CEDE; Wed, 11 Dec 2024 01:04:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879082; bh=TIHTphWBuVOkUDtoZBC1frDZIcBdWo09SQC7mFjqspw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=RJIzxGO9ObOgo4oihtpBf38kU5wUdj9l4zW3P4wo7xEyRvnIw7g+d8J+qttSdL5XR gIlQs7VlHPrmfZPLrzt6UYCYKAeNR7CxLmBA1eOJSQF+dzFog9vV9OsqbuSxuEiYch gYi0PS5Z66LX1yfdSaILRs+zeJxSKhvviXO+ojtyLKFczernfbcJJjoq0MJWDJDRnD YN136ycnoj0y0yM3MxlODW98SPnT0L9MdSyLRsd9sxkeVWeKm/17RXMX65jKPYruBo GLAJ5AD6CPvUjMViyIyIDzS56knZgkQQoLBjZa5s30nFPuD3cKSLBxeygnYs77cntb y5c5zxZ2kokkQ== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:51 +0000 Subject: [PATCH v4 6/9] arm64/sysreg: Update ID_AA64ISAR2_EL1 to DDI0601 2024-09 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-6-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=827; i=broonie@kernel.org; h=from:subject:message-id; bh=TIHTphWBuVOkUDtoZBC1frDZIcBdWo09SQC7mFjqspw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUThsm18uEZtQLS9pYRiLAL4lh6QYuVYwITO2XT DTeVQQ+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlEwAKCRAk1otyXVSH0OvpB/ 0XPMGf/WfzIbveT4gNjNboBw7DD62/YxmpCCoPr/Q4BCY9k1xkCplBqi3c7E51jqf6MYkf0nGbBdvz WYHcklfjIUIAYgIV3KfrpKzL93LIqbEgTNO29gEMjOcoNlZ8x5WfMsodfOjI/Ux7ig7BQ4aDpR7S2r gFsKNEyUgTP7novphMpBMGg7CgP5dW3ywHZe9mr9tzcI333uQdAnBV9HsNBlxZ9/dXiAokuUvaK+g3 bwEK91IPZrTUoHMynJqsjXCyftINTo4sM/32BttYVWVWJVlUlBEL3TuPFcGfN2AS1TIKIYIvNf42Tv cKOoIWqh2OM2s5vE5mv2MZ5PWNLJ28 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB DDI0601 2024-09 introduces new features which are enumerated via ID_AA64ISAR2_EL1, update the sysreg file to reflect these updates. Signed-off-by: Mark Brown --- arch/arm64/tools/sysreg | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index d78b12c59658b480739ae797f5ea2c2f14d8d765..724762f0c1db223b5772f4f1b27720facb428bf1 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1556,12 +1556,16 @@ EndEnum UnsignedEnum 55:52 CSSC 0b0000 NI 0b0001 IMP + 0b0010 CMPBR EndEnum UnsignedEnum 51:48 RPRFM 0b0000 NI 0b0001 IMP EndEnum -Res0 47:44 +UnsignedEnum 47:44 PCDPHINT + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 43:40 PRFMSLC 0b0000 NI 0b0001 IMP From patchwork Wed Dec 11 01:02:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902682 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F3B71AF0B4; Wed, 11 Dec 2024 01:04:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879086; cv=none; b=MTFiGflWZbwHepGaPEPpDYSdJG5ZW+76HEKdHbCeW6DRHM4s16DHH3gINlVlbc7me9zOPtTWdhnl+qKSh9SwuRSYPjmZ3/3G/f/60L9O9QS6eAVcrMqCmMytIwII/EVs1BhPlzZK8oQLuvMoa/IaPdWdr/53RVrYkaSlWm+xOL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879086; c=relaxed/simple; bh=tQF2bkOES8pELS6AoX890Q67hdQxb7iIENpry3lJWio=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fUBb/8kIpAKkL/0XOHAV+4P9OLBOyJQ+WwUzo2pmTleZ3diE8RPXppnFPKhObd5ohuh51BxWMSM94wqFNWLfhr6JWOPFRJNlSY3ynfocSw8cGELKYp9vhAeLYVEgaX70bT/q4lCLWApjwU2U5LQvW0aTuwygJQ0J77tGyESRJSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=j+exqhvL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="j+exqhvL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 528A2C4CEDF; Wed, 11 Dec 2024 01:04:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879086; bh=tQF2bkOES8pELS6AoX890Q67hdQxb7iIENpry3lJWio=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=j+exqhvL0QdikujMHoc65Hqg9Mr5JYrJvWEPn2X0wQ0uP4wqv4HdpBV9Og4Pjtzop mz/fBMZhtt8UFz3Y6WVXLgslgTwSaGtDNd3QcAUP/hF6n8gcmE8FRiEKv/4GcUyK2b EyYeeUqKuF1xz/vLb2b3pnlFKKDdLdZgr/Qd6J29LgPLsuHXMMenbpojRl+0ql37s5 fFM5/RKFJ4P7ZFoI2gQw6xEWTLcC8LcUO5fen0ZDLcIeVQOEcsZh54H+4BE2Z9YiUt dO3CC8ChQkFGX5Y6O8Q5hXU7/8xEagK1mdQ8h35mzIvmaW2JUkFIgfzjyf/w2qaYSt fj5jOg7pcgAfQ== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:52 +0000 Subject: [PATCH v4 7/9] arm64/hwcap: Describe 2024 dpISA extensions to userspace Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-7-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=14319; i=broonie@kernel.org; h=from:subject:message-id; bh=tQF2bkOES8pELS6AoX890Q67hdQxb7iIENpry3lJWio=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUTBCFAPOd+0/zmrsEaPATq4GutpRFW33rxnzPx +HMm2YeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlEwAKCRAk1otyXVSH0AKjB/ 0bCzuIi0j3aGooqIzTG64BSAMgslTwZbRmCQIoD/S7cSJdDh8EWrdfvm3BUTue9iPyx7IsgGxFPGfS Sx/Ero1f4b1SLTdLWa385t/XITbnTACx6VNqd7ilhRxUBnKBAcRQZU8xdoQx4ki6gIIUUAKbLn13dG /P5Yq09ziUhZDCosNq/VSamGFmAmvrzdCbHeZHSZxpVv1noAMXXcRGq+BVZqXkTA9EohSOOVi0JAAO zsKETCfPMfpZMuAd9zszrZn1nIvYNeLlajgt+NegiBaobpKf+/nr7G1koWTDPzrMLd8CJgYR83hs4l MBePMjQYATEIxP7lkJ9deYApvkW519 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2024 dpISA introduces a number of architecture features all of which only add new instructions so only require the addition of hwcaps and ID register visibility. Signed-off-by: Mark Brown --- Documentation/arch/arm64/elf_hwcaps.rst | 51 +++++++++++++++++++++++++++++++++ arch/arm64/include/asm/hwcap.h | 17 +++++++++++ arch/arm64/include/uapi/asm/hwcap.h | 17 +++++++++++ arch/arm64/kernel/cpufeature.c | 35 ++++++++++++++++++++++ arch/arm64/kernel/cpuinfo.c | 17 +++++++++++ 5 files changed, 137 insertions(+) diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 2ff922a406ad83d0dff8104a6e362ac6b02d0e1f..7c99894ca3e8f5433b1a0db6a4679395e5cd9ecc 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -174,6 +174,57 @@ HWCAP_GCS Functionality implied by ID_AA64PFR1_EL1.GCS == 0b1, as described by Documentation/arch/arm64/gcs.rst. +HWCAP_CMPBR + Functionality implied by ID_AA64ISAR2_EL1.CSSC == 0b0010. + +HWCAP_FPRCVT + Functionality implied by ID_AA64ISAR3_EL1.FPRCVT == 0b0001. + +HWCAP_F8MM8 + Functionality implied by ID_AA64FPFR0_EL1.F8MM8 == 0b0001. + +HWCAP_F8MM4 + Functionality implied by ID_AA64FPFR0_EL1.F8MM4 == 0b0001. + +HWCAP_SVE_F16MM + Functionality implied by ID_AA64ZFR0_EL1.F16MM == 0b0001. + +HWCAP_SVE_ELTPERM + Functionality implied by ID_AA64ZFR0_EL1.ELTPERM == 0b0001. + +HWCAP_SVE_AES2 + Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0011. + +HWCAP_SVE_BFSCALE + Functionality implied by ID_AA64ZFR0_EL1.B16B16 == 0b0010. + +HWCAP_SVE2P2 + Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0011. + +HWCAP_SME2P2 + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0011. + +HWCAP_SME_SF8MM8 + Functionality implied by ID_AA64SMFR0_EL1.SF8MM8 == 0b1. + +HWCAP_SME_SF8MM4 + Functionality implied by ID_AA64SMFR0_EL1.SF8MM4 == 0b1. + +HWCAP_SME_SBITPERM + Functionality implied by ID_AA64SMFR0_EL1.SBitPerm == 0b1. + +HWCAP_SME_AES + Functionality implied by ID_AA64SMFR0_EL1.AES == 0b1. + +HWCAP_SME_SFEXPA + Functionality implied by ID_AA64SMFR0_EL1.SFEXPA == 0b1. + +HWCAP_SME_STMOP + Functionality implied by ID_AA64SMFR0_EL1.STMOP == 0b1. + +HWCAP_SME_SMOP4 + Functionality implied by ID_AA64SMFR0_EL1.SMOP4 == 0b1. + HWCAP2_DCPODP Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010. diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 2b6c61c608e2cd107503b09aba5aaeab639b759a..dbec921ee39c8c897f3e1e1c84d522b5b57130bb 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -93,6 +93,23 @@ #define KERNEL_HWCAP_PACA __khwcap_feature(PACA) #define KERNEL_HWCAP_PACG __khwcap_feature(PACG) #define KERNEL_HWCAP_GCS __khwcap_feature(GCS) +#define KERNEL_HWCAP_CMPBR __khwcap_feature(CMPBR) +#define KERNEL_HWCAP_FPRCVT __khwcap_feature(FPRCVT) +#define KERNEL_HWCAP_F8MM8 __khwcap_feature(F8MM8) +#define KERNEL_HWCAP_F8MM4 __khwcap_feature(F8MM4) +#define KERNEL_HWCAP_SVE_F16MM __khwcap_feature(SVE_F16MM) +#define KERNEL_HWCAP_SVE_ELTPERM __khwcap_feature(SVE_ELTPERM) +#define KERNEL_HWCAP_SVE_AES2 __khwcap_feature(SVE_AES2) +#define KERNEL_HWCAP_SVE_BFSCALE __khwcap_feature(SVE_BFSCALE) +#define KERNEL_HWCAP_SVE2P2 __khwcap_feature(SVE2P2) +#define KERNEL_HWCAP_SME2P2 __khwcap_feature(SME2P2) +#define KERNEL_HWCAP_SME_SF8MM8 __khwcap_feature(SME_SF8MM8) +#define KERNEL_HWCAP_SME_SF8MM4 __khwcap_feature(SME_SF8MM4) +#define KERNEL_HWCAP_SME_SBITPERM __khwcap_feature(SME_SBITPERM) +#define KERNEL_HWCAP_SME_AES __khwcap_feature(SME_AES) +#define KERNEL_HWCAP_SME_SFEXPA __khwcap_feature(SME_SFEXPA) +#define KERNEL_HWCAP_SME_STMOP __khwcap_feature(SME_STMOP) +#define KERNEL_HWCAP_SME_SMOP4 __khwcap_feature(SME_SMOP4) #define __khwcap2_feature(x) (const_ilog2(HWCAP2_ ## x) + 64) #define KERNEL_HWCAP_DCPODP __khwcap2_feature(DCPODP) diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 48d46b768eaec4c307360cd3bee8b564687f4b88..61fbc88d2bfb81d0bad639ed533ac67440ae2fc4 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -56,6 +56,23 @@ #define HWCAP_PACA (1 << 30) #define HWCAP_PACG (1UL << 31) #define HWCAP_GCS (1UL << 32) +#define HWCAP_CMPBR (1UL << 33) +#define HWCAP_FPRCVT (1UL << 34) +#define HWCAP_F8MM8 (1UL << 35) +#define HWCAP_F8MM4 (1UL << 36) +#define HWCAP_SVE_F16MM (1UL << 37) +#define HWCAP_SVE_ELTPERM (1UL << 38) +#define HWCAP_SVE_AES2 (1UL << 39) +#define HWCAP_SVE_BFSCALE (1UL << 40) +#define HWCAP_SVE2P2 (1UL << 41) +#define HWCAP_SME2P2 (1UL << 42) +#define HWCAP_SME_SF8MM8 (1UL << 43) +#define HWCAP_SME_SF8MM4 (1UL << 44) +#define HWCAP_SME_SBITPERM (1UL << 45) +#define HWCAP_SME_AES (1UL << 46) +#define HWCAP_SME_SFEXPA (1UL << 47) +#define HWCAP_SME_STMOP (1UL << 48) +#define HWCAP_SME_SMOP4 (1UL << 49) /* * HWCAP2 flags - for AT_HWCAP2 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 6ce71f444ed84f9056196bb21bbfac61c9687e30..7ba73fdee6deb57cd745ff684eeb97f66d2ea85f 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -268,6 +268,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -317,6 +318,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), @@ -329,6 +332,8 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), + FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), @@ -373,6 +378,20 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8MM8_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8MM4_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), + FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), ARM64_FTR_END, }; @@ -381,6 +400,8 @@ static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), ARM64_FTR_END, @@ -3092,12 +3113,15 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), #ifdef CONFIG_ARM64_SVE HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), + HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), HWCAP_CAP(ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), HWCAP_CAP(ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), HWCAP_CAP(ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), + HWCAP_CAP(ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), HWCAP_CAP(ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), + HWCAP_CAP(ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), HWCAP_CAP(ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), HWCAP_CAP(ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), @@ -3105,6 +3129,8 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), HWCAP_CAP(ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), HWCAP_CAP(ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), + HWCAP_CAP(ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), + HWCAP_CAP(ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), #endif #ifdef CONFIG_ARM64_GCS HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), @@ -3124,6 +3150,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), + HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), @@ -3133,6 +3160,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), HWCAP_CAP(ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), HWCAP_CAP(ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), + HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), HWCAP_CAP(ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), HWCAP_CAP(ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), @@ -3150,6 +3178,13 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), HWCAP_CAP(ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM8), + HWCAP_CAP(ID_AA64SMFR0_EL1, SF8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8MM4), + HWCAP_CAP(ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), + HWCAP_CAP(ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), + HWCAP_CAP(ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), + HWCAP_CAP(ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), + HWCAP_CAP(ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), #endif /* CONFIG_ARM64_SME */ HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index d79e88fccdfce427507e7a34c5959ce6309cbd12..9861291843d8fbcc5f8e68e2b9eaac65a0b37c22 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -145,6 +145,23 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", [KERNEL_HWCAP_POE] = "poe", + [KERNEL_HWCAP_CMPBR] = "cmpbr", + [KERNEL_HWCAP_FPRCVT] = "fprcvt", + [KERNEL_HWCAP_F8MM8] = "f8mm8", + [KERNEL_HWCAP_F8MM4] = "f8mm4", + [KERNEL_HWCAP_SVE_F16MM] = "svef16mm", + [KERNEL_HWCAP_SVE_ELTPERM] = "sveeltperm", + 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(2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="est+jKTl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7478FC4CEDE; Wed, 11 Dec 2024 01:04:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879089; bh=cKym5jL1wVVG9G/7MeEDQVRM4fdPvM6wIXw2UfuLn2s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=est+jKTlMjjT0LteUy3l0s/bqzIPRBoO3iJZw0xbbgJUgc39gJnLG2FeGJUB7D5lJ BMp18/ena+cJH9IGZ6xCSER8+HFKMakvpRy1zkAfSK8TAhe+8Z2TtlnOV4zcjh8VQm DhJVCaOC0E3U55m93B/JaKUINPcYMsFYLOz7tP7FXkM4ysiRegyYJ76pOybkDUj0U5 IqrqHhEzJy0fFR4aB+cfD12Dvb5uOEshQz7m4qq+w0JL1f1t8nIvarVRGZdbG37Jnf 3jToVCG7N0Hd/RrhSc6E6HS8CYazhQFS7uvRb8jba0MZ0CEOWKCd7EJDqYtPEUdCH5 va5Byh4MWjXLw== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:53 +0000 Subject: [PATCH v4 8/9] KVM: arm64: Allow control of dpISA extensions in ID_AA64ISAR3_EL1 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-8-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=1369; i=broonie@kernel.org; h=from:subject:message-id; bh=cKym5jL1wVVG9G/7MeEDQVRM4fdPvM6wIXw2UfuLn2s=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUUhmVbDtN4zgUDprg+DePqkfqBwUsINMtFA3QJ 1gHnRzSJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlFAAKCRAk1otyXVSH0KZNB/ 9kB6zoenu8X62lAzSiX4YYO7L6QYm3FGYNXOKN+jxzU5x+tdlQmsJmsZlWwG5i5WMlttwWiCn6nVqe Ym449g++ZZ5W1OiLpJOAxZhSMg26IvKox88qwXM+qdcROa0e5qgUiNMzlfHUTB8+/RT7tkDm4+s4kK POUeMmmA3u3gVm5wS4SWIF5I0FI0iCiTc2XU54nHfD8u+UifrayrbiTqJewtV9iHiSNH1sM+HrKtY1 xvKpLgAElxMdEypMJvH5462BQKDj4PQISCJIGMCSBM+LROwiIZ2pwViVSYmL/52Hm9MaLrG0jcc2iB C3FUwcAO2DOUvyaQzphj7Bap5OvCu7 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB ID_AA64ISAR3_EL1 is currently marked as unallocated in KVM but does have a number of bitfields defined in it. Expose FPRCVT and FAMINMAX, two simple instruction only extensions to guests. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 83c6b4a07ef56cf0ed9c8751ec80686f45dca6b2..6efbe3f4a579afd1874c4cf844c1c1249ae8b942 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1604,6 +1604,9 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, if (!cpus_have_final_cap(ARM64_HAS_WFXT)) val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT); break; + case SYS_ID_AA64ISAR3_EL1: + val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX; + break; case SYS_ID_AA64MMFR2_EL1: val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK; break; @@ -2608,7 +2611,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | ID_AA64ISAR2_EL1_APA3 | ID_AA64ISAR2_EL1_GPA3)), - ID_UNALLOCATED(6,3), + ID_WRITABLE(ID_AA64ISAR3_EL1, (ID_AA64ISAR3_EL1_FPRCVT | + ID_AA64ISAR3_EL1_FAMINMAX)), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), ID_UNALLOCATED(6,6), From patchwork Wed Dec 11 01:02:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13902684 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EC371D63FA; Wed, 11 Dec 2024 01:04:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879092; cv=none; b=LXNF2CNgFHZQo13y10JWEqovstruqfKLwKN3AKUz8sOPUEE1EKysl4F5acvsrkmhv97CtEQBBDlglo6D0qXqZnyClFd1+gclGIdwGO8S+N2Arkf0xfEeu9q1rU7ZF37kNJ6FVWc5wGiDX0fouuVc4vCw2FhenTybSVaJIoT3n+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733879092; c=relaxed/simple; bh=iv/w/FqsQC6tPqMPucMTK26kMUPc3meLY49LgS4Xj9U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aqdSAakU09Q4S8FVUUory6VzWjrphYBgVR65stLPSZ+HTNH6cbqUFGLNxIaRNP74OK/aJ+MWafIP6w4HtyyB7ib41dyk6Tnh6Xp7jE9cXmSPo4tQWj1DMqBDb7drbnL046O/fdDqZ4PHVui5BwQH1Il2I9plqSuJC4hRODpsYNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fSt1lCZD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fSt1lCZD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6C2C0C4CEDF; Wed, 11 Dec 2024 01:04:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733879092; bh=iv/w/FqsQC6tPqMPucMTK26kMUPc3meLY49LgS4Xj9U=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fSt1lCZDZEjQ8/BBA+7Vgt6iSnCjnpGrhgDmchKTkWVYrhWouQWul8ZZDj3f9WEHc vWLi7cw8GF1GwV7SlSbeRy+53XLeSd+d0BDmIDpN6ZO1BajlbbTQeHInCqCZnV6Bsb iiybyBGSYMKT+AHOCPQNkxRW6Sx7tGhut1l+US/0bhn4FHV9Tg36ec1GWSJyMJjD++ aTqJw0kfPnr61SnR8RmU/P1pSs6NnghgQRpwVxzUlXtVhuR5Ecg8tLjfmTVWO81IUX dC2Y917qisk9/RotAZIea6OrK59iqUZ0ZcKN4h3zkzi0MSGmTwsdCOoiUqR9XYPYK1 jWhXPuSzNXcRw== From: Mark Brown Date: Wed, 11 Dec 2024 01:02:54 +0000 Subject: [PATCH v4 9/9] kselftest/arm64: Add 2024 dpISA extensions to hwcap test Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-arm64-2024-dpisa-v4-9-0fd403876df2@kernel.org> References: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> In-Reply-To: <20241211-arm64-2024-dpisa-v4-0-0fd403876df2@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-9b746 X-Developer-Signature: v=1; a=openpgp-sha256; l=10054; i=broonie@kernel.org; h=from:subject:message-id; bh=iv/w/FqsQC6tPqMPucMTK26kMUPc3meLY49LgS4Xj9U=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBnWOUVzEm5VT+wUpOmup7O9a342BuGW98g3WzIW+9N s12hKhCJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZ1jlFQAKCRAk1otyXVSH0KBXB/ 9r71PKDqagzQlH5Qur1yeAu9PrW/R9QpR0lJysjytV2mkBjt2eX9kOANcKjqxgbCXgzhdQfNpIt0pI Ub9G7QOD16Nk2Q/+OdzLepW9ECU1cr3tlf+BnnbHO6z3IBjgwmBYUKgSXzqg/bBx1+dEiltpxajcou zJeNmXTWGZYh+sggpLrPXmRJtERzyOeyAU30D7EXT7L/7WwAsfHBTOC1TqiixwZxSUm3WEK479yTrP Q59CReB/4W2Qzru1DiDJUpgw78gQiiYyNOIEHIGobBNbROfTpSOEFf7D3a7ANfNzR6e04M3Jn4+9Hj Rf9whhn63m02exaj1IIntnC0yBZ3JW X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add coverage of the hwcaps for the 2024 dpISA extensions to the hwcap test. We don't actually test SIGILL generation for CMPBR since the need to branch makes it a pain to generate and the SIGILL detection would be unreliable anyway. Since this should be very unusual we provide a stub function rather than supporting a missing test. The sigill functions aren't well sorted in the file so the ordering is a bit random. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/abi/hwcap.c | 273 +++++++++++++++++++++++++++++- 1 file changed, 271 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/arm64/abi/hwcap.c b/tools/testing/selftests/arm64/abi/hwcap.c index 0029ed9c5c9aa4451f3d0573ee672eca993fb2f4..2a230cfa4cb4108580a16161e2df03a513710dbc 100644 --- a/tools/testing/selftests/arm64/abi/hwcap.c +++ b/tools/testing/selftests/arm64/abi/hwcap.c @@ -46,6 +46,12 @@ static void atomics_sigill(void) asm volatile(".inst 0xb82003ff" : : : ); } +static void cmpbr_sigill(void) +{ + /* Not implemented, too complicated and unreliable anyway */ +} + + static void crc32_sigill(void) { /* CRC32W W0, W0, W1 */ @@ -82,6 +88,18 @@ static void f8fma_sigill(void) asm volatile(".inst 0xec0fc00"); } +static void f8mm4_sigill(void) +{ + /* FMMLA V0.4SH, V0.16B, V0.16B */ + asm volatile(".inst 0x6e00ec00"); +} + +static void f8mm8_sigill(void) +{ + /* FMMLA V0.4S, V0.16B, V0.16B */ + asm volatile(".inst 0x6e80ec00"); +} + static void faminmax_sigill(void) { /* FAMIN V0.4H, V0.4H, V0.4H */ @@ -98,6 +116,12 @@ static void fpmr_sigill(void) asm volatile("mrs x0, S3_3_C4_C4_2" : : : "x0"); } +static void fprcvt_sigill(void) +{ + /* FCVTAS S0, H0 */ + asm volatile(".inst 0x1efa0000"); +} + static void gcs_sigill(void) { unsigned long *gcspr; @@ -226,6 +250,42 @@ static void sme2p1_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } +static void sme2p2_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* UXTB Z0.D, P0/Z, Z0.D */ + asm volatile(".inst 0x4c1a000" : : : ); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme_aes_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* AESD z0.b, z0.b, z0.b */ + asm volatile(".inst 0x4522e400" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void sme_sbitperm_sigill(void) +{ + /* SMSTART SM */ + asm volatile("msr S0_3_C4_C3_3, xzr" : : : ); + + /* BDEP Z0.B, Z0.B, Z0.B */ + asm volatile(".inst 0x4500b400" : : : "z0"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smei16i32_sigill(void) { /* SMSTART */ @@ -334,13 +394,73 @@ static void smesf8dp4_sigill(void) asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); } +static void smesf8mm8_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMMLA V0.4S, V0.16B, V0.16B */ + asm volatile(".inst 0x6e80ec00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesf8mm4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FMMLA V0.4SH, V0.16B, V0.16B */ + asm volatile(".inst 0x6e00ec00"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + static void smesf8fma_sigill(void) { /* SMSTART */ asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); - /* FMLALB V0.8H, V0.16B, V0.16B */ - asm volatile(".inst 0xec0fc00"); + /* FMLALB Z0.8H, Z0.B, Z0.B */ + asm volatile(".inst 0x64205000"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesfexpa_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* FEXPA Z0.D, Z0.D */ + asm volatile(".inst 0x04e0b800"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smesmop4_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* SMOP4A ZA0.S, Z0.B, { Z0.B - Z1.B } */ + asm volatile(".inst 0x80108000"); + + /* SMSTOP */ + asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); +} + +static void smestmop_sigill(void) +{ + /* SMSTART */ + asm volatile("msr S0_3_C4_C7_3, xzr" : : : ); + + /* STMOPA ZA0.S, { Z0.H - Z1.H }, Z0.H, Z20[0] */ + asm volatile(".inst 0x80408008"); /* SMSTOP */ asm volatile("msr S0_3_C4_C6_3, xzr" : : : ); @@ -364,18 +484,42 @@ static void sve2p1_sigill(void) asm volatile(".inst 0x65000000" : : : "z0"); } +static void sve2p2_sigill(void) +{ + /* NOT Z0.D, P0/Z, Z0.D */ + asm volatile(".inst 0x4cea000" : : : "z0"); +} + static void sveaes_sigill(void) { /* AESD z0.b, z0.b, z0.b */ asm volatile(".inst 0x4522e400" : : : "z0"); } +static void sveaes2_sigill(void) +{ + /* AESD {Z0.B - Z1.B }, { Z0.B - Z1.B }, Z0.Q */ + asm volatile(".inst 0x4522ec00" : : : "z0"); +} + static void sveb16b16_sigill(void) { /* BFADD Z0.H, Z0.H, Z0.H */ asm volatile(".inst 0x65000000" : : : ); } +static void svebfscale_sigill(void) +{ + /* BFSCALE Z0.H, P0/M, Z0.H, Z0.H */ + asm volatile(".inst 0x65098000" : : : "z0"); +} + +static void svef16mm_sigill(void) +{ + /* FMMLA Z0.S, Z0.H, Z0.H */ + asm volatile(".inst 0x6420e400"); +} + static void svepmull_sigill(void) { /* PMULLB Z0.Q, Z0.D, Z0.D */ @@ -394,6 +538,12 @@ static void svesha3_sigill(void) asm volatile(".inst 0x4203800" : : : "z0"); } +static void sveeltperm_sigill(void) +{ + /* COMPACT Z0.B, P0, Z0.B */ + asm volatile(".inst 0x5218000" : : : "x0"); +} + static void svesm4_sigill(void) { /* SM4E Z0.S, Z0.S, Z0.S */ @@ -469,6 +619,13 @@ static const struct hwcap_data { .cpuinfo = "aes", .sigill_fn = aes_sigill, }, + { + .name = "CMPBR", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_CMPBR, + .cpuinfo = "cmpbr", + .sigill_fn = cmpbr_sigill, + }, { .name = "CRC32", .at_hwcap = AT_HWCAP, @@ -523,6 +680,20 @@ static const struct hwcap_data { .cpuinfo = "f8fma", .sigill_fn = f8fma_sigill, }, + { + .name = "F8MM8", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_F8MM8, + .cpuinfo = "f8mm8", + .sigill_fn = f8mm8_sigill, + }, + { + .name = "F8MM4", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_F8MM4, + .cpuinfo = "f8mm4", + .sigill_fn = f8mm4_sigill, + }, { .name = "FAMINMAX", .at_hwcap = AT_HWCAP2, @@ -545,6 +716,13 @@ static const struct hwcap_data { .sigill_fn = fpmr_sigill, .sigill_reliable = true, }, + { + .name = "FPRCVT", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_FPRCVT, + .cpuinfo = "fprcvt", + .sigill_fn = fprcvt_sigill, + }, { .name = "GCS", .at_hwcap = AT_HWCAP, @@ -691,6 +869,20 @@ static const struct hwcap_data { .cpuinfo = "sme2p1", .sigill_fn = sme2p1_sigill, }, + { + .name = "SME 2.2", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME2P2, + .cpuinfo = "sme2p2", + .sigill_fn = sme2p2_sigill, + }, + { + .name = "SME AES", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_AES, + .cpuinfo = "smeaes", + .sigill_fn = sme_aes_sigill, + }, { .name = "SME I16I32", .at_hwcap = AT_HWCAP2, @@ -740,6 +932,13 @@ static const struct hwcap_data { .cpuinfo = "smelutv2", .sigill_fn = smelutv2_sigill, }, + { + .name = "SME SBITPERM", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_SBITPERM, + .cpuinfo = "smesbitperm", + .sigill_fn = sme_sbitperm_sigill, + }, { .name = "SME SF8FMA", .at_hwcap = AT_HWCAP2, @@ -747,6 +946,20 @@ static const struct hwcap_data { .cpuinfo = "smesf8fma", .sigill_fn = smesf8fma_sigill, }, + { + .name = "SME SF8MM8", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_SF8MM8, + .cpuinfo = "smesf8mm8", + .sigill_fn = smesf8mm8_sigill, + }, + { + .name = "SME SF8MM4", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_SF8MM8, + .cpuinfo = "smesf8mm4", + .sigill_fn = smesf8mm4_sigill, + }, { .name = "SME SF8DP2", .at_hwcap = AT_HWCAP2, @@ -761,6 +974,27 @@ static const struct hwcap_data { .cpuinfo = "smesf8dp4", .sigill_fn = smesf8dp4_sigill, }, + { + .name = "SME SFEXPA", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_SFEXPA, + .cpuinfo = "smesfexpa", + .sigill_fn = smesfexpa_sigill, + }, + { + .name = "SME SMOP4", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_SMOP4, + .cpuinfo = "smesmop4", + .sigill_fn = smesmop4_sigill, + }, + { + .name = "SME STMOP", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SME_STMOP, + .cpuinfo = "smestmop", + .sigill_fn = smestmop_sigill, + }, { .name = "SVE", .at_hwcap = AT_HWCAP, @@ -783,6 +1017,13 @@ static const struct hwcap_data { .cpuinfo = "sve2p1", .sigill_fn = sve2p1_sigill, }, + { + .name = "SVE 2.2", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SVE2P2, + .cpuinfo = "sve2p2", + .sigill_fn = sve2p2_sigill, + }, { .name = "SVE AES", .at_hwcap = AT_HWCAP2, @@ -790,6 +1031,34 @@ static const struct hwcap_data { .cpuinfo = "sveaes", .sigill_fn = sveaes_sigill, }, + { + .name = "SVE AES2", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SVE_AES2, + .cpuinfo = "sveaes2", + .sigill_fn = sveaes2_sigill, + }, + { + .name = "SVE BFSCALE", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SVE_BFSCALE, + .cpuinfo = "svebfscale", + .sigill_fn = svebfscale_sigill, + }, + { + .name = "SVE ELTPERM", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SVE_ELTPERM, + .cpuinfo = "sveeltperm", + .sigill_fn = sveeltperm_sigill, + }, + { + .name = "SVE F16MM", + .at_hwcap = AT_HWCAP, + .hwcap_bit = HWCAP_SVE_F16MM, + .cpuinfo = "svef16mm", + .sigill_fn = svef16mm_sigill, + }, { .name = "SVE2 B16B16", .at_hwcap = AT_HWCAP2,