From patchwork Wed Dec 11 08:04:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri Fedrau via B4 Relay X-Patchwork-Id: 13903101 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7B8F1C5CD6; Wed, 11 Dec 2024 08:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733904293; cv=none; b=T98+0tKFIxWcZvuBLPw/XgBEiiEPN6aa6RcsTBfhzKLK9+O6W7h1i4LS4ecHxocWY4DnekJ8NASOIjeBu1vlnLrLeWVNT/oCLXDwztromDwtMcKc9RIwmv8m/BwqHAePcxk0ZTH1c8XCixCZ312Fefdiw7IJ/Uaz3xOBLGNZoWE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733904293; c=relaxed/simple; bh=4gzYsX5DOfJVDxZcD+g7jTzyct3WDgauHlFyvdfIIgw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t8hhDYfUWn+kB9jQu9UXK/u4y6Zh/fgBawWTsbqFQnHk/HpRZVtUEoz+dwbEmD6fuY2vVkgYRTOx3QBRQOECJ1ZxRqWqALm4r4csp0HI45ZzXgp+ya2ivBk7fwMT7aeDNDHeiRYfoMvbzgH2PnDusQIxTPMo+e4RBqBQ8w7nuDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Toat3qSg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Toat3qSg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4F5C2C4CEE0; Wed, 11 Dec 2024 08:04:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733904293; bh=4gzYsX5DOfJVDxZcD+g7jTzyct3WDgauHlFyvdfIIgw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Toat3qSg9Z6DoZ18gRpeqBpL3DR/OxqphuReM+YWFKcjXBuLqk28HLwpHap7sBF2c w2VnD+cbMrkgHlW0OOuj4iZ6e5ayN2bV57cqf+714YyUOsBf4NifdJGKSVBR59GnQe hc4h2SzTnxhl2J6PMppv7SeBXcN3f474nlkUxK0yBfXO3eRGElvv8G84eC25lyYgEN dv3Ua228QlndPiYnCVLWodakp4z7LILAHY17yaZOUApxLUzgOIBH2ILcVSk26Dx4WF nBwPAv01IxyYetQuP/YYnTGTIlBMTdDjZwhaQGYs9II27O2zBQC3N6FhpcpGMDw5Yl qVtAy+VzoplTw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 325ABE77180; Wed, 11 Dec 2024 08:04:53 +0000 (UTC) From: Dimitri Fedrau via B4 Relay Date: Wed, 11 Dec 2024 09:04:39 +0100 Subject: [PATCH net-next v2 1/2] dt-bindings: net: dp83822: Add support for GPIO2 clock output Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-dp83822-gpio2-clk-out-v2-1-614a54f6acab@liebherr.com> References: <20241211-dp83822-gpio2-clk-out-v2-0-614a54f6acab@liebherr.com> In-Reply-To: <20241211-dp83822-gpio2-clk-out-v2-0-614a54f6acab@liebherr.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dimitri Fedrau , Dimitri Fedrau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733904292; l=2015; i=dimitri.fedrau@liebherr.com; s=20241202; h=from:subject:message-id; bh=UwvludAxxAD5J0tfbp9WDwPSofbmqEDrg/Gfp7I54q8=; b=aaFtX/2uzrz07LlMHrp6aXO+OB5NYErym0t0TQvVgO7y0REfZGWQGKft5dOIyd1ABr9fCry/R lk/zcVqmv1CCJf1MPRBA4wMFF8JWpMkC0HXXYmoSVVM3u+oAzPubNfD X-Developer-Key: i=dimitri.fedrau@liebherr.com; a=ed25519; pk=rT653x09JSQvotxIqQl4/XiI4AOiBZrdOGvxDUbb5m8= X-Endpoint-Received: by B4 Relay for dimitri.fedrau@liebherr.com/20241202 with auth_id=290 X-Original-From: Dimitri Fedrau Reply-To: dimitri.fedrau@liebherr.com X-Patchwork-Delegate: kuba@kernel.org From: Dimitri Fedrau The GPIO2 pin on the DP83822 can be configured as clock output. Add binding to support this feature. Signed-off-by: Dimitri Fedrau --- .../devicetree/bindings/net/ti,dp83822.yaml | 7 +++++++ include/dt-bindings/net/ti-dp83822.h | 21 +++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml index 784866ea392b2083e93d8dc9aaea93b70dc80934..4a4dc794f21162c6a61c3daeeffa08e666034679 100644 --- a/Documentation/devicetree/bindings/net/ti,dp83822.yaml +++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml @@ -96,6 +96,13 @@ properties: - master - slave + ti,gpio2-clk-out: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DP83822 PHY only. + Muxing option for GPIO2 pin. See dt-bindings/net/ti-dp83822.h for + applicable values. When omitted, the PHY's default will be left as is. + required: - reg diff --git a/include/dt-bindings/net/ti-dp83822.h b/include/dt-bindings/net/ti-dp83822.h new file mode 100644 index 0000000000000000000000000000000000000000..d569c90618b7bcae9ffe44eb041f7dae2e74e5d1 --- /dev/null +++ b/include/dt-bindings/net/ti-dp83822.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Device Tree constants for the Texas Instruments DP83822 PHY + * + * Copyright (C) 2024 Liebherr-Electronics and Drives GmbH + * + * Author: Dimitri Fedrau + */ + +#ifndef _DT_BINDINGS_TI_DP83822_H +#define _DT_BINDINGS_TI_DP83822_H + +/* IO_MUX_GPIO_CTRL - Clock source selection */ +#define DP83822_CLK_SRC_MAC_IF 0x0 +#define DP83822_CLK_SRC_XI 0x1 +#define DP83822_CLK_SRC_INT_REF 0x2 +#define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4 +#define DP83822_CLK_SRC_FREE_RUNNING 0x6 +#define DP83822_CLK_SRC_RECOVERED 0x7 + +#endif From patchwork Wed Dec 11 08:04:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dimitri Fedrau via B4 Relay X-Patchwork-Id: 13903102 X-Patchwork-Delegate: kuba@kernel.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7C7F1CBE8C; Wed, 11 Dec 2024 08:04:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733904293; cv=none; b=I3Bt99oF3UieRgDEfr2+xrJBcm+KGGN+tFcHEXJNHwsDLGJpX+rPLzgQK9p8pmwSEsWlg0s3Zkyfo4YDi+iR9Za7g9R2GEVT/nS5pQAiocI54yR+OrzL0meCgTxmSBrU15/nutsQoL/hwXysebUzkNOS4Wl9sNn+SIhD2sv4fBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733904293; c=relaxed/simple; bh=/SwR3WBX/5RiStwbhzSqQodMFhGLLTKGvjGqpDQMhcA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XKDbGrARxpv7CP4zgDxPGa5l7xcCaV1N+746ijqLVyv503t9qAdLfpUG9wCchkq0Y85cJYIxxBh3AFvnE7DO5DcPqHdbdqHWm6hmezuaHFNpS+3aOWCzV6IF++0Z5mpflotTmJABgqoE1SNQ9qZAQUdM1bD4jc8LaulLkeA3j80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ifR7if7Q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ifR7if7Q" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5A002C4CEDF; Wed, 11 Dec 2024 08:04:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733904293; bh=/SwR3WBX/5RiStwbhzSqQodMFhGLLTKGvjGqpDQMhcA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ifR7if7Q4DWdlfzRgS5Rt+28t5UCXYo2/auU2HjmhTCQQE67UvMyEaxE9rhb7Mu+I xeqLpMbU3NMRimERyvMd+/p3B2Lpq6FYtANnka481G70E8lWotYaqn8ld6Y4Kbmen0 5l7JOb7lHaaaUVyKjlxi9XXDUG3G7h788O7gkq0n+BzcnNvKYHx7wYyRZ/C31wCrtt +lYcjoTeYOY1slRekeVb2jBbmesWG8nTvvdSuzeljeVLdlbvAHxvLGihek35yxCSPx 1pa/LN7ov4G9jArzkD58GtTZJGqlukpaHV7fWtepd9kGa1iX2ybVrbj5SGa5UWiFWa 8YiZ2jEwL+4pw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47949E77183; Wed, 11 Dec 2024 08:04:53 +0000 (UTC) From: Dimitri Fedrau via B4 Relay Date: Wed, 11 Dec 2024 09:04:40 +0100 Subject: [PATCH net-next v2 2/2] net: phy: dp83822: Add support for GPIO2 clock output Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-dp83822-gpio2-clk-out-v2-2-614a54f6acab@liebherr.com> References: <20241211-dp83822-gpio2-clk-out-v2-0-614a54f6acab@liebherr.com> In-Reply-To: <20241211-dp83822-gpio2-clk-out-v2-0-614a54f6acab@liebherr.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dimitri Fedrau , Dimitri Fedrau X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733904292; l=3323; i=dimitri.fedrau@liebherr.com; s=20241202; h=from:subject:message-id; bh=ocCCgiir9YwkF+ZSQqZS9864rONkKgcoc4c4WnPnqVY=; b=yv1U8A6QoIBwBBqKl4gSs2JSbfnbvmc98aZjStsY5+TxTQTke+7Ebc67gEeHDX/hUj8EcZK04 Ps6bx+EPbexAPRquU4pgDp6wU31AMnTQtjN2QvhKgCRAu5H5DiDfufA X-Developer-Key: i=dimitri.fedrau@liebherr.com; a=ed25519; pk=rT653x09JSQvotxIqQl4/XiI4AOiBZrdOGvxDUbb5m8= X-Endpoint-Received: by B4 Relay for dimitri.fedrau@liebherr.com/20241202 with auth_id=290 X-Original-From: Dimitri Fedrau Reply-To: dimitri.fedrau@liebherr.com X-Patchwork-Delegate: kuba@kernel.org From: Dimitri Fedrau The GPIO2 pin on the DP83822 can be configured as clock output. Add support for configuration via DT. Signed-off-by: Dimitri Fedrau --- drivers/net/phy/dp83822.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index 25ee09c48027c86b7d8f4acb5cbe2e157c56a85a..dc5595eae6cc74e5c77914d53772c5fad64c3e70 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -14,6 +14,8 @@ #include #include +#include + #define DP83822_PHY_ID 0x2000a240 #define DP83825S_PHY_ID 0x2000a140 #define DP83825I_PHY_ID 0x2000a150 @@ -30,6 +32,7 @@ #define MII_DP83822_FCSCR 0x14 #define MII_DP83822_RCSR 0x17 #define MII_DP83822_RESET_CTRL 0x1f +#define MII_DP83822_IOCTRL2 0x463 #define MII_DP83822_GENCFG 0x465 #define MII_DP83822_SOR1 0x467 @@ -104,6 +107,11 @@ #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) +/* IOCTRL2 bits */ +#define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4) +#define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0) +#define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0) + /* SOR1 mode */ #define DP83822_STRAP_MODE1 0 #define DP83822_STRAP_MODE2 BIT(0) @@ -139,6 +147,8 @@ struct dp83822_private { u8 cfg_dac_minus; u8 cfg_dac_plus; struct ethtool_wolinfo wol; + bool set_gpio2_clk_out; + u32 gpio2_clk_out; }; static int dp83822_config_wol(struct phy_device *phydev, @@ -413,6 +423,15 @@ static int dp83822_config_init(struct phy_device *phydev) int err = 0; int bmcr; + if (dp83822->set_gpio2_clk_out) + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2, + DP83822_IOCTRL2_GPIO2_CTRL | + DP83822_IOCTRL2_GPIO2_CLK_SRC, + FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL, + DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) | + FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC, + dp83822->gpio2_clk_out)); + if (phy_interface_is_rgmii(phydev)) { rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, true); @@ -611,6 +630,7 @@ static int dp83822_of_init(struct phy_device *phydev) { struct dp83822_private *dp83822 = phydev->priv; struct device *dev = &phydev->mdio.dev; + int ret; /* Signal detection for the PHY is only enabled if the FX_EN and the * SD_EN pins are strapped. Signal detection can only enabled if FX_EN @@ -623,6 +643,26 @@ static int dp83822_of_init(struct phy_device *phydev) dp83822->fx_enabled = device_property_present(dev, "ti,fiber-mode"); + ret = of_property_read_u32(dev->of_node, "ti,gpio2-clk-out", + &dp83822->gpio2_clk_out); + if (!ret) { + switch (dp83822->gpio2_clk_out) { + case DP83822_CLK_SRC_MAC_IF: + case DP83822_CLK_SRC_XI: + case DP83822_CLK_SRC_INT_REF: + case DP83822_CLK_SRC_RMII_MASTER_MODE_REF: + case DP83822_CLK_SRC_FREE_RUNNING: + case DP83822_CLK_SRC_RECOVERED: + break; + default: + phydev_err(phydev, "ti,gpio2-clk-out value %u not valid\n", + dp83822->gpio2_clk_out); + return -EINVAL; + } + + dp83822->set_gpio2_clk_out = true; + } + return 0; }