From patchwork Wed Dec 11 08:29:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903115 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20A5C1D9591 for ; Wed, 11 Dec 2024 08:30:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905804; cv=none; b=EBGZF5F3O8WBFllbpIa3MWrKg+ZCnZGp5lQWYhkURDUcOcpJv1yR9CrdnywV4yipGEx5M7KmZW95Xv0c33QJZl58i/2NSYEWz9xXYDeFXKKF+5zsmFtEiuQyFt1xhxS3DLfRmG48BByzHUkqcXLblv2TLpp0zPTRaBvz5ErVu2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905804; c=relaxed/simple; bh=uvbHEXTw+a2tX2idu+ViK6cwh2GKBsinSbc9Nbsj/3M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=notv3gSjzEa+z5Fa3LnepRD49hLSSfBJ4AdmsVo/daz23JXh6JjJDM1SrXM0aXW7F68ObLSGgDAjfGee/+5KDqTevx9cYyF1Ss4ZQvIB1rarCEqqUsvZ/b91gNdcQcj+1CQK8XdQ6HP/obxkc707Ek7L9vaTMHi4rRIV7px8U6Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=L2wUZ75f; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="L2wUZ75f" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4361a50e337so7347635e9.0 for ; Wed, 11 Dec 2024 00:30:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905800; x=1734510600; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GT6Ffu6NHkparOWH1yazIoGcxgWe1DmTQ9OnbymmN/0=; b=L2wUZ75fSKZGeEcl1scbNmKjgJQDIJkrMlRsrvz0nHF9SCtxja4l8HMxgy4tHEfUUz ikbcF4ZKIsYYOoecMcXOAOu0eWEpxek3tbEghAJdKeZB/Qptyj5OJ1C3G5og3oJdqLv4 BkmVNz4QSMflERRXqcwemX2waBZ6wxXCIWgmjg+yN13uWHdBMDPGHT0unIu3w1IyH12w HggB2LszdZUIXr8NyYMYfcZ2OYCg6G2Ihf3hvwc94e/q02mSL9NsAQFPtyIkLYx2tnWg meKYXFVMbgpadKRxiBugwdZlJZlXkWfCi9pjkJnSKP+Un5fNjRn1SejNHahM8OH5zOGq dY6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905800; x=1734510600; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GT6Ffu6NHkparOWH1yazIoGcxgWe1DmTQ9OnbymmN/0=; b=QhmGB6WPZN1G1+oLyI3wDyg5zxVGl6PYG00Zgl3MRMi53zmTPf5sJ+CBsHy1Yza/S4 dWwWmatqE9sl1/yi7wRlush5SXk+KXiZHDPMhrg3arhBIbc2U1DWHH7X1mdowLqfJSCT jPJviHQCQi68iySAsN+tT3UZPluhSocgQfXJLEWCOQEfa0WQ+CpgjxOoj0PpNCH+MXBD sA0zJ2VFP5ANKXSB+8z0tZyU6pp3+Y0KSydwtgv/ZT6AJ/rXd3wJNyaOZcShb5Hk0SRe /hR55L0WbrXSvzSWHdhHPF8t12+upgPRQ6pfWwk+lqkJF5jLFucIPFsEIVw/UiE3AXhY b3MQ== X-Gm-Message-State: AOJu0Yzd6ZQzG9i1Vv5ABLDVogdbb/ZbFhiwzGpqIrf3AUUqx49S3T2P 73gt/1csB06714/3aSJCZn1Uvx2PU7ANHmCnkdSGD7zGhc32aYDs97m0WFVU9GQ= X-Gm-Gg: ASbGncvPonkjsitYXYCDkLenoI7C3tMPdFjYT2DUnDZdqBEH1TQsxGpc7/g6n8TcZys qgW7W59DBHFmr+BsMiDNw9XN80jsmKpZvIJ5ZFB+F60xdhR2GGAd3NJhc0zMoT5OGnwGThtTFv3 jpLggJeucGNpHTW4kAkZZ5aU8uw2/SZXyg3PGhxF2fTUf+VFbndJym3MPRt+S0acQGMjmeLt8z1 1faeyVI58Swjk+bQWvVrqopotJYtfLpS2MNr2ssGr+j3zNBh8HCBmJnIgxKbsOy94jPKRZW+rE= X-Google-Smtp-Source: AGHT+IF7oHwnm8rIiEG12aOaCAXXwee4iH7RzxDw44Dh26ZuhO0Z1q9I0gkOLUHLoDLf9lIQrU/4qQ== X-Received: by 2002:a05:600c:1d20:b0:435:9ed3:5688 with SMTP id 5b1f17b1804b1-4361c3d6ac7mr12286655e9.18.1733905800503; Wed, 11 Dec 2024 00:30:00 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:00 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:51 +0100 Subject: [PATCH v5 1/7] drm/msm: adreno: add defines for gpu & gmu frequency table sizes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-1-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1458; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=uvbHEXTw+a2tX2idu+ViK6cwh2GKBsinSbc9Nbsj/3M=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2DzREykEvfRyTTeu2PJL3doUmLN4VZtaUtdXPl KCE67taJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNgwAKCRB33NvayMhJ0YlyD/ 9n1F55iW7tro2Ht/1yZuYHXbYF6L5n48SpHNqIT9F63uycOIBIA9C4UMVOHyQqLuGLrQxLQynDpIxe mpwriIFAbvwCOBf55h5iC0R1iVBnhTDaAHMm9sjNVGV0PB4PFzWtGwSDpfrqMWA40iHE5foCF0P40S biH0o0BEQy7iUbRjL0WRxybwkrQbAsOF1nqPfwpuqEFuWM906zWyZh63dqYLqrP7frbdiqD2oHVxXw Fd7rFTVBt695oaYLAKXvlqkmq71pOi6hxEy92dB0rmCFrr5fd1brrl3hqr0L8MZS3rdA8I646n0Aop eODmDQyX+Mj2aLW2Y26OoJsz4sAspQ1pksIsHc+rMwRL5MB9+9LsyLXHa/IP0eiTq5BAlsxdXvxtII JTlwvcFp04nKV6lGssJhXBFR1BFE1IxQG5PV5ZVJPoZYJMejeyiAT1T/2LNNXjNIBH1fNqUmXrTFpi rD5yzrQRZHF8vWsT70jtPABLg4uUmtvXsHuXkT0VLOLVIIJ8EEs+a3Q2zjcUgZAdtiHIlX1ZcjdQLZ Qfcgp90wnmg2KWS8PvxdI8A1UWEHnmBRiNUjb322vpciOOyKxrKyTJxPoB3y9jN49tkpOuvgY2xoVd LMIiXMhznpNbE3Xr60+5UbPHUnR+358wuB0n+lAOgxyt7MruKoawUvHbRAgQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Even if the code uses ARRAY_SIZE() to fill those tables, it's still a best practice to not use magic values for tables in structs. Suggested-by: Dmitry Baryshkov Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index b4a79f88ccf45cfe651c86d2a9da39541c5772b3..88f18ea6a38a08b5b171709e5020010947a5d347 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -19,6 +19,9 @@ struct a6xx_gmu_bo { u64 iova; }; +#define GMU_MAX_GX_FREQS 16 +#define GMU_MAX_CX_FREQS 4 + /* * These define the different GMU wake up options - these define how both the * CPU and the GMU bring up the hardware @@ -79,12 +82,12 @@ struct a6xx_gmu { int current_perf_index; int nr_gpu_freqs; - unsigned long gpu_freqs[16]; - u32 gx_arc_votes[16]; + unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; + u32 gx_arc_votes[GMU_MAX_GX_FREQS]; int nr_gmu_freqs; - unsigned long gmu_freqs[4]; - u32 cx_arc_votes[4]; + unsigned long gmu_freqs[GMU_MAX_CX_FREQS]; + u32 cx_arc_votes[GMU_MAX_CX_FREQS]; unsigned long freq; From patchwork Wed Dec 11 08:29:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903117 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A7D31DB361 for ; Wed, 11 Dec 2024 08:30:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905805; cv=none; b=YQjHiaL4csb1zgbcHefluLMlsXYx36qJrksx3pslCZaeGM+2QgwSt0gzoIAA2ALwu1+GPsUf7n+fKcy3bESp2ysIJDqIX2htET7DiO32eUpbuJ+PB55JVi6/fbTLYjZUCSsv43lwn/8unbvzrl7lnRlHHbN7H3YbTuxERZM5CJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905805; c=relaxed/simple; bh=5CQHNDz98zwjgzxFxwxhDaL+J5xp8wvGGCM/v4qnlp4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q570qYh1rNkLlsjW6DdEAhT+rdIi5z2fQ7TDjVuMooie0GHrjZGekOnzjsiVQ2nnvGThT4XdHKDsGpRoMd4vDEO9c456TGh5JaEueYPDwzzO7y554fUyoTV9rjqv2MJtba+9kom1cL/VWm/pH6rTSvMXp3AxeKxdvVW7vZFr7eo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=UjL4UrxY; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UjL4UrxY" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-4361c705434so2822155e9.3 for ; Wed, 11 Dec 2024 00:30:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905802; x=1734510602; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TFLBZPihl+blTy7cMJJuq67tqHiNDu0l7ncCwh5bLTM=; b=UjL4UrxYW9BaeGZj80z8gLIJXRSxUH8BlAaRYBJvnMzP4/wtE3r/G4DvqpgXvQTQp3 ijzXuNv1ToFGcR+oImHTDHT2royDIgMNLS6a5CJZ0hgec2XyvhV+IQdGdTG2i3yS5m65 nTRpuBxCYcgpMHbSLQxoc4P+EUCOLLWEciplKF4Ftc2uIwTg/UX/6UcYhEKb1yEp+uUK 6jpiywvUyqJ1H4Grzu2ASIQiUwc2B4sULTmrgrej4kUMA1o+s2ejQZ25TDpdyCKORIjy I7PhbBn1NxqfWj5q+KKiFWvyJF/uTdX5k8bqwk6QVMMWEkrR9402gJCbg03E33N+YThx C8HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905802; x=1734510602; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TFLBZPihl+blTy7cMJJuq67tqHiNDu0l7ncCwh5bLTM=; b=iMa60b6FZ5J09+LyGXH+v4RJRyXGnaCfYKydK903WKzOqcoYquP24mmX5KzpGT8wrQ ujqPBuhEeaUFTeUEuxMJai8YxtdIDUXIl8mSlRdjW9eiB0tm2sa887S7RTwe0cVOJJc8 bAJRT44Qq+cxgNFYLPsmdncJK/kCMHMKmeO1Gym3nxqFhrCBa36cRmHpyGFJqAzOBW5Y Ge6cdpfJbVNhWmEPrn20xCCoQQ4Xa6wZdHd1JKtgjQNTpWTq/ij/SWDGYTG3Lw1XiolK goVsYqpPmKILhSa268kvakCtDXIFJQhKJQlHbUt9z11lj4ift4p01+RuV9f7FFj0Uu1E OSjQ== X-Gm-Message-State: AOJu0YymjaC75cyIges0aEeSSJDJ5lDi8uX/nNRjXmUqrHBZD6gKDneO YEQf+y8Jmo98Q/33yUF4P/WUIMu2tTgJsJ/VFwfgVtZJYBnrwigeieQHiC+Nfmg= X-Gm-Gg: ASbGnctGsBEeZj9aQdzKhXIFK3RwF935QvcH4pGOGGlYQasVfYtkOlJr4f6egh0yKBQ UwJMFtPmdIIDOUJsIk0Q0QGiAoSjdiYibZpHwGIJNp8hFYzFLlEhiVVhYggn9Y/Ca3pZxpMH7Xy OT3uJxcle049ZPEmYeYFJUDnn6aALgUalRoObdTcA3IvRDwxw3HDTzE7E9EwY4WKiZ2ge13q0QR Jq+6wZzYbDMN7Q9UajYixfXWG1+nV8PSbe/I9NDuxlc67w0fVwyZb25cyi8v06R7uk8eOsmHA4= X-Google-Smtp-Source: AGHT+IFrQVS3ZF4RkFzo+v35cjZwBpc/gjOsA2T1oPths/28fR1+Yw+VKhxVNh/VM1JIEwssDxFXhQ== X-Received: by 2002:a05:600c:b86:b0:434:a367:2bd9 with SMTP id 5b1f17b1804b1-4361c376058mr14027255e9.14.1733905801638; Wed, 11 Dec 2024 00:30:01 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:01 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:52 +0100 Subject: [PATCH v5 2/7] drm/msm: adreno: add plumbing to generate bandwidth vote table for GMU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-2-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8926; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=5CQHNDz98zwjgzxFxwxhDaL+J5xp8wvGGCM/v4qnlp4=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2DiMnkrLgdct0amdtuFol1zXjE5Cut3ZaMI8mB qtbahcuJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNgwAKCRB33NvayMhJ0XRaEA CMvkIs8udDLimnoSNTlE7H67AU6hRyEXwzbaPPpD814BjSk49zeghkYFhUZq9inwJRUaF/3f26Y7Lf wnM7Yh1yoO70l9H42NeTbO8/MrljxOnw0ZIICpIyxi32sKaVFP5F5QdrcrCQdEjR3c5WqSaAknabCV rQz2aEiwqbOu5VGa8VnMDDJDlqpjgn05x84K0IXHnbWp5Oy+19Y4ROIvs8Qxuwa0pjmErGC9MnBXBx BffSfxFjQjMK3BiXTp8mcpUwDchnN/qiwvN1MplajbkwEdxH9y1UI+lYXG3FR6kN+HiGaMiIZPZjVN 6Li0JnSbiSQxJiJzNu0ZHjE4DUBQxEv8aj/yWSaKQLgfc/cPztNDo+l06IEVGbxO1lkCMRHfDj0cei tB6Av6wotgObyDbjbNLq3FvZJcQvHEXTOvNUAEuuHVduBEneBn1W9+T6mNcnkBJmyCRkQTDnLvwdki E5vmSQBvSywRxeL8UtWDO7VZXG3ZnNwCz4URR6mrdbRrhlz2ej3jrALZxCzH1uhO5Lp8GNLZLvN5Wc 1dKTKjY0mVUjF+kGNFjeFhai5+nJcpM9EQ8mk26SAaB0PRzGmQwDJBvAFRxAQiQf3SNQ3ugnwxGEsZ QtWyKFi0BjpRqryHMN3O0zFU8eKUfk+L6XBOzao5UW+ec7xcEiBJsfc4pQMQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. While scaling via the interconnect path was sufficient, newer GPUs like the A750 requires specific vote paremeters and bandwidth to achieve full functionality. In order to calculate vote values used by the GPU Management Unit (GMU), we need to parse all the possible OPP Bandwidths and create a vote value to be sent to the appropriate Bus Control Modules (BCMs) declared in the GPU info struct. This vote value is called IB, while on the other side the GMU also takes another vote called AB which is a 16bit quantized value of the floor bandwidth against the maximum supported bandwidth. The AB vote will be calculated later when setting the frequency. The vote array will then be used to dynamically generate the GMU bw_table sent during the GMU power-up. Reviewed-by: Akhil P Oommen Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 144 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 13 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + 3 files changed, 158 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 14db7376c712d19446b38152e480bd5a1e0a5198..36696d372a42a27b26a018b19e73bc6d8a4a5235 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "a6xx_gpu.h" @@ -1287,6 +1288,101 @@ static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) return 0; } +/** + * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager (BCM) + * @unit: divisor used to convert bytes/sec bw value to an RPMh msg + * @width: multiplier used to convert bytes/sec bw value to an RPMh msg + * @vcd: virtual clock domain that this bcm belongs to + * @reserved: reserved field + */ +struct bcm_db { + __le32 unit; + __le16 width; + u8 vcd; + u8 reserved; +}; + +static int a6xx_gmu_rpmh_bw_votes_init(const struct a6xx_info *info, + struct a6xx_gmu *gmu) +{ + const struct bcm_db *bcm_data[GMU_MAX_BCMS] = { 0 }; + unsigned int bcm_index, bw_index, bcm_count = 0; + + if (!info->bcms) + return 0; + + /* Retrieve BCM data from cmd-db */ + for (bcm_index = 0; bcm_index < GMU_MAX_BCMS; bcm_index++) { + size_t count; + + /* Stop at first unconfigured bcm */ + if (!info->bcms[bcm_index].name) + break; + + bcm_data[bcm_index] = cmd_db_read_aux_data( + info->bcms[bcm_index].name, + &count); + if (IS_ERR(bcm_data[bcm_index])) + return PTR_ERR(bcm_data[bcm_index]); + + if (!count) + return -EINVAL; + + ++bcm_count; + } + + /* Generate BCM votes values for each bandwidth & BCM */ + for (bw_index = 0; bw_index < gmu->nr_gpu_bws; bw_index++) { + u32 *data = gmu->gpu_ib_votes[bw_index]; + u32 bw = gmu->gpu_bw_table[bw_index]; + + /* Calculations loosely copied from bcm_aggregate() & tcs_cmd_gen() */ + for (bcm_index = 0; bcm_index < bcm_count; bcm_index++) { + bool commit = false; + u64 peak; + u32 vote; + + /* Skip unconfigured BCM */ + if (!bcm_data[bcm_index]) + continue; + + if (bcm_index == bcm_count - 1 || + (bcm_data[bcm_index + 1] && + bcm_data[bcm_index]->vcd != bcm_data[bcm_index + 1]->vcd)) + commit = true; + + if (!bw) { + data[bcm_index] = BCM_TCS_CMD(commit, false, 0, 0); + continue; + } + + if (info->bcms[bcm_index].fixed) { + u32 perfmode = 0; + + if (bw >= info->bcms[bcm_index].perfmode_bw) + perfmode = info->bcms[bcm_index].perfmode; + + data[bcm_index] = BCM_TCS_CMD(commit, true, 0, perfmode); + continue; + } + + /* Multiply the bandwidth by the width of the connection */ + peak = (u64)bw * le16_to_cpu(bcm_data[bcm_index]->width); + do_div(peak, info->bcms[bcm_index].buswidth); + + /* Input bandwidth value is in KBps, scale the value to BCM unit */ + peak *= 1000ULL; + do_div(peak, le32_to_cpu(bcm_data[bcm_index]->unit)); + + vote = clamp(peak, 1, BCM_TCS_CMD_VOTE_MASK); + + data[bcm_index] = BCM_TCS_CMD(commit, true, vote, vote); + } + } + + return 0; +} + /* Return the 'arc-level' for the given frequency */ static unsigned int a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq) @@ -1390,12 +1486,15 @@ static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes, * The GMU votes with the RPMh for itself and on behalf of the GPU but we need * to construct the list of votes on the CPU and send it over. Query the RPMh * voltage levels and build the votes + * The GMU can also vote for DDR interconnects, use the OPP bandwidth entries + * and BCM parameters to build the votes. */ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; struct msm_gpu *gpu = &adreno_gpu->base; int ret; @@ -1407,6 +1506,10 @@ static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl"); + /* Build the interconnect votes */ + if (info->bcms && gmu->nr_gpu_bws > 1) + ret |= a6xx_gmu_rpmh_bw_votes_init(info, gmu); + return ret; } @@ -1442,10 +1545,43 @@ static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs, return index; } +static int a6xx_gmu_build_bw_table(struct device *dev, unsigned long *bandwidths, + u32 size) +{ + int count = dev_pm_opp_get_opp_count(dev); + struct dev_pm_opp *opp; + int i, index = 0; + unsigned int bandwidth = 1; + + /* + * The OPP table doesn't contain the "off" bandwidth level so we need to + * add 1 to the table size to account for it + */ + + if (WARN(count + 1 > size, + "The GMU bandwidth table is being truncated\n")) + count = size - 1; + + /* Set the "off" bandwidth */ + bandwidths[index++] = 0; + + for (i = 0; i < count; i++) { + opp = dev_pm_opp_find_bw_ceil(dev, &bandwidth, 0); + if (IS_ERR(opp)) + break; + + dev_pm_opp_put(opp); + bandwidths[index++] = bandwidth++; + } + + return index; +} + static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) { struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; struct msm_gpu *gpu = &adreno_gpu->base; int ret = 0; @@ -1472,6 +1608,14 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) gmu->current_perf_index = gmu->nr_gpu_freqs - 1; + /* + * The GMU also handles GPU Interconnect Votes so build a list + * of DDR bandwidths from the GPU OPP table + */ + if (info->bcms) + gmu->nr_gpu_bws = a6xx_gmu_build_bw_table(&gpu->pdev->dev, + gmu->gpu_bw_table, ARRAY_SIZE(gmu->gpu_bw_table)); + /* Build the list of RPMh votes that we'll send to the GMU */ return a6xx_gmu_rpmh_votes_init(gmu); } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 88f18ea6a38a08b5b171709e5020010947a5d347..2062a2be224768c1937d7768f7b8439920e9e127 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -21,6 +21,15 @@ struct a6xx_gmu_bo { #define GMU_MAX_GX_FREQS 16 #define GMU_MAX_CX_FREQS 4 +#define GMU_MAX_BCMS 3 + +struct a6xx_bcm { + char *name; + unsigned int buswidth; + bool fixed; + unsigned int perfmode; + unsigned int perfmode_bw; +}; /* * These define the different GMU wake up options - these define how both the @@ -85,6 +94,10 @@ struct a6xx_gmu { unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; u32 gx_arc_votes[GMU_MAX_GX_FREQS]; + int nr_gpu_bws; + unsigned long gpu_bw_table[GMU_MAX_GX_FREQS]; + u32 gpu_ib_votes[GMU_MAX_GX_FREQS][GMU_MAX_BCMS]; + int nr_gmu_freqs; unsigned long gmu_freqs[GMU_MAX_CX_FREQS]; u32 cx_arc_votes[GMU_MAX_CX_FREQS]; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 4aceffb6aae89c781facc2a6e4a82b20b341b6cb..9201a53dd341bf432923ffb44947e015208a3d02 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -44,6 +44,7 @@ struct a6xx_info { u32 gmu_chipid; u32 gmu_cgc_mode; u32 prim_fifo_threshold; + const struct a6xx_bcm *bcms; }; struct a6xx_gpu { From patchwork Wed Dec 11 08:29:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903118 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CF081D8A0B for ; Wed, 11 Dec 2024 08:30:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905807; cv=none; b=OsQXwbxd3OYtAmPmd/0vhX7Y8869mS4HTHBxTn4ZT/ZstiFgIc/DAG4u1FDgKEIBX3hmS6v6nkzbnVxFjKRxHsw1J4Kd31Sh9Q8v9ZbOZchqg0m7guqNCmnDccTK+GziSxThrvZlEV1dR68lfSTz+yw39OWBOZuroyKGvVWORvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905807; c=relaxed/simple; bh=yovwygK3S8pu26HzluofMUYGeWNAA5KC7l+8jvZOelI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LFtIT2r+sBIvQ871REKm7RmFfsKgl/ONsst6nhVogE1R1UOJOFgQ2GYnEjPi2Y8gFOLEzwDFrIkKdNTZx6RzzaYoSYfPC04tGwcRRLpqbcli4Lvs/mzFiz4HbwiiWUI2MkjEN9TQ00G7xO5/21ylGJpqA9A9PpdLeR5k9pR1ek8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PnWFqNjc; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PnWFqNjc" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-436202dd7f6so1196365e9.0 for ; Wed, 11 Dec 2024 00:30:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905803; x=1734510603; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=lNypXtc4nIg+qb7sUPhcVsJhL4eqdZ8B/Tfk40MaJXk=; b=PnWFqNjcSyAzV+/3Wo5juToy41Wej9C7Hm/xY8G05FeaBMtW8dP3o7/JHG5OFfJEE+ hj83Ld3E30z5IP72dhXG1Lwf5qpesWq7fDurhmTLTgJt26KYbzdaFfdieCFj3sfChM8I 9SbY1MEmx2dJHSbmEQSIev4tpg4uBJObQUN99bIkg2gkxz2mMK+3A0beme4JsYLwdM8O GA+Rse8Ic2oEuZ6OqMOpVe0jStDYpuSaiCxvCNYGO6xbIa8Kbg4uPQmgbqoMHmZvU2jE QQ28CkEFzP74XX1CCW3u9dkJ/Rp7H8gFNAhQfyUdUQN/X8+UbCXEX2Gq6VXJFEj3/n/N Efbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905803; x=1734510603; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lNypXtc4nIg+qb7sUPhcVsJhL4eqdZ8B/Tfk40MaJXk=; b=IGsILe3BY3ih82oMfR+5ZHWaFov8FD9cMkbpqr7pQUzU11OrRSkGTllE6MoTmt2LaP +3pLoOU0pqcrnr2NCYrontSXoe1s9q0LcPLK+rbi188ZuNwz+tNkyYDhumHIcB9oypnx 0n6r3UTkw/63aAsUTaN9imXmafoZgylx2SEuuTAwN7GNeHUQIshqSEsaZg8vjAflNwsR jqDtKtljqJeR/AbdYe6X1X+Ib1eNdY4WBCdNcwU5zZISNy9mR05wxyj+PChcbJV1TRsw jHNh0iv+V2o+JPR+SzxdbRtjP9uAFGk1663pr6DYCOCq+Qj7Tb6sil6dILLXGX7ABLqe RpbQ== X-Gm-Message-State: AOJu0YzRhr+3NhJsT39whY5Vi2/48jewKcjSn70mml3kaKe5MbXYZ6Ix 8285vn6zuICTOXABgOfptR6RZNOFIib3LFiJCnImUURorF4BmrX3gvOfNgnj+5k= X-Gm-Gg: ASbGncsVZCUyjEDNuqobZNf4RNjMt0pO/sGvxr6N2TWbl1SiUQRnXGgO/3/5J7wNacp 8A0MDMX3FnryT2Zp/gsb8c8X8ytUZlo897+y+Tv3rolLI5JNpOKWSmi4dCiou8mpeTaFARQMwAN 7P3VxGUe55j+sCiMmCaYVl9025CN9GoQLqzP5USWXaGowVRd94H6js+LZjC1nde2d8A70ZnU7// W4CRS/T99ILnbdGSIZ/CtkvRYIw1SBO1eACzEDnnvprs28r8zAJXXDQYCJ4JbWjMxlNnuihcvY= X-Google-Smtp-Source: AGHT+IH6+vEX2WfNXNJ2nAc7kKUYdmLrBTuQoYVlYpfObom8aKcXHzrfp+P4XyYInweEJtk1gSrx/w== X-Received: by 2002:a05:600c:c11:b0:434:f7ea:fb44 with SMTP id 5b1f17b1804b1-4361c3acb65mr13968775e9.14.1733905802821; Wed, 11 Dec 2024 00:30:02 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.30.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:02 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:53 +0100 Subject: [PATCH v5 3/7] drm/msm: adreno: dynamically generate GMU bw table Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-3-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3622; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=yovwygK3S8pu26HzluofMUYGeWNAA5KC7l+8jvZOelI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2D/mNj+S561qPZ/Vd9Rzw1cSUKaTGzvfXwgVkA QS3aNyqJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNgwAKCRB33NvayMhJ0agxEA C+A9ezN6FpehfMIejE/kwgdHMeDDhFA6t0KwsN/26Mi/YL0grjbDM5ahRuQ89HQ2nu9RXW/A3s7hkC ABtUbGsL5+ltQ7s+OSVAO8AOcSDEig5sNc6TuUTybS39C31rnVVdJtOCpVak5rw2dFWvBSAGX46fJG HMu4/UprRHYitqxhGOIhnA6O8OOWb/dff3ZbJ879AhsRnt/SSZK99ZrUjALeSBP50RcLgT0ulmm5tm 586MuPgiAWTlol9VL1vovc+4dIz9NMnHywnqSBEme1ZUEUD1fw1JDUPaVlL5CBZ3n4KEIwDpnbPCEd /rNlt30YQ9ZLFxCEwEWIf/1rgMUhAB/V86RIFJX3UaH8jFkGTaXvFSt7vyFLw4gZ0QmRtWcCPghY1K 6UtX59fg1BEBY0CyUMZ0VffC1kriWkCvYp3E9FWkRbMaf7Ij1s/d1/OJ+koJXOHr2ugy36ApYpYY+H B84m2/sFreBaRYe0ZzyiHWyO8NqaLVK2XafTNzQzcgKkArR65IYyjcVr+xKOQb/lr/c4qvgLN/qvX5 wnuLhoapLyKY5Q/hRg9+PHmtcDt8ltdyZBu85AEKsX0QfZIqIClvD5z4c6G/uGhyBSKTPLnuocUeD+ 8g+dTvwRLe6WvTOGmfHKS5hyPOH9Nz9p98KbfvfcFnRBUxOqdhZWuQ71xPUQ== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GPU Management Unit (GMU) can also scale the ddr bandwidth along the frequency and power domain level, but for now we statically fill the bw_table with values from the downstream driver. Only the first entry is used, which is a disable vote, so we currently rely on scaling via the linux interconnect paths. Let's dynamically generate the bw_table with the vote values previously calculated from the OPPs. Those entries will then be used by the GMU when passing the appropriate bandwidth level while voting for a gpu frequency. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 48 ++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index cb8844ed46b29c4569d05eb7a24f7b27e173190f..995526620d678cd05020315f771213e4a6943bec 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -6,6 +6,7 @@ #include #include +#include #include "a6xx_gmu.h" #include "a6xx_gmu.xml.h" @@ -259,6 +260,48 @@ static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu) NULL, 0); } +static void a6xx_generate_bw_table(const struct a6xx_info *info, struct a6xx_gmu *gmu, + struct a6xx_hfi_msg_bw_table *msg) +{ + unsigned int i, j; + + for (i = 0; i < GMU_MAX_BCMS; i++) { + if (!info->bcms[i].name) + break; + msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcms[i].name); + } + msg->ddr_cmds_num = i; + + for (i = 0; i < gmu->nr_gpu_bws; ++i) + for (j = 0; j < msg->ddr_cmds_num; j++) + msg->ddr_cmds_data[i][j] = gmu->gpu_ib_votes[i][j]; + msg->bw_level_num = gmu->nr_gpu_bws; + + /* Compute the wait bitmask with each BCM having the commit bit */ + msg->ddr_wait_bitmask = 0; + for (j = 0; j < msg->ddr_cmds_num; j++) + if (msg->ddr_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) + msg->ddr_wait_bitmask |= BIT(j); + + /* + * These are the CX (CNOC) votes - these are used by the GMU + * The 'CN0' BCM is used on all targets, and votes are basically + * 'off' and 'on' states with first bit to enable the path. + */ + + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); + msg->cnoc_cmds_num = 1; + + msg->cnoc_cmds_data[0][0] = BCM_TCS_CMD(true, false, 0, 0); + msg->cnoc_cmds_data[1][0] = BCM_TCS_CMD(true, true, 0, BIT(0)); + + /* Compute the wait bitmask with each BCM having the commit bit */ + msg->cnoc_wait_bitmask = 0; + for (j = 0; j < msg->cnoc_cmds_num; j++) + if (msg->cnoc_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) + msg->cnoc_wait_bitmask |= BIT(j); +} + static void a618_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 618 GMU doesn't do bus scaling */ @@ -664,6 +707,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) struct a6xx_hfi_msg_bw_table *msg; struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + const struct a6xx_info *info = adreno_gpu->info->a6xx; if (gmu->bw_table) goto send; @@ -672,7 +716,9 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) if (!msg) return -ENOMEM; - if (adreno_is_a618(adreno_gpu)) + if (info->bcms && gmu->nr_gpu_bws > 1) + a6xx_generate_bw_table(info, gmu, msg); + else if (adreno_is_a618(adreno_gpu)) a618_build_bw_table(msg); else if (adreno_is_a619(adreno_gpu)) a619_build_bw_table(msg); From patchwork Wed Dec 11 08:29:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903119 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFF4B1DFD89 for ; Wed, 11 Dec 2024 08:30:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905807; cv=none; b=EclPxpPsGopz9KVv3pGfkRblMU14VAUKUVXUEtPY2oEIbPNZk9pJT9L0lmfARHyroG7FNauDBQhgnv1LWUSuVkHEz6mpUYno390tfZNeA8DZn403PrrYAohSn3AXi/c7darctTCRdQ1GllNc6TvDNQuQK/WV4J07L4Aizw8HOlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905807; c=relaxed/simple; bh=m1NcPOsMY9FCd05ub7OGALb9yrmOmV54oQAtHzEO7ck=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JcQ03As+FoHd++CvJYN2SQKEJGHsluz1FEUJ7dFCAVzBjkkvsbgKu97yRIIgU2BuPF0gX5Rafvij691qDzAWROy9KmVMBHyCUp88/fhyLiMjjj966xiuwoOmVupdnu3/fOEzLnHKJIGt1Rv6Z/UF3ocOGEbPMuQOObcrFcRpc2s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Shnmf0Qs; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Shnmf0Qs" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4361d5dcf5bso4454395e9.3 for ; Wed, 11 Dec 2024 00:30:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905804; x=1734510604; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=U86WDKdPrAsITfGPygHUha71OD7ZxDhxILD/leyKWik=; b=Shnmf0QsD5vjBGRjSIalzziId6RJyn6pkY59ZLG07bxuMTZIKlFCOuYligzG0hKuVb r8KoGeT98BJfgeUFv9OpD+kw1ki49DuguvE6VXcgSPs6rsxw+lzZH3aXQfpxdQJEQDN3 Q0vAmEwX21tDQQJhjrX9HGcq4+QQq6QI+F4xm8KTLimAok/Z8hE7eUcX6+3hIkmi59mj AKcG/NZscJ9eLDriEXU1Mf9LyGZu7+mGW/SFwMLb3mIx3vNyB0ziYcZPCnzYTs92CtYZ ZoBuxfhvyNDP47ZwGcdSi2QJbZusMjpbTed0un0afWV2W6GXNKNbaWsg5bAZWrtxjin0 FIAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905804; x=1734510604; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U86WDKdPrAsITfGPygHUha71OD7ZxDhxILD/leyKWik=; b=QNiLK5flCrcjOJg45TQRuhCF8JE5yRARSCiFYdM5MF9zg6l1F1MR4cqKoZAkMVF61I uvSvPRKOIDPDZ6hWKWXjQXqPPeJ30Z+UGY4sw9cFehIAonwMQf9HnOssiaF564XmGVTs aGbNxkJ5msyLaB2mCu32aQgP7oDMBN6U6k0zxPZYS4z4FXV26wg3iLs5NLCMDo5NN/vw 6HN21nzFUgFnXpu8vwNlx7/hzHEBBGHXBJfJ3HrMi7A3yWriaqpU9BRKN5En4QtMNNqm oe85erBURms5VCLH7NDinasnZOAd6F46agjV6vdFBGhXHNSjnPLtMMwgsK31EpoMGX5B 0gfA== X-Gm-Message-State: AOJu0Yze471Dqp8EC+9l/wpuueAdJEzedzgCOvodT5PGP2OJY/7cgGfO QmECM2lFXNTl3nIyVoYACUUbTxTKLX+SCLxc9MH2kCDjhUQ4ttsFZLpTi6p6d20= X-Gm-Gg: ASbGnctN6ttNVXpQ44EpQQjqaCv86/7mE10RJ3anTULiLH0ONKbhG81KqU0bZlBltgG mAK1m9lfW/M5ul6m3SiytODJOSurEpp9LQuzJJTEXqpDKfsBqpXZQOoKwAJekq+pUYHSwwXU+hy iGQNLzNHDGr/etX3L3AbRRpVZQ3Jn5wbgZ4K4Y9Fe98hh3OeC2WQVSrsOeke5dwCRqgnSWg7ObE O5XTmE3/4DYp1zJMNLkHeuHmFASaTrK1v676YEapaUiGU4mm0bgW3VBbN6bZzmC+NgvXg4ORQQ= X-Google-Smtp-Source: AGHT+IGq09en0HnyDXiGn/DX/au6Q0EcVUymi4G25zrq3RQ0sx1AuF1JJDxDo+5X7J7HeWOENNonBA== X-Received: by 2002:a05:6000:4403:b0:386:3864:5cf2 with SMTP id ffacd0b85a97d-3864ce96b0fmr795384f8f.19.1733905803964; Wed, 11 Dec 2024 00:30:03 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.30.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:03 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:54 +0100 Subject: [PATCH v5 4/7] drm/msm: adreno: find bandwidth index of OPP and set it along freq index Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-4-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5886; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=m1NcPOsMY9FCd05ub7OGALb9yrmOmV54oQAtHzEO7ck=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2Ei90pzqxk6DE5LSfYiHHw+v5iLh0rbkkQUMox R14N192JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNhAAKCRB33NvayMhJ0SASD/ 9Qb/vw3MzeW4uUPJENXlKpxSlje8+9uVBi8LPWqLER1gLjuXvV4l9w9ow8Ck/ay73L9LlhHw/kZ6ie /WHDSBkELDJ5yMSaQyOkH6ulm38ZhUx9Nq2UHYzEIhtRMsmzWWFrboGuWmmZKdlDcG7N9gh2Zjn8st /9mVTXVO0emv38Fd4vigI0Qqk1FSNV7tQ7EWceL4hD9AhS9zZKhNNIBuo4ONyGtvmQyB3JrfrNAvGj 8haeGUqbyO8FmAKXH5x3yQ+1oYzc6LphnGt49wsb1OQRpvBOJX9lYhU5AABENTQf9AZXXuqH81VBCb qjNE/k0uZRxEXy061XNtVhIkMf3JBv4I+hfNfAYKZSdAgahatOKIB7s8H3K8cuQfbHPek8O9Jw24Q9 MEXVAC03+LhMgBemFkQW/9jRBOhQAtgV9w/egVeckCCxAqO9ShdAJeauEPK0P8jfYEMy/4q+OWK41S VQstBDldm4CCrOXe+VNNHwe+YOXvzSQoNNkEz4mq0HW09Lka94fhMZGLNpw8QaAaYhB7d/4rsMqTuM xba+2uy+JcsQt+6ykAF14YpOsG1zrgYlmNvSCJw3thFNnL4LlD/QmfG/MGn7WouvbrXjBsyKrzbaIa SX9J94Ho4hjK99p35B+UnX+5jfhsLA4s14uRF5viLeDgdxUAXOPZzSTLjIxg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The Adreno GPU Management Unit (GMU) can also scale the DDR Bandwidth along the Frequency and Power Domain level, until now we left the OPP core scale the OPP bandwidth via the interconnect path. In order to enable bandwidth voting via the GPU Management Unit (GMU), when an opp is set by devfreq we also look for the corresponding bandwidth index in the previously generated bw_table and pass this value along the frequency index to the GMU. The GMU also takes another vote called AB which is a 16bit quantized value of the floor bandwidth against the maximum supported bandwidth. The AB is calculated with a default 25% of the bandwidth like the downstream implementation too inform the GMU firmware the minimal quantity of bandwidth we require for this OPP. Since we now vote for all resources via the GMU, setting the OPP is no more needed, so we can completely skip calling dev_pm_opp_set_opp() in this situation. Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 39 +++++++++++++++++++++++++++++++++-- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 +- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 6 +++--- drivers/gpu/drm/msm/adreno/a6xx_hfi.h | 5 +++++ 4 files changed, 46 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 36696d372a42a27b26a018b19e73bc6d8a4a5235..46ae0ec7a16a41d55755ce04fb32404cdba087be 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -110,9 +110,11 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, bool suspended) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + const struct a6xx_info *info = adreno_gpu->info->a6xx; struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; u32 perf_index; + u32 bw_index = 0; unsigned long gpu_freq; int ret = 0; @@ -125,6 +127,37 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, if (gpu_freq == gmu->gpu_freqs[perf_index]) break; + /* If enabled, find the corresponding DDR bandwidth index */ + if (info->bcms && gmu->nr_gpu_bws > 1) { + unsigned int bw = dev_pm_opp_get_bw(opp, true, 0); + + for (bw_index = 0; bw_index < gmu->nr_gpu_bws - 1; bw_index++) { + if (bw == gmu->gpu_bw_table[bw_index]) + break; + } + + /* Vote AB as a fraction of the max bandwidth */ + if (bw) { + u64 tmp; + + /* For now, vote for 25% of the bandwidth */ + tmp = bw * 25; + do_div(tmp, 100); + + /* + * The AB vote consists of a 16 bit wide quantized level + * against the maximum supported bandwidth. + * Quantization can be calculated as below: + * vote = (bandwidth * 2^16) / max bandwidth + */ + tmp *= MAX_AB_VOTE; + do_div(tmp, gmu->gpu_bw_table[gmu->nr_gpu_bws - 1]); + + bw_index |= AB_VOTE(clamp(tmp, 1, MAX_AB_VOTE)); + bw_index |= AB_VOTE_ENABLE; + } + } + gmu->current_perf_index = perf_index; gmu->freq = gmu->gpu_freqs[perf_index]; @@ -140,8 +173,10 @@ void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, return; if (!gmu->legacy) { - a6xx_hfi_set_freq(gmu, perf_index); - dev_pm_opp_set_opp(&gpu->pdev->dev, opp); + a6xx_hfi_set_freq(gmu, perf_index, bw_index); + /* With Bandwidth voting, we now vote for all resources, so skip OPP set */ + if (!bw_index) + dev_pm_opp_set_opp(&gpu->pdev->dev, opp); return; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 2062a2be224768c1937d7768f7b8439920e9e127..0c888b326cfb485400118f3601fa5f1949b03374 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -209,7 +209,7 @@ void a6xx_hfi_init(struct a6xx_gmu *gmu); int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state); void a6xx_hfi_stop(struct a6xx_gmu *gmu); int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); -int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index); +int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index); bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index 995526620d678cd05020315f771213e4a6943bec..0989aee3dd2cf9bc3405c3b25a595c22e6f06387 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -772,13 +772,13 @@ static int a6xx_hfi_send_core_fw_start(struct a6xx_gmu *gmu) sizeof(msg), NULL, 0); } -int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, int index) +int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 freq_index, u32 bw_index) { struct a6xx_hfi_gx_bw_perf_vote_cmd msg = { 0 }; msg.ack_type = 1; /* blocking */ - msg.freq = index; - msg.bw = 0; /* TODO: bus scaling */ + msg.freq = freq_index; + msg.bw = bw_index; return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_GX_BW_PERF_VOTE, &msg, sizeof(msg), NULL, 0); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h index 528110169398f69f16443a29a1594d19c36fb595..52ba4a07d7b9a709289acd244a751ace9bdaab5d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.h @@ -173,6 +173,11 @@ struct a6xx_hfi_gx_bw_perf_vote_cmd { u32 bw; }; +#define AB_VOTE_MASK GENMASK(31, 16) +#define MAX_AB_VOTE (FIELD_MAX(AB_VOTE_MASK) - 1) +#define AB_VOTE(vote) FIELD_PREP(AB_VOTE_MASK, (vote)) +#define AB_VOTE_ENABLE BIT(8) + #define HFI_H2F_MSG_PREPARE_SLUMBER 33 struct a6xx_hfi_prep_slumber_cmd { From patchwork Wed Dec 11 08:29:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903120 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E3FC1EC4CA for ; Wed, 11 Dec 2024 08:30:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905810; cv=none; b=L1js6F/XGWdHiSJkc6/FlBWGt5rKo3BXLV2abRQk4AUQq5yX3LIwdIjsKdNOUR4KM57IIqpOO02l4JVpSnsqWeJ8yj0dyPO+SkmgAmUKXHiR8Ey8r5UI7++rQ2zfynfh9L0zPA89c5UmowGp5Ioeo4nDQ8Qf7sYNv0kzQbvqX7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905810; c=relaxed/simple; bh=HwDocDUkhgOfD1IlB5zGqmjPJaEeewUJn9MRE88hfiw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dw1SmTwPs0Okd/w2OsE4FamuH/U4bgAIqCy5HQdQStGf36sfv/M9AdUM0fMoJY2RS3r9hEzMhBEJMyPCP6/rOEUegyea4gmdNEepRwVRVmU4xpF4u/LIfWvO2ZSlR/9YoAIVgRjkn9qrbVxXlTwr9FlqeM98+NNcdxQP00uJBRU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=XjZ1cHdu; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XjZ1cHdu" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-434a742481aso55796255e9.3 for ; Wed, 11 Dec 2024 00:30:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905805; x=1734510605; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=froNOEJ5fP4HPjSwjJSIEMf48laX07a0dnLFUTX+430=; b=XjZ1cHdunkFo/m3dmX/4tvsi/7jVrgUOChdqHWLkXy8HRRmsjezrLRSfltBbOtrczO 7O80aoKBECWW7YXjGSuhde6b9hSbwDYARtR34FrXe4XoWNDZmC5NsoOXCr9R8adOHVmU aoSiriJ8NZ7pnf4wBHYcsLy37TrehyORgePvSgsnzhDYeFbb57EjKZSu+7i2Z79T3T7P xt2vq9fSpUsDsuUVliFvEW5Ptt3pdTFV3kZR60SqskZleohQm9HhdAIhCN1hV9WMfiAN 5b+HczomXKm9KfYwjL9y4qCZMHTpOmtD6vq+rSYcpc8Tlu0Pyz4L6kaOWnRpZqeZPQ9W biqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905805; x=1734510605; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=froNOEJ5fP4HPjSwjJSIEMf48laX07a0dnLFUTX+430=; b=L60/n0NVEsAD/8Z7iGRunlgrrLZHuq3S/x2p0TtTEwKq+nccGbQmG2wCuH1y1JBvcj BMp+bupHMzqZyzUtuD2tsfbKkA0Jfw+I5A1FeXKXgbR/H6u0xGdW6WQzuwm6NkSUXbon 7R2dmkr3qPfRwnQSE2Ox4SFVhDuHf4SZyDmecggcI6AnsukAMOOwa8Ys8mFV11YFiPrW zdjZA86/2WdvBLMy2MOQmVYXVIPz08p+7j/XLNL3k46BaQyFeWjwgpg2DQM5bgkotPfZ Pkh4g99EB2Lx6eR4qfObi/Rm/wnDoS3MayU4VDU1RcFodr9LU6w24sElU/Ov46r/hK9f cy0Q== X-Gm-Message-State: AOJu0YyqIMRE7tSQ7LcmtDJJXTT/JEr1jAb9Q/wRdEPi8n6BdYbc0t0d GyNrkn20HTJ5Fa3ri6CEsiqppzm49vMIT+E05K/QARy2eGzeZRlrex0kku1PtCc= X-Gm-Gg: ASbGnctxsVAvA/GHQq+gMuhZGdelTqFN3/vCGiP+yzkV7eaa1J9L1LDfl8l+/tlqobN f+ZmqTomU1I60AtKNx9wyOnyHVsPVK0d0SlDw8pjnza6m9ObcTUYlcn9VRve4hYL6neME68O3zR OBWKKRkadoMXrJY+JUfGDu/VI1e0Znq5C+FqinhbDOHfjDPksn+7RTzU29iw4Eoeoc4pG5Z0rts wAdJf8Zo140BDCov3WiUYO+s65ctFOx7kiTcfHFgx9WLMjcH6h485mhJJ8/yCYeOUzOSdIlcFs= X-Google-Smtp-Source: AGHT+IGSwDAHYbnw5S2IK3PrmYkN6EG/ZxWl01dgNYJZ1WOshMIaf3xBAqPQQalIgOFUQFPOGjdAnA== X-Received: by 2002:a05:600c:a011:b0:434:e8cf:6390 with SMTP id 5b1f17b1804b1-4361c375be3mr11052565e9.6.1733905805266; Wed, 11 Dec 2024 00:30:05 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:04 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:55 +0100 Subject: [PATCH v5 5/7] drm/msm: adreno: enable GMU bandwidth for A740 and A750 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-5-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1853; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=HwDocDUkhgOfD1IlB5zGqmjPJaEeewUJn9MRE88hfiw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2EHqgkCKVKYrWHVmNIXex/RLBqozejaQeTXpj8 kUBYk4yJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNhAAKCRB33NvayMhJ0T3rD/ 9FVpn1zNY11iw2SqO/QGija56WN3UAmzifwdqisQKqIk3Nftezf9LgNpv6iMwTf/TzFm88pBqVpdOU 2zsK2aL/PuSC52aM8UqN2wRSr+TFXkbdcw+2UiGEr1FU9Lr8EX16nbg5uxHQ0duIAT217kFXDuhuG/ 2CZ5oUAd5JCN3ngw+2CRxWWAheksuFTc82nqs24au/SZCks53k7ZFZv16ibNtmvm0HdOI1P+aecnS7 4S9LDFcdLk5hRdTKB/SNXBsLVtuVt+AFW0rtT5GTP5bEozbzL1pf8/huJWgSlzlvtKFBByOtPi6YJ4 KTGMoCVLINhn08nt3K/9Pw4nDSlVAOqN98nPQPCSEKw0iIPyKCQR456aGCwLs20cAzjIMhC5UXdQrx Rutu3430RFGdvrNwlhW8RxL1HFu5gXnhYhX8h6ggso2u2WfykTgDLrloRw6f+Lhyw1YFn6+INKgcuK sfDmLi1Mln8KgAagtJjvFOC/dv0R806q/t2MRIguFFWL8CZ308dmSAwQIkL+mrVwj97AY1snoDx2yH p60KPgNSCdfUH0QdfFQzVgq9D83JOZBQyXL9Q3eleNc7jmNEGCP2v7VjL/HaOqK+UDiUTGw+Cmmuu/ 5NCrPiIxU/Js8tzXNPlVJbMIzH4RyzPhW3EstmpefIbW7Eqx43GkCabuHvSA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Now all the DDR bandwidth voting via the GPU Management Unit (GMU) is in place, declare the Bus Control Modules (BCMs) and the corresponding parameters in the GPU info struct. Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Signed-off-by: Neil Armstrong --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..edffb7737a97b268bb2986d557969e651988a344 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1388,6 +1388,17 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7020100, .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 4192 * SZ_1K, @@ -1432,6 +1443,17 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7090100, .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(2), + .perfmode_bw = 10687500, + }, + { /* sentinel */ }, + }, }, .address_space_size = SZ_16G, .preempt_record_size = 3572 * SZ_1K, From patchwork Wed Dec 11 08:29:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903121 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47C041DD894 for ; Wed, 11 Dec 2024 08:30:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905810; cv=none; b=GaeK16eXg6pHZiwZekJndgA8TJkjebkVVoB0vo7n0Q/jH/9dgEeaBpLAdr61ZnO2938uq88dt2lbm56hGpeZSu60U6LPLns7yAeP/GvmXW5glqijkuhxHvmHkKZX9p+mAXwZhwCSiHTY9hchIJlv7l9a6OIagFrU68G6N4WD4zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905810; c=relaxed/simple; bh=TRwNAhGHhGveZJg6Jt3v1KhBQ4NlTPzWkB4It076Q5s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lbcsceBQSgYuInC1Bi3bkdSQZE4msht33gJgN+2xD0Nl/mLqyAGRHWy0bi4EjxXzweOY+Qx8nkjJ+r6opmXO2iJiV/ROKYBIEgr0eukY2tl8zFyDbHjLW9kIGTTddoU4JNpd8QIIrI/xvw/jV758NdX+Er/zIrYZGOGqHHJ0Pv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VCReXDdb; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VCReXDdb" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4361815b96cso8553355e9.1 for ; Wed, 11 Dec 2024 00:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905806; x=1734510606; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OJE6jWewYLR4+WwL69RNcPxwF9+nvRISCL65MftveMw=; b=VCReXDdbF3SqguK6S0B7v6xj6K+Vdzst45qON9FIa/DIkfj+7ElJ4GD9oUfyLcI2wl ITXPzEXVbQ+6rYx4C/YdyFh4bV2nGC6P5EjEvYJjmrLYSKVVcm9IKv/tdQy2He+72WZH WCH8lSZkpI0R4lqIMlc6cVzjFSsZ4b9lJPQUX0npBlFnZWLufq3i7Gr5wKseY0WAm2f1 3H5jIOkKP7nEvEsX3UKQP5Xn1nR27F9ADz8YR5kJzmGrQsb1l2e2zIW1RKb5ZvczPiyJ 07OrmWJ9vNVi0+azGB6qteo9VQfvvoYj2U34UGJd1372d58uci5RXVWs12YFWM7CxYtX mqpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905807; x=1734510607; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OJE6jWewYLR4+WwL69RNcPxwF9+nvRISCL65MftveMw=; b=nQmdwvLTFWmOAxrCzyNSKSGdvExVpuvsOmIvQMOZG+vaivhmxx2baojjMcrnr88dGa UHQHnMu4G/AFnPOh1HHyQ7eqnc6fc0BcVtsuocVLbOocTPGhMDccwxu3wGp42gGuxZIO 6IJhQtCaG59HrefT2dGlw0GNlTP0gl0y/SZLSRiUpmplYgqODbi//+KxHqUV98clmiH5 4MJbuz19zmTYGJHF102sAW7jTsjVhW356ROPvxdXJeoESuslfwqVIhHa0HwosctEcfXe 5+zd/50YIebi3RyFlyJTRcjFLai1WW7g3h/hs4E4H1dnY9m6CitOz5bUw07oFml7bfNJ E11Q== X-Gm-Message-State: AOJu0Yz6vDmGbMX1lVwyl9Hg302jmPSv/YN5iW6gUwL/I3JRy/rY9puo J4iJeQus6zMTLyPIJbVWbioukIiDDP+u6fCYdtBlS4ftfHpqyJrtfJ/9YCmRpyw= X-Gm-Gg: ASbGncv0KXuJ5AJxqOe8op4CsXLm5X24kh0/izegLIcMLzvjsFLfRB2ZvvFeocgxR1V pS4zXMYuiOB7E3Vx5O0WW3IxICLU397799BgH5haGdNqcD8ImWkZBCvPoC2/fTKFOkxftb82DJQ +eX5q7CeIaxSN6zVv2feP43DbVDhdcuS+XEHQWs/QcrzLmwtXQmHbaSSO2xzdtfwgpcjgL53DID c57huY3pV8E97q/DlerhSsPf1qZ8rOO60nX4TZmlGEGg7+Vm5FlmaymTnauNUNRuJSUfJSXIhw= X-Google-Smtp-Source: AGHT+IEUW0/j6mo/cphlP6h+I+zkwofgriHLT9wdAyPVKtEJ1u7lzyZIITwTPRB+Ctkzy3cAPNR3Dw== X-Received: by 2002:a05:600c:1907:b0:434:ffd7:6fca with SMTP id 5b1f17b1804b1-4361c34469amr13541845e9.2.1733905806625; Wed, 11 Dec 2024 00:30:06 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:06 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:56 +0100 Subject: [PATCH v5 6/7] arm64: qcom: dts: sm8550: add interconnect and opp-peak-kBps for GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-6-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2617; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=TRwNAhGHhGveZJg6Jt3v1KhBQ4NlTPzWkB4It076Q5s=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2FA2VPuTGXFnwJEd+MglovyCJPCjTRgawXwdkJ c9Lin2+JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNhQAKCRB33NvayMhJ0VIKD/ 0enVnSmdAg9FuxyRRV2ix6HrTWcoGkQNwZVZT1c540JRfipkIEbGsWfGAnBVoUl3tSAkV73jOULxZ+ hdKixrVaHfXVgOW6eAbsO4vW/ebwzI7Ss/ay7OWpxcXEBd+ZwP42sg/QRVpWsWL08e45AJaY0QD6Tm GCBUZ2bZyD01G4EbRlIutPvr4gW0uvJPS6jCTi2h8DATZ0y5+t5KkGp27NR1+WjcZptAQi7speJq6y PgVREfhvLHtw3rqE1HHPLf5/hVRZs6Yx3B4e7xnfvy1Yrlxdm3vbkdGazngKSjT+MsU0zJx95EfrrT 6i7WhiMdynEbxPsPWMXmNnNkyzr5AqMaOH5FrNlsdOQnvxau/+X4hUHBvmTdLw24MGMGeNrm4NnJII /oBwgI/95t+oSfiSEj1V00jVnZlYeFHgV5T3+ahFWTHdcN7NJZv2PYrJDjn+NEeGhJMEVyg8s6fdAw GO9v40k3Ywgb0NM+x9CjiSz/HUIlinU0bGZqC2cb2DUzLuEyWllQKqMI9Ur+J+JQ7tjQcHRF8n7mBY J07are5KHIeFi1wsg275CMIBiyZFvJeuRTU5LLnLDv868G5PiFXfsTUHyGdZrIqPj9/rEkppyDpwRe MSnwjKhCsboqd1tJ1dHG0y9RnG3f9kr7X+whjnrDI6FZVRgLhsbaijQvWO8Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Reviewed-by: Akhil P Oommen Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index e7774d32fb6d2288748ecec00bf525b2b3c40fbb..dedd4a2a58f2c89b6e1b12d955da9ef8734604c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2114,6 +2115,10 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + status = "disabled"; zap-shader { @@ -2127,41 +2132,49 @@ gpu_opp_table: opp-table { opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-peak-kBps = <16500000>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-peak-kBps = <10687500>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-peak-kBps = <2136718>; }; }; }; From patchwork Wed Dec 11 08:29:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 13903122 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 984761EC4DA for ; Wed, 11 Dec 2024 08:30:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905812; cv=none; b=A50FWmbLRuPIDH0ls4+QFwdbnd3vCE745tVZDk8xfiWDBIdYS0d9TWkl7jfWo/sgC9zzCR2uZb28Q/X22RPSCIgW/4XNdvc9Qnp2NkEVEA26MYaLpELdu2zBJKoV32h9S9GAg8NInBuS81R10zEghUkRWf51yLGCfA3k9Bm839A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733905812; c=relaxed/simple; bh=mRmcybJomrA8DtYq9fiyqS6rR7q297sl5lRf/i/VlGk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H2P83dUDXPH97oprmSGzvAkDL3PfDL6QATiaIXFUtlXNN9HpTmkInfI+fecw8gGhKNm1wH5PCOirfgcEIDpoRUiJdEdkOeL7hvOJcpi1kHZKIG74SwQiG8bYxKUwykBVVebXAEkVdbrNC3OiDxPcfsXdKwXkP3CTC72fwP3gW+w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KZjBz81q; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KZjBz81q" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-385e06af753so2824413f8f.2 for ; Wed, 11 Dec 2024 00:30:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1733905808; x=1734510608; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=B4/tn0+NaXoZvCxd7DO6dwQt1/7UILyIFVNQSPfY62g=; b=KZjBz81qSRGscxaLNsENWG7Ltli9uAOo6mf7ux/64spu0JZKi36HixORf06kqPtakp KUWStfMZMCeSlNrj2/1HxGgkXPs6Twcz2UWEMwW16kJJ78n7Qdpvnoeb3qvT/JtHehJ7 QspBoW3MBM3Mr+6l1e8A6HA0nOGHU1Aa9SSBakPXYotPTDoB3b7cb3ocbSEKpOTflT4A 5TnhpsInBaI60sS7QHo3CrtzLfg+lnVLrm6tKgr31ZaJEgUmjoI4Uu0BOdDzRyCJIPHE jt9LrB0mVQRq5aEpf0DscPZ59X66YzxZWEhspZb3bm5Mh1iQ33eACOhu7ELT/bezSHGO HoIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1733905808; x=1734510608; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B4/tn0+NaXoZvCxd7DO6dwQt1/7UILyIFVNQSPfY62g=; b=N7FJ49w29ykaxw2o1FhAizLhwsezauRWaDHsCC6uxEyY57Bl1x3LdydO1dA6nJohuy VAyMkm3cz31ql0K4+62b6RpQxEBmFWWuZc42Q6EqeS7lUNSHZbtmkRX2jyy4sDksdvKK vJ9PpNd8uUUh2IkHHf11MnwNRJXKML2lP44iy7mvYZMaDeJFXEhLTnp8zOTvK+tIIoJK YQOEX4xP6SGhl/+mvaCTdt0wOW5G7M18uCceIDbQq2nbUfRL+azsXDtchhnMgWSTPW0t irUIH1gLPs9KOoW3z6riN0t46DT3KvaLTubiSEtLuvdvCGm27HiAPYWbfd2+nb+DprYM PW7g== X-Gm-Message-State: AOJu0YxrKcAR/YVktmMlfKNCvaLCZYy5axCnfzEE/gSYdXqh2grsLe5+ zQ7phAq4GpCFHwqRrua4cP0a9L9XDOwxNNdHuywQRlWPK6aauA/CY//mpgxwiZU= X-Gm-Gg: ASbGnctF+aciGzyk/sL6IdqVhdnRMc8XDmITIJWcd2SAKq+MwyY4jWB8m0kBCT/fmO3 Q50uLhcdUwE2lCZdqDfsUzyF8h+H7GvRJR54vFhcJX5/x7txOXrxq2UURjx/EFua5ZtAMeH5L3X 1hj0WLjQfSC0pvUDQVHJzPBZfgXNxsXJNS7sc50glCX05VJVT1Iy6dStVUSCSmbqvbOa6ZrZbop 6P1rxOA+7dMUOKseu3avhbVxkOSwCkdP2lsBTB3P+rGAi4TmZKxcRtF++STKc1sQpYICsGEMoI= X-Google-Smtp-Source: AGHT+IFH/NzXNJbgRyEoKdsrxfAQKdSlTl8if4/S8TBRBKiFSopNd9WK8zDKR4VFHgwJ90urpCjVjA== X-Received: by 2002:a05:6000:1a8b:b0:382:30a5:c38e with SMTP id ffacd0b85a97d-3864cea3ea9mr1488908f8f.31.1733905807963; Wed, 11 Dec 2024 00:30:07 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-387824a3e38sm735687f8f.23.2024.12.11.00.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Dec 2024 00:30:07 -0800 (PST) From: Neil Armstrong Date: Wed, 11 Dec 2024 09:29:57 +0100 Subject: [PATCH v5 7/7] arm64: qcom: dts: sm8650: add interconnect and opp-peak-kBps for GPU Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241211-topic-sm8x50-gpu-bw-vote-v5-7-6112f9f785ec@linaro.org> References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> To: Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2681; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=mRmcybJomrA8DtYq9fiyqS6rR7q297sl5lRf/i/VlGk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnWU2FIURdxNJLLaES0fnJrqYO+HzNf4JEpRojHmTZ gBojavyJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ1lNhQAKCRB33NvayMhJ0ZWEEA CaXmuD++16A4jWWDPTEnOk6gHg/IoOGcwhhh5hSIk7V1mQdjU/g5+hVTcDxpB7epXvCSHEei5zO7l8 j151YYqlSesFX58NbskoPn4b5RnO5oTgQojQ+s1fSk+4sy5ma7p7eavT3ScwnkZmmePM9CZcFYixFv maLVtAqSC9HX1UbotSMFXkl49O4YNS3NmD691m3yaqz584LXPApnDnsL7vk9cYucv+wb+cRt32i8aV zkDut4H7bGNPxieMKeSPddgeGrPI2lbeOyF1KEMo9HXRqqNH7W9bryUOcKOyNnU1fIjvWX+WEJ2Pa3 GMjrFD66Z6NYSthpEO6yhvWhBliW9g26Md2JO8QwIG2V4hEKS/afML23yoQM8MezF3johQgLBQ4WFP JuVUVb70eptjRYCC4NMk4Hpe1+sI00FhEtRTv8sLCcS9bqfw5R1fuO/edkzlhIqckvoZEviiJBReJ5 z+OEs9GqX1Gk4p20epT7VQJuL74ywqCBm18WqgMuUnuVR8Zvwbhjc+0mHJR8RJZ8AtUuK7TzPDkzcu PFt1AFR4vtuZW3ap+J76jHpTBf0Ufg8jEP9US4gjrRMNKm/lxk++tJzD/d2pkZnpGFLu8RdGGzjxdV 3Sm0R2CkIrPFb2c0Z8e1L++R/uV3E1BDLcUL54gh3YTqROKG3BiLEK+2ijSw== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Each GPU OPP requires a specific peak DDR bandwidth, let's add those to each OPP and also the related interconnect path. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 25e47505adcb790d09f1d2726386438487255824..c76c0038c35ab048c88be9870b14c3a0b24b4183 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2636,6 +2636,10 @@ gpu: gpu@3d00000 { qcom,gmu = <&gmu>; #cooling-cells = <2>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + status = "disabled"; zap-shader { @@ -2649,56 +2653,67 @@ gpu_opp_table: opp-table { opp-231000000 { opp-hz = /bits/ 64 <231000000>; opp-level = ; + opp-peak-kBps = <2136718>; }; opp-310000000 { opp-hz = /bits/ 64 <310000000>; opp-level = ; + opp-peak-kBps = <2136718>; }; opp-366000000 { opp-hz = /bits/ 64 <366000000>; opp-level = ; + opp-peak-kBps = <6074218>; }; opp-422000000 { opp-hz = /bits/ 64 <422000000>; opp-level = ; + opp-peak-kBps = <8171875>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-level = ; + opp-peak-kBps = <8171875>; }; opp-578000000 { opp-hz = /bits/ 64 <578000000>; opp-level = ; + opp-peak-kBps = <8171875>; }; opp-629000000 { opp-hz = /bits/ 64 <629000000>; opp-level = ; + opp-peak-kBps = <10687500>; }; opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-770000000 { opp-hz = /bits/ 64 <770000000>; opp-level = ; + opp-peak-kBps = <12449218>; }; opp-834000000 { opp-hz = /bits/ 64 <834000000>; opp-level = ; + opp-peak-kBps = <14398437>; }; }; };