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Signed-off-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Elliot Berman Reviewed-by: Vladimir Zapolskiy --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index df7e93a5a4f6..53892bdaaf58 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -48,13 +48,13 @@ #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) -#define CSIPHY_DEFAULT_PARAMS 0 -#define CSIPHY_LANE_ENABLE 1 -#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 -#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3 -#define CSIPHY_DNP_PARAMS 4 -#define CSIPHY_2PH_REGS 5 -#define CSIPHY_3PH_REGS 6 +#define CSIPHY_DEFAULT_PARAMS 0 +#define CSIPHY_LANE_ENABLE 1 +#define CSIPHY_SETTLE_CNT_LOWER_BYTE 2 +#define CSIPHY_SETTLE_CNT_HIGHER_BYTE 3 +#define CSIPHY_DNP_PARAMS 4 +#define CSIPHY_2PH_REGS 5 +#define CSIPHY_3PH_REGS 6 struct csiphy_reg_t { s32 reg_addr; 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Wed, 11 Dec 2024 14:08:47 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:08:40 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 02/16] media: qcom: camss: csiphy-3ph: Remove redundant PHY init sequence control loop Date: Wed, 11 Dec 2024 19:37:24 +0530 Message-ID: <20241211140738.3835588-3-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: nFj1gF9bZxY3xI-sjvvgYt_hDAOByF9I X-Proofpoint-ORIG-GUID: nFj1gF9bZxY3xI-sjvvgYt_hDAOByF9I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 From: Bryan O'Donoghue Adding a new CSIPHY init sequence using downstream as a reference prompted me to look at why we are splitting up the init sequence into chunks. Right now we declare CSI PHY init sequences as an array of five equally sized writes with a hard-coded control loop to iterate through each of the five indexes. One bug in this model is that if you don't have an even number of writes, you can't init the PHY as you wish. In downstream the original code has something of the character phy_init_seq[MAX_LANES][MAX_PARAMS] which in upstream we have translated into phy_init_seq[5][SOME_NUMBER_OF_EQUAL_WRITES]; What the code does is take a pointer to the first index of the r = &phy_init_seq[0][0]; and then literally does write(r, value); r++; The controlling loop that hard-codes '5' in-lieu of MAX_LANES does no special sleep, fabric-coherence sync or even a printk() to justify its existence. Our compilers are optimising all of this away anyway so lets drop. Reduce the array declaration down to one flat aggregate init and let the code just step through. As a happy side-effect we can then also handle odd-number writes as the number of elements in the init sequence will no longer have to be evenly divisible. Signed-off-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Elliot Berman Reviewed-by: Vladimir Zapolskiy --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 554 +++++++++--------- 1 file changed, 261 insertions(+), 293 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 53892bdaaf58..39269ae31709 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -65,287 +65,257 @@ struct csiphy_reg_t { /* GEN2 1.0 2PH */ static const struct -csiphy_reg_t lane_regs_sdm845[5][14] = { - { - {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, +csiphy_reg_t lane_regs_sdm845[] = { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x14, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; /* GEN2 1.1 2PH */ static const struct -csiphy_reg_t lane_regs_sc8280xp[5][14] = { - { - {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, +csiphy_reg_t lane_regs_sc8280xp[] = { + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0764, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x90, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x0E, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, }; /* GEN2 1.2.1 2PH */ static const struct -csiphy_reg_t lane_regs_sm8250[5][20] = { - { - {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, - { - {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - }, +csiphy_reg_t lane_regs_sm8250[] = { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }; static void csiphy_hw_version_read(struct csiphy_device *csiphy, @@ -501,41 +471,39 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u8 settle_cnt) { const struct csiphy_reg_t *r; - int i, l, array_size; + int i, array_size; u32 val; switch (csiphy->camss->res->version) { case CAMSS_845: - r = &lane_regs_sdm845[0][0]; - array_size = ARRAY_SIZE(lane_regs_sdm845[0]); + r = &lane_regs_sdm845[0]; + array_size = ARRAY_SIZE(lane_regs_sdm845); break; case CAMSS_8250: - r = &lane_regs_sm8250[0][0]; - array_size = ARRAY_SIZE(lane_regs_sm8250[0]); + r = &lane_regs_sm8250[0]; + array_size = ARRAY_SIZE(lane_regs_sm8250); break; case CAMSS_8280XP: - r = &lane_regs_sc8280xp[0][0]; - array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]); + r = &lane_regs_sc8280xp[0]; + array_size = ARRAY_SIZE(lane_regs_sc8280xp); break; default: WARN(1, "unknown cspi version\n"); return; } - for (l = 0; l < 5; l++) { - for (i = 0; i < array_size; i++, r++) { - switch (r->csiphy_param_type) { - case CSIPHY_SETTLE_CNT_LOWER_BYTE: - val = settle_cnt & 0xff; - break; - case CSIPHY_DNP_PARAMS: - continue; - default: - val = r->reg_data; - break; - } - writel_relaxed(val, csiphy->base + r->reg_addr); + for (i = 0; i < array_size; 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lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 From: Bryan O'Donoghue The existing structure captures the configuration of CSIPHY lane registers. Rename to struct csiphy_lane_regs to reflect. Signed-off-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Elliot Berman Reviewed-by: Vladimir Zapolskiy --- .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 39269ae31709..bc4834ee2dcc 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -56,7 +56,7 @@ #define CSIPHY_2PH_REGS 5 #define CSIPHY_3PH_REGS 6 -struct csiphy_reg_t { +struct csiphy_lane_regs { s32 reg_addr; s32 reg_data; s32 delay; @@ -65,7 +65,7 @@ struct csiphy_reg_t { /* GEN2 1.0 2PH */ static const struct -csiphy_reg_t lane_regs_sdm845[] = { +csiphy_lane_regs lane_regs_sdm845[] = { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -140,7 +140,7 @@ csiphy_reg_t lane_regs_sdm845[] = { /* GEN2 1.1 2PH */ static const struct -csiphy_reg_t lane_regs_sc8280xp[] = { +csiphy_lane_regs lane_regs_sc8280xp[] = { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -215,7 +215,7 @@ csiphy_reg_t lane_regs_sc8280xp[] = { /* GEN2 1.2.1 2PH */ static const struct -csiphy_reg_t lane_regs_sm8250[] = { +csiphy_lane_regs lane_regs_sm8250[] = { {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -470,7 +470,7 @@ static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy, static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u8 settle_cnt) { - const struct csiphy_reg_t *r; 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Wed, 11 Dec 2024 14:08:55 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:08:48 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 04/16] media: qcom: camss: csiphy: Add an init callback to CSI PHY devices Date: Wed, 11 Dec 2024 19:37:26 +0530 Message-ID: <20241211140738.3835588-5-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: vp1tZXFeOj_n-RiPsXPawLQSfSnsmkKy X-Proofpoint-GUID: vp1tZXFeOj_n-RiPsXPawLQSfSnsmkKy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 From: Bryan O'Donoghue Add a nop init callback to CSIPHY devices, this callback is used to add some HW register offset and register configuration for specific platform, then different platform can reuse the same CSIPHY driver. Later changes will enumerate with enabling code. Signed-off-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Vladimir Zapolskiy --- drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c | 6 ++++++ drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 6 ++++++ drivers/media/platform/qcom/camss/camss-csiphy.c | 4 ++++ drivers/media/platform/qcom/camss/camss-csiphy.h | 1 + 4 files changed, 17 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c index cd4a8c369234..9d67e7fa6366 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c @@ -180,6 +180,11 @@ static irqreturn_t csiphy_isr(int irq, void *dev) return IRQ_HANDLED; } +static int csiphy_init(struct csiphy_device *csiphy) +{ + return 0; +} + const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = { .get_lane_mask = csiphy_get_lane_mask, .hw_version_read = csiphy_hw_version_read, @@ -187,4 +192,5 @@ const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = { .lanes_enable = csiphy_lanes_enable, .lanes_disable = csiphy_lanes_disable, .isr = csiphy_isr, + .init = csiphy_init, }; diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index bc4834ee2dcc..b60c32a195df 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -581,6 +581,11 @@ static void csiphy_lanes_disable(struct csiphy_device *csiphy, CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); } +static int csiphy_init(struct csiphy_device *csiphy) +{ + return 0; +} + const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { .get_lane_mask = csiphy_get_lane_mask, .hw_version_read = csiphy_hw_version_read, @@ -588,4 +593,5 @@ const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { .lanes_enable = csiphy_lanes_enable, .lanes_disable = csiphy_lanes_disable, .isr = csiphy_isr, + .init = csiphy_init, }; diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index 5af2b382a843..35afddf6af5d 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -589,6 +589,10 @@ int msm_csiphy_subdev_init(struct camss *camss, csiphy->cfg.combo_mode = 0; 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Wed, 11 Dec 2024 14:08:59 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBE8wAT030350 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 14:08:58 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:08:52 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 05/16] media: qcom: camss: csiphy-3ph: Move CSIPHY variables to data field inside csiphy struct Date: Wed, 11 Dec 2024 19:37:27 +0530 Message-ID: <20241211140738.3835588-6-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: XF9FIhDtU8JMYKrqAwaqI4EekWpHO7sC X-Proofpoint-ORIG-GUID: XF9FIhDtU8JMYKrqAwaqI4EekWpHO7sC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110101 From: Bryan O'Donoghue A .data field in the csiphy device structure allows us to extend out the register layout of the three phase capable CSIPHY layer. Move the existing lane configuration structure to an encapsulating structure -> struct csiphy_device_regs which is derived from the .data field populated at PHY init time, as opposed to calculated at lane configuration. Signed-off-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Vladimir Zapolskiy --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 49 +++++++++++-------- .../media/platform/qcom/camss/camss-csiphy.h | 6 +++ 2 files changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index b60c32a195df..2b8ff7fd1dd9 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -470,28 +470,10 @@ static void csiphy_gen1_config_lanes(struct csiphy_device *csiphy, static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u8 settle_cnt) { - const struct csiphy_lane_regs *r; - int i, array_size; + const struct csiphy_lane_regs *r = csiphy->regs->lane_regs; + int i, array_size = csiphy->regs->lane_array_size; u32 val; - switch (csiphy->camss->res->version) { - case CAMSS_845: - r = &lane_regs_sdm845[0]; - array_size = ARRAY_SIZE(lane_regs_sdm845); - break; - case CAMSS_8250: - r = &lane_regs_sm8250[0]; - array_size = ARRAY_SIZE(lane_regs_sm8250); - break; - case CAMSS_8280XP: - r = &lane_regs_sc8280xp[0]; - array_size = ARRAY_SIZE(lane_regs_sc8280xp); - break; - default: - WARN(1, "unknown cspi version\n"); - return; - } - for (i = 0; i < array_size; i++, r++) { switch (r->csiphy_param_type) { case CSIPHY_SETTLE_CNT_LOWER_BYTE: @@ -583,6 +565,33 @@ static void csiphy_lanes_disable(struct csiphy_device *csiphy, static int csiphy_init(struct csiphy_device *csiphy) { + struct device *dev = csiphy->camss->dev; + struct csiphy_device_regs *regs; + + regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL); + if (!regs) + return -ENOMEM; + + csiphy->regs = regs; + + switch (csiphy->camss->res->version) { + case CAMSS_845: + regs->lane_regs = &lane_regs_sdm845[0]; + regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845); + break; + case CAMSS_8250: + regs->lane_regs = &lane_regs_sm8250[0]; + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250); + break; + case CAMSS_8280XP: + regs->lane_regs = &lane_regs_sc8280xp[0]; + regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); + break; + default: + WARN(1, "unknown csiphy version\n"); + return -ENODEV; + } + return 0; } diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h index a77bccacb37f..2371507b0a1f 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -79,6 +79,11 @@ struct csiphy_subdev_resources { const struct csiphy_formats *formats; }; +struct csiphy_device_regs { + const struct csiphy_lane_regs *lane_regs; + int lane_array_size; +}; + struct csiphy_device { struct camss *camss; u8 id; @@ -97,6 +102,7 @@ struct csiphy_device { struct csiphy_config cfg; struct v4l2_mbus_framefmt fmt[MSM_CSIPHY_PADS_NUM]; const struct csiphy_subdev_resources *res; + struct csiphy_device_regs *regs; }; struct camss_subdev_resources; From patchwork Wed Dec 11 14:07:28 2024 Content-Type: text/plain; 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Wed, 11 Dec 2024 14:09:02 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:08:56 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 06/16] media: qcom: camss: csiphy-3ph: Use an offset variable to find common control regs Date: Wed, 11 Dec 2024 19:37:28 +0530 Message-ID: <20241211140738.3835588-7-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: SOvcgukn8kAJ7LUZBOwj_xlt2N1PfIzQ X-Proofpoint-ORIG-GUID: SOvcgukn8kAJ7LUZBOwj_xlt2N1PfIzQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 From: Bryan O'Donoghue New versions of the CSIPHY locate the control registers at offset 0x1000 not offset 0x800. Provide a variable to base an offset from for the purposes of redirecting the base offset for the new PHY regs layout. The existing setup bases from 0x800, the new from 0x1000 with some of the 'EXT' registers dropped but the lower-order lane config regs at offset 0x00 and up the same as before. Signed-off-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Vladimir Zapolskiy --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 67 ++++++++++++------- .../media/platform/qcom/camss/camss-csiphy.h | 1 + 2 files changed, 44 insertions(+), 24 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 2b8ff7fd1dd9..e44198686b55 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -42,11 +42,11 @@ #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n)) #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 -#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n) ((offset) + 0x4 * (n)) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n)) #define CSIPHY_DEFAULT_PARAMS 0 #define CSIPHY_LANE_ENABLE 1 @@ -321,19 +321,20 @@ csiphy_lane_regs lane_regs_sm8250[] = { static void csiphy_hw_version_read(struct csiphy_device *csiphy, struct device *dev) { + struct csiphy_device_regs *regs = csiphy->regs; u32 hw_version; - writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, - csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); + writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); hw_version = readl_relaxed(csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12)); hw_version |= readl_relaxed(csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8; + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8; hw_version |= readl_relaxed(csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16; + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16; hw_version |= readl_relaxed(csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24; + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24; dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); } @@ -344,31 +345,39 @@ static void csiphy_hw_version_read(struct csiphy_device *csiphy, */ static void csiphy_reset(struct csiphy_device *csiphy) { - writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); + struct csiphy_device_regs *regs = csiphy->regs; + + writel_relaxed(0x1, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0)); usleep_range(5000, 8000); - writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); + writel_relaxed(0x0, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0)); } static irqreturn_t csiphy_isr(int irq, void *dev) { struct csiphy_device *csiphy = dev; + struct csiphy_device_regs *regs = csiphy->regs; int i; for (i = 0; i < 11; i++) { int c = i + 22; u8 val = readl_relaxed(csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i)); writel_relaxed(val, csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c)); + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c)); } - writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); - writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); + writel_relaxed(0x1, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 10)); + writel_relaxed(0x0, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 10)); - for (i = 22; i < 33; i++) + for (i = 22; i < 33; i++) { writel_relaxed(0x0, csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i)); + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); + } return IRQ_HANDLED; } @@ -522,6 +531,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; + struct csiphy_device_regs *regs = csiphy->regs; u8 settle_cnt; u8 val; int i; @@ -532,16 +542,20 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, for (i = 0; i < c->num_data; i++) val |= BIT(c->data[i].pos * 2); - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); + writel_relaxed(val, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 5)); val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); + writel_relaxed(val, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); val = 0x02; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(7)); + writel_relaxed(val, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 7)); val = 0x00; - writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); + writel_relaxed(val, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 0)); if (csiphy_is_gen2(csiphy->camss->res->version)) csiphy_gen2_config_lanes(csiphy, settle_cnt); @@ -549,18 +563,22 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, csiphy_gen1_config_lanes(csiphy, cfg, settle_cnt); /* IRQ_MASK registers - disable all interrupts */ - for (i = 11; i < 22; i++) - writel_relaxed(0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i)); + for (i = 11; i < 22; i++) { + writel_relaxed(0, csiphy->base + + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, i)); + } } static void csiphy_lanes_disable(struct csiphy_device *csiphy, struct csiphy_config *cfg) { + struct csiphy_device_regs *regs = csiphy->regs; + writel_relaxed(0, csiphy->base + - CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 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Wed, 11 Dec 2024 14:09:07 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBE97SS003876 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 14:09:07 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:00 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 07/16] media: qcom: camss: csid: Move common code into csid core Date: Wed, 11 Dec 2024 19:37:29 +0530 Message-ID: <20241211140738.3835588-8-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gf7NYO2VDpCaTQhZ-Uxli8qpuxeE9ga3 X-Proofpoint-GUID: gf7NYO2VDpCaTQhZ-Uxli8qpuxeE9ga3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 phishscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 The get hw version and src pad code functions can be common code in csid core file, then the csid driver of different hw version can reuse them, rather than adding duplicate code in csid driver for each version. Suggested-by: Bryan O'Donoghue Signed-off-by: Depeng Shao Reviewed-by: Vladimir Zapolskiy --- .../platform/qcom/camss/camss-csid-4-1.c | 19 ----- .../platform/qcom/camss/camss-csid-4-7.c | 42 ---------- .../platform/qcom/camss/camss-csid-gen2.c | 60 --------------- .../media/platform/qcom/camss/camss-csid.c | 77 +++++++++++++++++++ .../media/platform/qcom/camss/camss-csid.h | 21 +++++ 5 files changed, 98 insertions(+), 121 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid-4-1.c b/drivers/media/platform/qcom/camss/camss-csid-4-1.c index c95861420502..6998e1c52895 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-4-1.c +++ b/drivers/media/platform/qcom/camss/camss-csid-4-1.c @@ -17,7 +17,6 @@ #include "camss-csid-gen1.h" #include "camss.h" -#define CAMSS_CSID_HW_VERSION 0x0 #define CAMSS_CSID_CORE_CTRL_0 0x004 #define CAMSS_CSID_CORE_CTRL_1 0x008 #define CAMSS_CSID_RST_CMD 0x00c @@ -139,15 +138,6 @@ static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) return 0; } -static u32 csid_hw_version(struct csid_device *csid) -{ - u32 hw_version = readl_relaxed(csid->base + CAMSS_CSID_HW_VERSION); - - dev_dbg(csid->camss->dev, "CSID HW Version = 0x%08x\n", hw_version); - - return hw_version; -} - static irqreturn_t csid_isr(int irq, void *dev) { struct csid_device *csid = dev; @@ -180,15 +170,6 @@ static int csid_reset(struct csid_device *csid) return 0; } -static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code, - unsigned int match_format_idx, u32 match_code) -{ - if (match_format_idx > 0) - return 0; - - return sink_code; -} - static void csid_subdev_init(struct csid_device *csid) { csid->testgen.modes = csid_testgen_modes; diff --git a/drivers/media/platform/qcom/camss/camss-csid-4-7.c b/drivers/media/platform/qcom/camss/camss-csid-4-7.c index 08578a143688..66054d4872e6 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-4-7.c +++ b/drivers/media/platform/qcom/camss/camss-csid-4-7.c @@ -16,7 +16,6 @@ #include "camss-csid-gen1.h" #include "camss.h" -#define CAMSS_CSID_HW_VERSION 0x0 #define CAMSS_CSID_CORE_CTRL_0 0x004 #define CAMSS_CSID_CORE_CTRL_1 0x008 #define CAMSS_CSID_RST_CMD 0x010 @@ -151,15 +150,6 @@ static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) return 0; } -static u32 csid_hw_version(struct csid_device *csid) -{ - u32 hw_version = readl_relaxed(csid->base + CAMSS_CSID_HW_VERSION); - - dev_dbg(csid->camss->dev, "CSID HW Version = 0x%08x\n", hw_version); - - return hw_version; -} - /* * isr - CSID module interrupt service routine * @irq: Interrupt line @@ -205,38 +195,6 @@ static int csid_reset(struct csid_device *csid) return 0; } -static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code, - unsigned int match_format_idx, u32 match_code) -{ - switch (sink_code) { - case MEDIA_BUS_FMT_SBGGR10_1X10: - { - u32 src_code[] = { - MEDIA_BUS_FMT_SBGGR10_1X10, - MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, - }; - - return csid_find_code(src_code, ARRAY_SIZE(src_code), - match_format_idx, match_code); - } - case MEDIA_BUS_FMT_Y10_1X10: - { - u32 src_code[] = { - MEDIA_BUS_FMT_Y10_1X10, - MEDIA_BUS_FMT_Y10_2X8_PADHI_LE, - }; - - return csid_find_code(src_code, ARRAY_SIZE(src_code), - match_format_idx, match_code); - } - default: - if (match_format_idx > 0) - return 0; - - return sink_code; - } -} - static void csid_subdev_init(struct csid_device *csid) { csid->testgen.modes = csid_testgen_modes; diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c index e1c757933e27..2a1746dcc1c5 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c @@ -22,11 +22,6 @@ * alternate register layout. */ -#define CSID_HW_VERSION 0x0 -#define HW_VERSION_STEPPING 0 -#define HW_VERSION_REVISION 16 -#define HW_VERSION_GENERATION 28 - #define CSID_RST_STROBES 0x10 #define RST_STROBES 0 @@ -351,29 +346,6 @@ static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) return 0; } -/* - * csid_hw_version - CSID hardware version query - * @csid: CSID device - * - * Return HW version or error - */ -static u32 csid_hw_version(struct csid_device *csid) -{ - u32 hw_version; - u32 hw_gen; - u32 hw_rev; - u32 hw_step; - - hw_version = readl_relaxed(csid->base + CSID_HW_VERSION); - hw_gen = (hw_version >> HW_VERSION_GENERATION) & 0xF; - hw_rev = (hw_version >> HW_VERSION_REVISION) & 0xFFF; - hw_step = (hw_version >> HW_VERSION_STEPPING) & 0xFFFF; - dev_dbg(csid->camss->dev, "CSID HW Version = %u.%u.%u\n", - hw_gen, hw_rev, hw_step); - - return hw_version; -} - /* * csid_isr - CSID module interrupt service routine * @irq: Interrupt line @@ -443,38 +415,6 @@ static int csid_reset(struct csid_device *csid) return 0; } -static u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code, - unsigned int match_format_idx, u32 match_code) -{ - switch (sink_code) { - case MEDIA_BUS_FMT_SBGGR10_1X10: - { - u32 src_code[] = { - MEDIA_BUS_FMT_SBGGR10_1X10, - MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, - }; - - return csid_find_code(src_code, ARRAY_SIZE(src_code), - match_format_idx, match_code); - } - case MEDIA_BUS_FMT_Y10_1X10: - { - u32 src_code[] = { - MEDIA_BUS_FMT_Y10_1X10, - MEDIA_BUS_FMT_Y10_2X8_PADHI_LE, - }; - - return csid_find_code(src_code, ARRAY_SIZE(src_code), - match_format_idx, match_code); - } - default: - if (match_format_idx > 0) - return 0; - - return sink_code; - } -} - static void csid_subdev_init(struct csid_device *csid) { csid->testgen.modes = csid_testgen_modes; diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 858db5d4ca75..6cf8e434dc05 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -29,6 +29,11 @@ #define VFE_480_CSID_OFFSET 0x1200 #define VFE_480_LITE_CSID_OFFSET 0x200 +#define CSID_HW_VERSION 0x0 +#define HW_VERSION_STEPPING 0 +#define HW_VERSION_REVISION 16 +#define HW_VERSION_GENERATION 28 + #define MSM_CSID_NAME "msm_csid" const char * const csid_testgen_modes[] = { @@ -590,6 +595,78 @@ static int csid_set_clock_rates(struct csid_device *csid) return 0; } +/* + * csid_hw_version - CSID hardware version query + * @csid: CSID device + * + * Return HW version or error + */ +u32 csid_hw_version(struct csid_device *csid) +{ + u32 hw_version; + u32 hw_gen; + u32 hw_rev; + u32 hw_step; + + hw_version = readl_relaxed(csid->base + CSID_HW_VERSION); + hw_gen = (hw_version >> HW_VERSION_GENERATION) & 0xF; + hw_rev = (hw_version >> HW_VERSION_REVISION) & 0xFFF; + hw_step = (hw_version >> HW_VERSION_STEPPING) & 0xFFFF; + dev_info(csid->camss->dev, "CSID:%d HW Version = %u.%u.%u\n", + csid->id, hw_gen, hw_rev, hw_step); + + return hw_version; +} + +/* + * csid_src_pad_code - Pick an output/src format based on the input/sink format + * @csid: CSID device + * @sink_code: The sink format of the input + * @match_format_idx: Request preferred index, as defined by subdevice csid + * format. Set @match_code to 0 if used. + * @match_code: Request preferred code, set @match_format_idx to 0 if used + * + * Return 0 on failure or src format code otherwise + */ +u32 csid_src_pad_code(struct csid_device *csid, u32 sink_code, + unsigned int match_format_idx, u32 match_code) +{ + if (csid->camss->res->version == CAMSS_8x16) { + if (match_format_idx > 0) + return 0; + + return sink_code; + } + + switch (sink_code) { + case MEDIA_BUS_FMT_SBGGR10_1X10: + { + u32 src_code[] = { + MEDIA_BUS_FMT_SBGGR10_1X10, + MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, + }; + + return csid_find_code(src_code, ARRAY_SIZE(src_code), + match_format_idx, match_code); + } + case MEDIA_BUS_FMT_Y10_1X10: + { + u32 src_code[] = { + MEDIA_BUS_FMT_Y10_1X10, + MEDIA_BUS_FMT_Y10_2X8_PADHI_LE, + }; + + return csid_find_code(src_code, ARRAY_SIZE(src_code), + match_format_idx, match_code); + } + default: + if (match_format_idx > 0) + return 0; + + return sink_code; + } +} + /* * csid_set_power - Power on/off CSID module * @sd: CSID V4L2 subdevice diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 8cdae98e4dca..f52209b96583 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -237,4 +237,25 @@ extern const struct csid_hw_ops csid_ops_gen2; */ bool csid_is_lite(struct csid_device *csid); +/* + * csid_hw_version - CSID hardware version query + * @csid: CSID device + * + * Return HW version or error + */ +u32 csid_hw_version(struct csid_device *csid); + +/* + * csid_src_pad_code - Pick an output/src format based on the input/sink format + * @csid: CSID device + * @sink_code: The sink format of the input + * @match_format_idx: Request preferred index, as defined by subdevice csid + * format. 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Wed, 11 Dec 2024 14:09:11 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:04 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 08/16] media: qcom: camss: vfe: Move common code into vfe core Date: Wed, 11 Dec 2024 19:37:30 +0530 Message-ID: <20241211140738.3835588-9-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2Gqh6O6JGFS_ir3iDgZbnAqi3IOVrYyX X-Proofpoint-GUID: 2Gqh6O6JGFS_ir3iDgZbnAqi3IOVrYyX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 mlxscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 Some v4l2 buffer related logic functions can be moved to vfe core as common code, then the vfe driver of different hw version can reuse them, this also can avoid adding duplicate code for new version supporting. Suggested-by: Bryan O'Donoghue Signed-off-by: Depeng Shao --- .../media/platform/qcom/camss/camss-vfe-17x.c | 112 +------ .../media/platform/qcom/camss/camss-vfe-4-1.c | 9 - .../media/platform/qcom/camss/camss-vfe-4-7.c | 11 - .../media/platform/qcom/camss/camss-vfe-4-8.c | 11 - .../media/platform/qcom/camss/camss-vfe-480.c | 301 +++--------------- drivers/media/platform/qcom/camss/camss-vfe.c | 276 +++++++++++++++- drivers/media/platform/qcom/camss/camss-vfe.h | 57 +++- 7 files changed, 376 insertions(+), 401 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-17x.c b/drivers/media/platform/qcom/camss/camss-vfe-17x.c index 380c99321030..e5ee7e717b3b 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-17x.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-17x.c @@ -14,8 +14,6 @@ #include "camss.h" #include "camss-vfe.h" -#define VFE_HW_VERSION (0x000) - #define VFE_GLOBAL_RESET_CMD (0x018) #define GLOBAL_RESET_CMD_CORE BIT(0) #define GLOBAL_RESET_CMD_CAMIF BIT(1) @@ -176,20 +174,6 @@ #define VFE_BUS_WM_FRAME_INC(n) (0x2258 + (n) * 0x100) #define VFE_BUS_WM_BURST_LIMIT(n) (0x225c + (n) * 0x100) -static u32 vfe_hw_version(struct vfe_device *vfe) -{ - u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); - - u32 gen = (hw_version >> 28) & 0xF; - u32 rev = (hw_version >> 16) & 0xFFF; - u32 step = hw_version & 0xFFFF; - - dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n", - gen, rev, step); - - return hw_version; -} - static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) { u32 bits = readl_relaxed(vfe->base + reg); @@ -438,62 +422,6 @@ static int vfe_get_output(struct vfe_line *line) return -EINVAL; } -static int vfe_enable_output(struct vfe_line *line) -{ - struct vfe_device *vfe = to_vfe(line); - struct vfe_output *output = &line->output; - const struct vfe_hw_ops *ops = vfe->res->hw_ops; - struct media_entity *sensor; - unsigned long flags; - unsigned int frame_skip = 0; - unsigned int i; - - sensor = camss_find_sensor(&line->subdev.entity); - if (sensor) { - struct v4l2_subdev *subdev = media_entity_to_v4l2_subdev(sensor); - - v4l2_subdev_call(subdev, sensor, g_skip_frames, &frame_skip); - /* Max frame skip is 29 frames */ - if (frame_skip > VFE_FRAME_DROP_VAL - 1) - frame_skip = VFE_FRAME_DROP_VAL - 1; - } - - spin_lock_irqsave(&vfe->output_lock, flags); - - ops->reg_update_clear(vfe, line->id); - - if (output->state > VFE_OUTPUT_RESERVED) { - dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", - output->state); - spin_unlock_irqrestore(&vfe->output_lock, flags); - return -EINVAL; - } - - WARN_ON(output->gen2.active_num); - - output->state = VFE_OUTPUT_ON; - - output->sequence = 0; - output->wait_reg_update = 0; - reinit_completion(&output->reg_update); - - vfe_wm_start(vfe, output->wm_idx[0], line); - - for (i = 0; i < 2; i++) { - output->buf[i] = vfe_buf_get_pending(output); - if (!output->buf[i]) - break; - output->gen2.active_num++; - vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - } - - ops->reg_update(vfe, line->id); - - spin_unlock_irqrestore(&vfe->output_lock, flags); - - return 0; -} - /* * vfe_enable - Enable streaming on VFE line * @line: VFE line @@ -518,7 +446,7 @@ static int vfe_enable(struct vfe_line *line) if (ret < 0) goto error_get_output; - ret = vfe_enable_output(line); + ret = vfe_enable_output_v2(line); if (ret < 0) goto error_enable_output; @@ -627,40 +555,6 @@ static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) spin_unlock_irqrestore(&vfe->output_lock, flags); } -/* - * vfe_queue_buffer - Add empty buffer - * @vid: Video device structure - * @buf: Buffer to be enqueued - * - * Add an empty buffer - depending on the current number of buffers it will be - * put in pending buffer queue or directly given to the hardware to be filled. - * - * Return 0 on success or a negative error code otherwise - */ -static int vfe_queue_buffer(struct camss_video *vid, - struct camss_buffer *buf) -{ - struct vfe_line *line = container_of(vid, struct vfe_line, video_out); - struct vfe_device *vfe = to_vfe(line); - struct vfe_output *output; - unsigned long flags; - - output = &line->output; - - spin_lock_irqsave(&vfe->output_lock, flags); - - if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) { - output->buf[output->gen2.active_num++] = buf; - vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line); - } else { - vfe_buf_add_pending(output, buf); - } - - spin_unlock_irqrestore(&vfe->output_lock, flags); - - return 0; -} - static const struct vfe_isr_ops vfe_isr_ops_170 = { .reset_ack = vfe_isr_reset_ack, .halt_ack = vfe_isr_halt_ack, @@ -671,7 +565,7 @@ static const struct vfe_isr_ops vfe_isr_ops_170 = { }; static const struct camss_video_ops vfe_video_ops_170 = { - .queue_buffer = vfe_queue_buffer, + .queue_buffer = vfe_queue_buffer_v2, .flush_buffers = vfe_flush_buffers, }; @@ -695,5 +589,7 @@ const struct vfe_hw_ops vfe_ops_170 = { .vfe_enable = vfe_enable, .vfe_halt = vfe_halt, .violation_read = vfe_violation_read, + .vfe_wm_start = vfe_wm_start, .vfe_wm_stop = vfe_wm_stop, + .vfe_wm_update = vfe_wm_update, }; diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c index 9a9007c3ff33..901677293d97 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-4-1.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-4-1.c @@ -210,15 +210,6 @@ #define MSM_VFE_VFE0_UB_SIZE 1023 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) -static u32 vfe_hw_version(struct vfe_device *vfe) -{ - u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); - - dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version); - - return hw_version; -} - static u16 vfe_get_ub_size(u8 vfe_id) { if (vfe_id == 0) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c index ce0719106bd3..76729607db02 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-4-7.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-4-7.c @@ -18,8 +18,6 @@ #include "camss-vfe-gen1.h" -#define VFE_0_HW_VERSION 0x000 - #define VFE_0_GLOBAL_RESET_CMD 0x018 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) @@ -254,15 +252,6 @@ #define MSM_VFE_VFE1_UB_SIZE 1535 #define MSM_VFE_VFE1_UB_SIZE_RDI (MSM_VFE_VFE1_UB_SIZE / 3) -static u32 vfe_hw_version(struct vfe_device *vfe) -{ - u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); - - dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version); - - return hw_version; -} - static u16 vfe_get_ub_size(u8 vfe_id) { if (vfe_id == 0) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-4-8.c b/drivers/media/platform/qcom/camss/camss-vfe-4-8.c index 6b59c8107a3c..b2f7d855d8dd 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-4-8.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-4-8.c @@ -17,8 +17,6 @@ #include "camss-vfe.h" #include "camss-vfe-gen1.h" -#define VFE_0_HW_VERSION 0x000 - #define VFE_0_GLOBAL_RESET_CMD 0x018 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) @@ -247,15 +245,6 @@ #define MSM_VFE_VFE1_UB_SIZE 1535 #define MSM_VFE_VFE1_UB_SIZE_RDI (MSM_VFE_VFE1_UB_SIZE / 3) -static u32 vfe_hw_version(struct vfe_device *vfe) -{ - u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); - - dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version); - - return hw_version; -} - static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) { u32 bits = readl_relaxed(vfe->base + reg); diff --git a/drivers/media/platform/qcom/camss/camss-vfe-480.c b/drivers/media/platform/qcom/camss/camss-vfe-480.c index dc2735476c82..f8b93541c4ab 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-480.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-480.c @@ -15,8 +15,6 @@ #include "camss.h" #include "camss-vfe.h" -#define VFE_HW_VERSION (0x00) - #define VFE_GLOBAL_RESET_CMD (vfe_is_lite(vfe) ? 0x0c : 0x1c) #define GLOBAL_RESET_HW_AND_REG (vfe_is_lite(vfe) ? BIT(1) : BIT(0)) @@ -92,23 +90,48 @@ static inline int bus_irq_mask_0_comp_done(struct vfe_device *vfe, int n) #define MAX_VFE_OUTPUT_LINES 4 -static u32 vfe_hw_version(struct vfe_device *vfe) +static void vfe_global_reset(struct vfe_device *vfe) +{ + writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); + writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); +} + +static void vfe_enable_irq(struct vfe_device *vfe) { - u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); + int i; + u32 bus_irq_mask = 0; - u32 gen = (hw_version >> 28) & 0xF; - u32 rev = (hw_version >> 16) & 0xFFF; - u32 step = hw_version & 0xFFFF; + if (!vfe->stream_count) + /* enable reset ack IRQ and top BUS status IRQ */ + writel(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, + vfe->base + VFE_IRQ_MASK(0)); - dev_dbg(vfe->camss->dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step); + for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) { + /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */ + if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED || + vfe->line[i].output.state == VFE_OUTPUT_ON) { + bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i) + | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)); + } + } - return hw_version; + writel(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0)); } -static void vfe_global_reset(struct vfe_device *vfe) +static void vfe_disable_irq(struct vfe_device *vfe, u8 wm) { - writel_relaxed(IRQ_MASK_0_RESET_ACK, vfe->base + VFE_IRQ_MASK(0)); - writel_relaxed(GLOBAL_RESET_HW_AND_REG, vfe->base + VFE_GLOBAL_RESET_CMD); + u32 bus_irq_mask; + + bus_irq_mask = readl_relaxed(vfe->base + VFE_BUS_IRQ_MASK(0)); + + bus_irq_mask &= ~(BUS_IRQ_MASK_0_RDI_RUP(vfe, wm)); + bus_irq_mask &= ~(BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(wm))); + + writel(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0)); + + if (!vfe->stream_count) + writel(0, vfe->base + VFE_IRQ_MASK(0)); + } static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) @@ -140,10 +163,14 @@ static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) writel_relaxed(1 << WM_CFG_EN | MODE_MIPI_RAW << WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); + + vfe_enable_irq(vfe); } static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) { + vfe_disable_irq(vfe, wm); + wm = RDI_WM(wm); /* map to actual WM used (from wm=RDI index) */ writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm)); } @@ -167,32 +194,7 @@ static inline void vfe_reg_update_clear(struct vfe_device *vfe, vfe->reg_update &= ~REG_UPDATE_RDI(vfe, line_id); } -static void vfe_enable_irq_common(struct vfe_device *vfe) -{ - /* enable reset ack IRQ and top BUS status IRQ */ - writel_relaxed(IRQ_MASK_0_RESET_ACK | IRQ_MASK_0_BUS_TOP_IRQ, - vfe->base + VFE_IRQ_MASK(0)); -} - -static void vfe_enable_lines_irq(struct vfe_device *vfe) -{ - int i; - u32 bus_irq_mask = 0; - - for (i = 0; i < MAX_VFE_OUTPUT_LINES; i++) { - /* Enable IRQ for newly added lines, but also keep already running lines's IRQ */ - if (vfe->line[i].output.state == VFE_OUTPUT_RESERVED || - vfe->line[i].output.state == VFE_OUTPUT_ON) { - bus_irq_mask |= BUS_IRQ_MASK_0_RDI_RUP(vfe, i) - | BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i)); - } - } - - writel_relaxed(bus_irq_mask, vfe->base + VFE_BUS_IRQ_MASK(0)); -} - static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id); -static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm); /* * vfe_isr - VFE module interrupt handler @@ -226,7 +228,7 @@ static irqreturn_t vfe_isr(int irq, void *dev) vfe_isr_reg_update(vfe, i); if (status & BUS_IRQ_MASK_0_COMP_DONE(vfe, RDI_COMP_GROUP(i))) - vfe_isr_wm_done(vfe, i); + vfe_buf_done(vfe, i); } } @@ -245,132 +247,6 @@ static int vfe_halt(struct vfe_device *vfe) return 0; } -static int vfe_get_output(struct vfe_line *line) -{ - struct vfe_device *vfe = to_vfe(line); - struct vfe_output *output; - unsigned long flags; - - spin_lock_irqsave(&vfe->output_lock, flags); - - output = &line->output; - if (output->state > VFE_OUTPUT_RESERVED) { - dev_err(vfe->camss->dev, "Output is running\n"); - goto error; - } - - output->wm_num = 1; - - /* Correspondence between VFE line number and WM number. - * line 0 -> RDI 0, line 1 -> RDI1, line 2 -> RDI2, line 3 -> PIX/RDI3 - * Note this 1:1 mapping will not work for PIX streams. - */ - output->wm_idx[0] = line->id; - vfe->wm_output_map[line->id] = line->id; - - output->drop_update_idx = 0; - - spin_unlock_irqrestore(&vfe->output_lock, flags); - - return 0; - -error: - spin_unlock_irqrestore(&vfe->output_lock, flags); - output->state = VFE_OUTPUT_OFF; - - return -EINVAL; -} - -static int vfe_enable_output(struct vfe_line *line) -{ - struct vfe_device *vfe = to_vfe(line); - struct vfe_output *output = &line->output; - unsigned long flags; - unsigned int i; - - spin_lock_irqsave(&vfe->output_lock, flags); - - vfe_reg_update_clear(vfe, line->id); - - if (output->state > VFE_OUTPUT_RESERVED) { - dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", - output->state); - spin_unlock_irqrestore(&vfe->output_lock, flags); - return -EINVAL; - } - - WARN_ON(output->gen2.active_num); - - output->state = VFE_OUTPUT_ON; - - output->sequence = 0; - output->wait_reg_update = 0; - reinit_completion(&output->reg_update); - - vfe_wm_start(vfe, output->wm_idx[0], line); - - for (i = 0; i < 2; i++) { - output->buf[i] = vfe_buf_get_pending(output); - if (!output->buf[i]) - break; - output->gen2.active_num++; - vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line); - } - - vfe_reg_update(vfe, line->id); - - spin_unlock_irqrestore(&vfe->output_lock, flags); - - return 0; -} - -/* - * vfe_enable - Enable streaming on VFE line - * @line: VFE line - * - * Return 0 on success or a negative error code otherwise - */ -static int vfe_enable(struct vfe_line *line) -{ - struct vfe_device *vfe = to_vfe(line); - int ret; - - mutex_lock(&vfe->stream_lock); - - if (!vfe->stream_count) - vfe_enable_irq_common(vfe); - - vfe->stream_count++; - - vfe_enable_lines_irq(vfe); - - mutex_unlock(&vfe->stream_lock); - - ret = vfe_get_output(line); - if (ret < 0) - goto error_get_output; - - ret = vfe_enable_output(line); - if (ret < 0) - goto error_enable_output; - - vfe->was_streaming = 1; - - return 0; - -error_enable_output: - vfe_put_output(line); - -error_get_output: - mutex_lock(&vfe->stream_lock); - - vfe->stream_count--; - - mutex_unlock(&vfe->stream_lock); - - return ret; -} - /* * vfe_isr_reg_update - Process reg update interrupt * @vfe: VFE Device @@ -394,97 +270,8 @@ static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) spin_unlock_irqrestore(&vfe->output_lock, flags); } -/* - * vfe_isr_wm_done - Process write master done interrupt - * @vfe: VFE Device - * @wm: Write master id - */ -static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) -{ - struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]]; - struct camss_buffer *ready_buf; - struct vfe_output *output; - unsigned long flags; - u32 index; - u64 ts = ktime_get_ns(); - - spin_lock_irqsave(&vfe->output_lock, flags); - - if (vfe->wm_output_map[wm] == VFE_LINE_NONE) { - dev_err_ratelimited(vfe->camss->dev, - "Received wm done for unmapped index\n"); - goto out_unlock; - } - output = &vfe->line[vfe->wm_output_map[wm]].output; - - ready_buf = output->buf[0]; - if (!ready_buf) { - dev_err_ratelimited(vfe->camss->dev, - "Missing ready buf %d!\n", output->state); - goto out_unlock; - } - - ready_buf->vb.vb2_buf.timestamp = ts; - ready_buf->vb.sequence = output->sequence++; - - index = 0; - output->buf[0] = output->buf[1]; - if (output->buf[0]) - index = 1; - - output->buf[index] = vfe_buf_get_pending(output); - - if (output->buf[index]) - vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line); - else - output->gen2.active_num--; - - spin_unlock_irqrestore(&vfe->output_lock, flags); - - vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); - - return; - -out_unlock: - spin_unlock_irqrestore(&vfe->output_lock, flags); -} - -/* - * vfe_queue_buffer - Add empty buffer - * @vid: Video device structure - * @buf: Buffer to be enqueued - * - * Add an empty buffer - depending on the current number of buffers it will be - * put in pending buffer queue or directly given to the hardware to be filled. - * - * Return 0 on success or a negative error code otherwise - */ -static int vfe_queue_buffer(struct camss_video *vid, - struct camss_buffer *buf) -{ - struct vfe_line *line = container_of(vid, struct vfe_line, video_out); - struct vfe_device *vfe = to_vfe(line); - struct vfe_output *output; - unsigned long flags; - - output = &line->output; - - spin_lock_irqsave(&vfe->output_lock, flags); - - if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) { - output->buf[output->gen2.active_num++] = buf; - vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line); - } else { - vfe_buf_add_pending(output, buf); - } - - spin_unlock_irqrestore(&vfe->output_lock, flags); - - return 0; -} - static const struct camss_video_ops vfe_video_ops_480 = { - .queue_buffer = vfe_queue_buffer, + .queue_buffer = vfe_queue_buffer_v2, .flush_buffers = vfe_flush_buffers, }; @@ -499,9 +286,13 @@ const struct vfe_hw_ops vfe_ops_480 = { .isr = vfe_isr, .pm_domain_off = vfe_pm_domain_off, .pm_domain_on = vfe_pm_domain_on, + .reg_update = vfe_reg_update, + .reg_update_clear = vfe_reg_update_clear, .subdev_init = vfe_subdev_init, .vfe_disable = vfe_disable, - .vfe_enable = vfe_enable, + .vfe_enable = vfe_enable_v2, .vfe_halt = vfe_halt, + .vfe_wm_start = vfe_wm_start, .vfe_wm_stop = vfe_wm_stop, + .vfe_wm_update = vfe_wm_update, }; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 80a62ba11295..58e24a043e81 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -32,6 +32,11 @@ #define SCALER_RATIO_MAX 16 +#define VFE_HW_VERSION 0x0 +#define HW_VERSION_STEPPING 0 +#define HW_VERSION_REVISION 16 +#define HW_VERSION_GENERATION 28 + static const struct camss_format_info formats_rdi_8x16[] = { { MEDIA_BUS_FMT_UYVY8_1X16, 8, V4L2_PIX_FMT_UYVY, 1, PER_PLANE_DATA(0, 1, 1, 1, 1, 16) }, @@ -403,6 +408,265 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, return 0; } +/* + * vfe_hw_version - Process write master done interrupt + * @vfe: VFE Device + * + * Return vfe hw version + */ +u32 vfe_hw_version(struct vfe_device *vfe) +{ + u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION); + + u32 gen = (hw_version >> HW_VERSION_GENERATION) & 0xF; + u32 rev = (hw_version >> HW_VERSION_REVISION) & 0xFFF; + u32 step = (hw_version >> HW_VERSION_STEPPING) & 0xFFFF; + + dev_info(vfe->camss->dev, "VFE:%d HW Version = %u.%u.%u\n", + vfe->id, gen, rev, step); + + return hw_version; +} + +/* + * vfe_buf_done - Process write master done interrupt + * @vfe: VFE Device + * @wm: Write master id + */ +void vfe_buf_done(struct vfe_device *vfe, int wm) +{ + struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]]; + const struct vfe_hw_ops *ops = vfe->res->hw_ops; + struct camss_buffer *ready_buf; + struct vfe_output *output; + unsigned long flags; + u32 index; + u64 ts = ktime_get_ns(); + + spin_lock_irqsave(&vfe->output_lock, flags); + + if (vfe->wm_output_map[wm] == VFE_LINE_NONE) { + dev_err_ratelimited(vfe->camss->dev, + "Received wm done for unmapped index\n"); + goto out_unlock; + } + output = &vfe->line[vfe->wm_output_map[wm]].output; + + ready_buf = output->buf[0]; + if (!ready_buf) { + dev_err_ratelimited(vfe->camss->dev, + "Missing ready buf %d!\n", output->state); + goto out_unlock; + } + + ready_buf->vb.vb2_buf.timestamp = ts; + ready_buf->vb.sequence = output->sequence++; + + index = 0; + output->buf[0] = output->buf[1]; + if (output->buf[0]) + index = 1; + + output->buf[index] = vfe_buf_get_pending(output); + + if (output->buf[index]) { + ops->vfe_wm_update(vfe, output->wm_idx[0], + output->buf[index]->addr[0], + line); + ops->reg_update(vfe, line->id); + } else { + output->gen2.active_num--; + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + return; + +out_unlock: + spin_unlock_irqrestore(&vfe->output_lock, flags); +} + +int vfe_enable_output_v2(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output = &line->output; + const struct vfe_hw_ops *ops = vfe->res->hw_ops; + struct media_entity *sensor; + unsigned long flags; + unsigned int frame_skip = 0; + unsigned int i; + + sensor = camss_find_sensor(&line->subdev.entity); + if (sensor) { + struct v4l2_subdev *subdev = media_entity_to_v4l2_subdev(sensor); + + v4l2_subdev_call(subdev, sensor, g_skip_frames, &frame_skip); + /* Max frame skip is 29 frames */ + if (frame_skip > VFE_FRAME_DROP_VAL - 1) + frame_skip = VFE_FRAME_DROP_VAL - 1; + } + + spin_lock_irqsave(&vfe->output_lock, flags); + + ops->reg_update_clear(vfe, line->id); + + if (output->state > VFE_OUTPUT_RESERVED) { + dev_err(vfe->camss->dev, + "Output is not in reserved state %d\n", + output->state); + spin_unlock_irqrestore(&vfe->output_lock, flags); + return -EINVAL; + } + + WARN_ON(output->gen2.active_num); + + output->state = VFE_OUTPUT_ON; + + output->sequence = 0; + output->wait_reg_update = 0; + reinit_completion(&output->reg_update); + + ops->vfe_wm_start(vfe, output->wm_idx[0], line); + + for (i = 0; i < 2; i++) { + output->buf[i] = vfe_buf_get_pending(output); + if (!output->buf[i]) + break; + output->gen2.active_num++; + ops->vfe_wm_update(vfe, output->wm_idx[0], + output->buf[i]->addr[0], line); + ops->reg_update(vfe, line->id); + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +/* + * vfe_queue_buffer_v2 - Add empty buffer + * @vid: Video device structure + * @buf: Buffer to be enqueued + * + * Add an empty buffer - depending on the current number of buffers it will be + * put in pending buffer queue or directly given to the hardware to be filled. + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_queue_buffer_v2(struct camss_video *vid, + struct camss_buffer *buf) +{ + struct vfe_line *line = container_of(vid, struct vfe_line, video_out); + struct vfe_device *vfe = to_vfe(line); + const struct vfe_hw_ops *ops = vfe->res->hw_ops; + struct vfe_output *output; + unsigned long flags; + + output = &line->output; + + spin_lock_irqsave(&vfe->output_lock, flags); + + if (output->state == VFE_OUTPUT_ON && + output->gen2.active_num < 2) { + output->buf[output->gen2.active_num++] = buf; + ops->vfe_wm_update(vfe, output->wm_idx[0], + buf->addr[0], line); + ops->reg_update(vfe, line->id); + } else { + vfe_buf_add_pending(output, buf); + } + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; +} + +/* + * vfe_enable_v2 - Enable streaming on VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_enable_v2(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + int ret; + + mutex_lock(&vfe->stream_lock); + + vfe->stream_count++; + + mutex_unlock(&vfe->stream_lock); + + ret = vfe_get_output_v2(line); + if (ret < 0) + goto error_get_output; + + ret = vfe_enable_output_v2(line); + if (ret < 0) + goto error_enable_output; + + vfe->was_streaming = 1; + + return 0; + +error_enable_output: + vfe_put_output(line); + +error_get_output: + mutex_lock(&vfe->stream_lock); + + vfe->stream_count--; + + mutex_unlock(&vfe->stream_lock); + + return ret; +} + +/* + * vfe_get_output_v2 - Get vfe output port for corresponding VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_get_output_v2(struct vfe_line *line) +{ + struct vfe_device *vfe = to_vfe(line); + struct vfe_output *output; + unsigned long flags; + + spin_lock_irqsave(&vfe->output_lock, flags); + + output = &line->output; + if (output->state > VFE_OUTPUT_RESERVED) { + dev_err(vfe->camss->dev, "Output is running\n"); + goto error; + } + + output->wm_num = 1; + + /* Correspondence between VFE line number and WM number. + * line 0 -> RDI 0, line 1 -> RDI1, line 2 -> RDI2, line 3 -> PIX/RDI3 + * Note this 1:1 mapping will not work for PIX streams. + */ + output->wm_idx[0] = line->id; + vfe->wm_output_map[line->id] = line->id; + + output->drop_update_idx = 0; + + spin_unlock_irqrestore(&vfe->output_lock, flags); + + return 0; + +error: + spin_unlock_irqrestore(&vfe->output_lock, flags); + output->state = VFE_OUTPUT_OFF; + + return -EINVAL; +} + int vfe_reset(struct vfe_device *vfe) { unsigned long time; @@ -552,18 +816,18 @@ int vfe_disable(struct vfe_line *line) struct vfe_device *vfe = to_vfe(line); int ret; - ret = vfe_disable_output(line); - if (ret) - goto error; - - vfe_put_output(line); - mutex_lock(&vfe->stream_lock); vfe->stream_count--; mutex_unlock(&vfe->stream_lock); + ret = vfe_disable_output(line); + if (ret) + goto error; + + vfe_put_output(line); + error: return ret; } diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index 10e2cc3c0b83..977710d6655e 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -99,7 +99,6 @@ struct vfe_line { struct vfe_device; struct vfe_hw_ops { - void (*enable_irq_common)(struct vfe_device *vfe); void (*global_reset)(struct vfe_device *vfe); u32 (*hw_version)(struct vfe_device *vfe); irqreturn_t (*isr)(int irq, void *dev); @@ -114,7 +113,12 @@ struct vfe_hw_ops { int (*vfe_enable)(struct vfe_line *line); int (*vfe_halt)(struct vfe_device *vfe); void (*violation_read)(struct vfe_device *vfe); + void (*vfe_wm_start)(struct vfe_device *vfe, u8 wm, + struct vfe_line *line); void (*vfe_wm_stop)(struct vfe_device *vfe, u8 wm); + void (*vfe_buf_done)(struct vfe_device *vfe, int port_id); + void (*vfe_wm_update)(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line); }; struct vfe_isr_ops { @@ -252,4 +256,55 @@ void vfe_put(struct vfe_device *vfe); */ bool vfe_is_lite(struct vfe_device *vfe); +/* + * vfe_hw_version - Process write master done interrupt + * @vfe: VFE Device + * + * Return vfe hw version + */ +u32 vfe_hw_version(struct vfe_device *vfe); +/* + * vfe_enable - Enable streaming on VFE line + * @line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_enable_v2(struct vfe_line *line); + +/* + * vfe_buf_done - Process write master done interrupt + * @vfe: VFE Device + * @wm: Write master id + */ +void vfe_buf_done(struct vfe_device *vfe, int wm); + +/* + * vfe_get_output_v2 - Get vfe output line + * line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_get_output_v2(struct vfe_line *line); + +/* + * vfe_enable_output_v2 - Enable vfe output line + * line: VFE line + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_enable_output_v2(struct vfe_line *line); + +/* + * vfe_queue_buffer_v2 - Add empty buffer + * @vid: Video device structure + * @buf: Buffer to be enqueued + * + * Add an empty buffer - depending on the current number of buffers it will be + * put in pending buffer queue or directly given to the hardware to be filled. + * + * Return 0 on success or a negative error code otherwise + */ +int vfe_queue_buffer_v2(struct camss_video *vid, + struct camss_buffer *buf); + #endif /* QC_MSM_CAMSS_VFE_H */ From patchwork Wed Dec 11 14:07:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Depeng Shao X-Patchwork-Id: 13903572 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA83323E6CE; Wed, 11 Dec 2024 14:09:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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Wed, 11 Dec 2024 14:09:15 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBE9FQr015845 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 14:09:15 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:08 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 09/16] media: qcom: camss: Add callback API for RUP update and buf done Date: Wed, 11 Dec 2024 19:37:31 +0530 Message-ID: <20241211140738.3835588-10-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 3-AmXJoNX9ios37QF3KPwRQ4vjAdS8Bk X-Proofpoint-ORIG-GUID: 3-AmXJoNX9ios37QF3KPwRQ4vjAdS8Bk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 The RUP registers and buf done irq are moved from the IFE to CSID register block on recent CAMSS implementations. Add callbacks structure to wrapper the location change with minimum logic disruption. Signed-off-by: Depeng Shao Signed-off-by: Bryan O'Donoghue --- .../media/platform/qcom/camss/camss-csid.h | 9 ++++++++ drivers/media/platform/qcom/camss/camss.c | 22 +++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 3 +++ 3 files changed, 34 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index f52209b96583..1369e7ea7219 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -152,6 +152,14 @@ struct csid_hw_ops { * @csid: CSID device */ void (*subdev_init)(struct csid_device *csid); + + /* + * reg_update - receive message from other sub device + * @csid: CSID device + * @port_id: Port id + * @is_clear: Indicate if it is clearing reg update or setting reg update + */ + void (*reg_update)(struct csid_device *csid, int port_id, bool is_clear); }; struct csid_subdev_resources { @@ -168,6 +176,7 @@ struct csid_device { struct media_pad pads[MSM_CSID_PADS_NUM]; void __iomem *base; u32 irq; + u32 reg_update; char irq_name[30]; struct camss_clock *clock; int nclocks; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 9fb31f4c18ad..e24084ff88de 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2087,6 +2087,28 @@ static int camss_link_entities(struct camss *camss) return 0; } +void camss_reg_update(struct camss *camss, int hw_id, int port_id, bool is_clear) +{ + struct csid_device *csid; + + if (hw_id < camss->res->csid_num) { + csid = &camss->csid[hw_id]; + + csid->res->hw_ops->reg_update(csid, port_id, is_clear); + } +} + +void camss_buf_done(struct camss *camss, int hw_id, int port_id) +{ + struct vfe_device *vfe; + + if (hw_id < camss->res->vfe_num) { + vfe = &camss->vfe[hw_id]; + + vfe->res->hw_ops->vfe_buf_done(vfe, port_id); + } +} + /* * camss_register_entities - Register subdev nodes and create links * @camss: CAMSS device diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 9da7f48f5dd7..6dceff8ce319 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -161,5 +161,8 @@ void camss_pm_domain_off(struct camss *camss, int id); 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Signed-off-by: Depeng Shao Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-vfe.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 58e24a043e81..1c9b6569fbe5 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -404,6 +404,10 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, return sink_code; } break; + default: + WARN(1, "Unsupported HW version: %x\n", + vfe->camss->res->version); + break; } return 0; } From patchwork Wed Dec 11 14:07:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Depeng Shao X-Patchwork-Id: 13903574 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F35D231A3E; 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Wed, 11 Dec 2024 14:09:23 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBE9M1P015925 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 14:09:22 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:16 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 11/16] media: qcom: camss: csid: Add v4l2 ctrl if TPG mode isn't disabled Date: Wed, 11 Dec 2024 19:37:33 +0530 Message-ID: <20241211140738.3835588-12-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: j1FLSqFqhXygwHOv-TOQmxxLetVZqTXI X-Proofpoint-GUID: j1FLSqFqhXygwHOv-TOQmxxLetVZqTXI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 mlxscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 There is no CSID TPG in some modern HW, so the v4l2 ctrl in CSID driver shouldn't be registered. Checking the supported TPG modes to indicate if the TPG HW is existing or not, and only register v4l2 ctrl for CSID only when TPG HW is existing. Signed-off-by: Depeng Shao --- .../media/platform/qcom/camss/camss-csid.c | 60 +++++++++++-------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 6cf8e434dc05..e26a69a454a7 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -760,11 +760,13 @@ static int csid_set_stream(struct v4l2_subdev *sd, int enable) int ret; if (enable) { - ret = v4l2_ctrl_handler_setup(&csid->ctrls); - if (ret < 0) { - dev_err(csid->camss->dev, - "could not sync v4l2 controls: %d\n", ret); - return ret; + if (csid->testgen.nmodes != CSID_PAYLOAD_MODE_DISABLED) { + ret = v4l2_ctrl_handler_setup(&csid->ctrls); + if (ret < 0) { + dev_err(csid->camss->dev, + "could not sync v4l2 controls: %d\n", ret); + return ret; + } } if (!csid->testgen.enabled && @@ -838,7 +840,8 @@ static void csid_try_format(struct csid_device *csid, break; case MSM_CSID_PAD_SRC: - if (csid->testgen_mode->cur.val == 0) { + if (csid->testgen.nmodes == CSID_PAYLOAD_MODE_DISABLED || + csid->testgen_mode->cur.val == 0) { /* Test generator is disabled, */ /* keep pad formats in sync */ u32 code = fmt->code; @@ -888,7 +891,8 @@ static int csid_enum_mbus_code(struct v4l2_subdev *sd, code->code = csid->res->formats->formats[code->index].code; } else { - if (csid->testgen_mode->cur.val == 0) { + if (csid->testgen.nmodes == CSID_PAYLOAD_MODE_DISABLED || + csid->testgen_mode->cur.val == 0) { struct v4l2_mbus_framefmt *sink_fmt; sink_fmt = __csid_get_format(csid, sd_state, @@ -1267,7 +1271,8 @@ static int csid_link_setup(struct media_entity *entity, /* If test generator is enabled */ /* do not allow a link from CSIPHY to CSID */ - if (csid->testgen_mode->cur.val != 0) + if (csid->testgen.nmodes != CSID_PAYLOAD_MODE_DISABLED && + csid->testgen_mode->cur.val != 0) return -EBUSY; sd = media_entity_to_v4l2_subdev(remote->entity); @@ -1360,24 +1365,27 @@ int msm_csid_register_entity(struct csid_device *csid, MSM_CSID_NAME, csid->id); v4l2_set_subdevdata(sd, csid); - ret = v4l2_ctrl_handler_init(&csid->ctrls, 1); - if (ret < 0) { - dev_err(dev, "Failed to init ctrl handler: %d\n", ret); - return ret; - } + if (csid->testgen.nmodes != CSID_PAYLOAD_MODE_DISABLED) { + ret = v4l2_ctrl_handler_init(&csid->ctrls, 1); + if (ret < 0) { + dev_err(dev, "Failed to init ctrl handler: %d\n", ret); + return ret; + } - csid->testgen_mode = v4l2_ctrl_new_std_menu_items(&csid->ctrls, - &csid_ctrl_ops, V4L2_CID_TEST_PATTERN, - csid->testgen.nmodes, 0, 0, - csid->testgen.modes); + csid->testgen_mode = + v4l2_ctrl_new_std_menu_items(&csid->ctrls, + &csid_ctrl_ops, V4L2_CID_TEST_PATTERN, + csid->testgen.nmodes, 0, 0, + csid->testgen.modes); - if (csid->ctrls.error) { - dev_err(dev, "Failed to init ctrl: %d\n", csid->ctrls.error); - ret = csid->ctrls.error; - goto free_ctrl; - } + if (csid->ctrls.error) { + dev_err(dev, "Failed to init ctrl: %d\n", csid->ctrls.error); + ret = csid->ctrls.error; + goto free_ctrl; + } - csid->subdev.ctrl_handler = &csid->ctrls; + csid->subdev.ctrl_handler = &csid->ctrls; + } ret = csid_init_formats(sd, NULL); if (ret < 0) { @@ -1408,7 +1416,8 @@ int msm_csid_register_entity(struct csid_device *csid, media_cleanup: media_entity_cleanup(&sd->entity); free_ctrl: - v4l2_ctrl_handler_free(&csid->ctrls); + if (csid->testgen.nmodes != CSID_PAYLOAD_MODE_DISABLED) + v4l2_ctrl_handler_free(&csid->ctrls); return ret; } @@ -1421,7 +1430,8 @@ void msm_csid_unregister_entity(struct csid_device *csid) { v4l2_device_unregister_subdev(&csid->subdev); media_entity_cleanup(&csid->subdev.entity); - v4l2_ctrl_handler_free(&csid->ctrls); + if (csid->testgen.nmodes != CSID_PAYLOAD_MODE_DISABLED) + v4l2_ctrl_handler_free(&csid->ctrls); } inline bool csid_is_lite(struct csid_device *csid) From patchwork Wed Dec 11 14:07:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Depeng Shao X-Patchwork-Id: 13903575 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3DC5231A3E; Wed, 11 Dec 2024 14:09:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 11 Dec 2024 14:09:27 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBE9R7Q015970 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 14:09:27 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:20 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , , Yongsheng Li Subject: [PATCH 12/16] dt-bindings: media: camss: Add qcom,sm8550-camss binding Date: Wed, 11 Dec 2024 19:37:34 +0530 Message-ID: <20241211140738.3835588-13-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 8SUb6VA-KHptviK32DgNUaOGCNqjhSHu X-Proofpoint-ORIG-GUID: 8SUb6VA-KHptviK32DgNUaOGCNqjhSHu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110102 Add bindings for qcom,sm8550-camss in order to support the camera subsystem for sm8550. Co-developed-by: Yongsheng Li Signed-off-by: Yongsheng Li Signed-off-by: Depeng Shao --- .../bindings/media/qcom,sm8550-camss.yaml | 604 ++++++++++++++++++ 1 file changed, 604 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml new file mode 100644 index 000000000000..c493524a1add --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-camss.yaml @@ -0,0 +1,604 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Camera Subsystem (CAMSS) + +maintainers: + - Depeng Shao + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8550-camss + + reg: + maxItems: 19 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 36 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_ife_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy6 + - const: csiphy6_timer + - const: csiphy7 + - const: csiphy7_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_0_mnoc + - const: icp_mnoc + - const: sf_0_mnoc + + iommus: + maxItems: 1 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI4. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@6: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI6. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@7: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI7. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb7000 { + compatible = "qcom,sm8550-camss"; + + reg = <0 0x0acb7000 0 0xd00>, + <0 0x0acb9000 0 0xd00>, + <0 0x0acbb000 0 0xd00>, + <0 0x0acca000 0 0xa00>, + <0 0x0acce000 0 0xa00>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0acf0000 0 0x2000>, + <0 0x0acf2000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accb000 0 0x1800>, + <0 0x0accf000 0 0x1800>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY6_CLK>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY7_CLK>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_ife_lite", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy6", + "csiphy6_timer", + "csiphy7", + "csiphy7_timer", + "csiphy_rx", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "ahb", + "hf_0_mnoc", + "icp_mnoc", + "sf_0_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csiphy_ep0: endpoint@0 { + reg = <0>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; From patchwork Wed Dec 11 14:07:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Depeng Shao X-Patchwork-Id: 13903576 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate 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(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:24 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , Subject: [PATCH 13/16] media: qcom: camss: Add sm8550 compatible Date: Wed, 11 Dec 2024 19:37:35 +0530 Message-ID: <20241211140738.3835588-14-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LdO0FsCMs1Ldy053iSgNjshW64cfsLnl X-Proofpoint-ORIG-GUID: LdO0FsCMs1Ldy053iSgNjshW64cfsLnl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110101 Add CAMSS_8550 enum, sm8550 compatible and sm8550 camss drvier private data, the private data just include some basic information now, later changes will enumerate with csiphy, csid and vfe resources. Signed-off-by: Depeng Shao Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss.c | 32 +++++++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index e24084ff88de..2f7697540578 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1634,6 +1634,29 @@ static const struct resources_icc icc_res_sc8280xp[] = { }, }; +static const struct resources_icc icc_res_sm8550[] = { + { + .name = "ahb", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "hf_0_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "icp_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, + { + .name = "sf_0_mnoc", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -2644,6 +2667,14 @@ static const struct camss_resources sc8280xp_resources = { .link_entities = camss_link_entities }; +static const struct camss_resources sm8550_resources = { + .version = CAMSS_8550, + .pd_name = "top", + .icc_res = icc_res_sm8550, + .icc_path_num = ARRAY_SIZE(icc_res_sm8550), + .link_entities = camss_link_entities +}; + static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources }, @@ -2652,6 +2683,7 @@ static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, + { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources }, { } }; diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 6dceff8ce319..cf6672baea1c 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -84,6 +84,7 @@ enum camss_version { CAMSS_845, CAMSS_8250, CAMSS_8280XP, + CAMSS_8550, }; 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The PHY can be configured as two phase or three phase in C-PHY or D-PHY mode. This configuration supports two-phase D-PHY mode. Signed-off-by: Depeng Shao Reviewed-by: Bryan O'Donoghue --- .../qcom/camss/camss-csiphy-3ph-1-0.c | 111 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss.c | 109 +++++++++++++++++ 2 files changed, 220 insertions(+) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index e44198686b55..18a3cf0d64bb 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -318,6 +318,111 @@ csiphy_lane_regs lane_regs_sm8250[] = { {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }; +/* GEN2 2.1.2 2PH DPHY mode */ +static const struct +csiphy_lane_regs lane_regs_sm8550[] = { + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0094, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0494, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0894, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x085C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0860, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0864, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C94, 0xD7, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C60, 0xBD, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, +}; + static void csiphy_hw_version_read(struct csiphy_device *csiphy, struct device *dev) { @@ -519,6 +624,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_8550: ret = true; break; } @@ -606,6 +712,11 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs = &lane_regs_sc8280xp[0]; regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp); break; + case CAMSS_8550: + regs->lane_regs = &lane_regs_sm8550[0]; + regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550); + regs->offset = 0x1000; + break; default: WARN(1, "unknown csiphy version\n"); return -ENODEV; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 2f7697540578..75073841156f 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1634,6 +1634,113 @@ static const struct resources_icc icc_res_sc8280xp[] = { }, }; +static const struct camss_subdev_resources csiphy_res_8550[] = { + /* CSIPHY0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy0", "csiphy0_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy1", "csiphy1_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy2", "csiphy2_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy3", "csiphy3_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy4", "csiphy4_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy4" }, + .interrupt = { "csiphy4" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy5", "csiphy5_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy5" }, + .interrupt = { "csiphy5" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY6 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy6", "csiphy6_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy6" }, + .interrupt = { "csiphy6" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + }, + /* CSIPHY7 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + .clock = { "csiphy7", "csiphy7_timer" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000 } }, + .reg = { "csiphy7" }, + .interrupt = { "csiphy7" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sdm845 + } + } +}; + static const struct resources_icc icc_res_sm8550[] = { { .name = "ahb", @@ -2670,8 +2777,10 @@ static const struct camss_resources sc8280xp_resources = { static const struct camss_resources sm8550_resources = { .version = CAMSS_8550, .pd_name = "top", + .csiphy_res = csiphy_res_8550, .icc_res = icc_res_sm8550, .icc_path_num = ARRAY_SIZE(icc_res_sm8550), + .csiphy_num = ARRAY_SIZE(csiphy_res_8550), .link_entities = camss_link_entities }; From patchwork Wed Dec 11 14:07:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Depeng Shao X-Patchwork-Id: 13903578 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D84123A1A1; Wed, 11 Dec 2024 14:09:44 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, , , , , , CC: , , , , , , , Yongsheng Li Subject: [PATCH 15/16] media: qcom: camss: Add CSID 780 support Date: Wed, 11 Dec 2024 19:37:37 +0530 Message-ID: <20241211140738.3835588-16-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gKhk8z7UB_BFZlTmAFQExJ9owS9vCVRz X-Proofpoint-ORIG-GUID: gKhk8z7UB_BFZlTmAFQExJ9owS9vCVRz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110101 The CSID in sm8550 is version 780, it has new register offset and new functionality. The buf done irq, register update and reset are moved to CSID 780. Co-developed-by: Yongsheng Li Signed-off-by: Yongsheng Li Signed-off-by: Depeng Shao Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/Makefile | 1 + .../platform/qcom/camss/camss-csid-780.c | 337 ++++++++++++++++++ .../platform/qcom/camss/camss-csid-780.h | 25 ++ .../media/platform/qcom/camss/camss-csid.h | 1 + drivers/media/platform/qcom/camss/camss.c | 85 +++++ 5 files changed, 449 insertions(+) create mode 100644 drivers/media/platform/qcom/camss/camss-csid-780.c create mode 100644 drivers/media/platform/qcom/camss/camss-csid-780.h diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index e636968a1126..9a723e8712a2 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -7,6 +7,7 @@ qcom-camss-objs += \ camss-csid-4-1.o \ camss-csid-4-7.o \ camss-csid-gen2.o \ + camss-csid-780.o \ camss-csiphy-2ph-1-0.o \ camss-csiphy-3ph-1-0.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-780.c b/drivers/media/platform/qcom/camss/camss-csid-780.c new file mode 100644 index 000000000000..4c720d177731 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-780.c @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) 2024 Qualcomm Technologies, Inc. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-780.h" + +#define CSID_IO_PATH_CFG0(csid) (0x4 * (csid)) +#define OUTPUT_IFE_EN 0x100 +#define INTERNAL_CSID 1 + +#define CSID_RST_CFG 0xC +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +#define CSID_RST_CMD 0x10 +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) + +#define CSID_IRQ_CMD 0x14 +#define IRQ_CMD_CLEAR BIT(0) + +#define CSID_RUP_AUP_CMD 0x18 +#define CSID_RUP_AUP_RDI(rdi) ((BIT(4) | BIT(20)) << (rdi)) + +#define CSID_TOP_IRQ_STATUS 0x7C +#define TOP_IRQ_STATUS_RESET_DONE BIT(0) + +#define CSID_TOP_IRQ_MASK 0x80 +#define CSID_TOP_IRQ_CLEAR 0x84 +#define CSID_TOP_IRQ_SET 0x88 + +#define CSID_CSI2_RX_IRQ_STATUS 0x9C +#define CSID_CSI2_RX_IRQ_MASK 0xA0 +#define CSID_CSI2_RX_IRQ_CLEAR 0xA4 +#define CSID_CSI2_RX_IRQ_SET 0xA8 + +#define CSID_BUF_DONE_IRQ_STATUS 0x8C +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 14) +#define CSID_BUF_DONE_IRQ_MASK 0x90 +#define CSID_BUF_DONE_IRQ_CLEAR 0x94 +#define CSID_BUF_DONE_IRQ_SET 0x98 + +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0xEC + 0x10 * (rdi)) +#define RUP_DONE_IRQ_STATUS BIT(23) + +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0xF4 + 0x10 * (rdi)) +#define CSID_CSI2_RDIN_IRQ_SET(rdi) (0xF8 + 0x10 * (rdi)) + +#define CSID_CSI2_RX_CFG0 0x200 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 + +#define CSID_CSI2_RX_CFG1 0x204 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define CSID_RDI_CFG0(rdi) (0x500 + 0x100 * (rdi)) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_DT_ID 27 +#define RDI_CFG0_EN BIT(31) + +#define CSID_RDI_CTRL(rdi) (0x504 + 0x100 * (rdi)) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) (0x510 + 0x100 * (rdi)) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PIX_STORE BIT(10) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +#define CSID_RDI_IRQ_SUBSAMPLE_PATTERN(rdi) (0x548 + 0x100 * (rdi)) +#define CSID_RDI_IRQ_SUBSAMPLE_PERIOD(rdi) (0x54C + 0x100 * (rdi)) + +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy, int vc) +{ + int val; + + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0_PHY_NUM_SEL; + + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val = CSI2_RX_CFG1_ECC_CORRECTION_EN; + if (vc > 3) + val |= CSI2_RX_CFG1_VC_MODE; + + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val = 0; + + if (enable) + val = RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_wrapper(struct csid_device *csid) +{ + u32 val; + + /* csid lite doesn't need to configure top register */ + if (csid->res->is_lite) + return; + + val = OUTPUT_IFE_EN | INTERNAL_CSID; + writel(val, csid->camss->csid_wrapper_base + CSID_IO_PATH_CFG0(csid->id)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc) +{ + u32 val; + u8 lane_cnt = csid->phy.lane_cnt; + /* Source pads matching RDI channels on hardware. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. */ + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc]; + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt = 4; + + /* + * DT_ID is a two bit bitfield that is concatenated with + * the four least significant bits of the five bit VC + * bitfield to generate an internal CID value. + * + * CSID_RDI_CFG0(vc) + * DT_ID : 28:27 + * VC : 26:22 + * DT : 21:16 + * + * CID : VC 3:0 << 2 | DT_ID 1:0 + */ + u8 dt_id = vc & 0x03; + + val = RDI_CFG0_TIMESTAMP_EN; + val |= RDI_CFG0_TIMESTAMP_STB_SEL; + /* note: for non-RDI path, this should be format->decode_format */ + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |= vc << RDI_CFG0_VC; + val |= format->data_type << RDI_CFG0_DT; + val |= dt_id << RDI_CFG0_DT_ID; + + writel(val, csid->base + CSID_RDI_CFG0(vc)); + + val = RDI_CFG1_PACKING_FORMAT_MIPI; + val |= RDI_CFG1_PIX_STORE; + val |= RDI_CFG1_DROP_H_EN; + val |= RDI_CFG1_DROP_V_EN; + val |= RDI_CFG1_CROP_H_EN; + val |= RDI_CFG1_CROP_V_EN; + + writel(val, csid->base + CSID_RDI_CFG1(vc)); + + val = 0; + writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PERIOD(vc)); + + val = 1; + writel(val, csid->base + CSID_RDI_IRQ_SUBSAMPLE_PATTERN(vc)); + + val = 0; + writel(val, csid->base + CSID_RDI_CTRL(vc)); + + val = readl(csid->base + CSID_RDI_CFG0(vc)); + + if (enable) + val |= RDI_CFG0_EN; + writel(val, csid->base + CSID_RDI_CFG0(vc)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i; + + __csid_configure_wrapper(csid); + + /* Loop through all enabled VCs and configure stream for each */ + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) + if (csid->phy.en_vc & BIT(i)) { + __csid_configure_rdi_stream(csid, enable, i); + __csid_configure_rx(csid, &csid->phy, i); + __csid_ctrl_rdi(csid, enable, i); + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, bool clear) +{ + if (clear) { + csid->reg_update &= ~CSID_RUP_AUP_RDI(port_id); + } else { + csid->reg_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_RUP_AUP_CMD); + } +} + +/* + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid = dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val = readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + reset_done = val & TOP_IRQ_STATUS_RESET_DONE; + + val = readl(csid->base + CSID_CSI2_RX_IRQ_STATUS); + writel(val, csid->base + CSID_CSI2_RX_IRQ_CLEAR); + + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + /* Read and clear IRQ status for each enabled RDI channel */ + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) + if (csid->phy.en_vc & BIT(i)) { + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & RUP_DONE_IRQ_STATUS) + /* clear the reg update bit */ + csid_subdev_reg_update(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) { + /* + * For Titan 780, bus done and RUP IRQ have been moved to + * CSID from VFE. Once CSID received bus done, need notify + * VFE of this event. Trigger VFE to handle bus done process. + */ + camss_buf_done(csid->camss, csid->id, i); + } + } + + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/* + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + writel(1, csid->base + CSID_TOP_IRQ_CLEAR); + writel(1, csid->base + CSID_IRQ_CMD); + writel(1, csid->base + CSID_TOP_IRQ_MASK); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS; i++) + if (csid->phy.en_vc & BIT(i)) { + writel(BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i), + csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(IRQ_CMD_CLEAR, csid->base + CSID_IRQ_CMD); + writel(BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i), + csid->base + CSID_BUF_DONE_IRQ_MASK); + } + + /* preserve registers */ + val = RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val = SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time = wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_780 = { + .configure_stream = csid_configure_stream, + .configure_testgen_pattern = csid_configure_testgen_pattern, + .hw_version = csid_hw_version, + .isr = csid_isr, + .reset = csid_reset, + .src_pad_code = csid_src_pad_code, + .subdev_init = csid_subdev_init, + .reg_update = csid_subdev_reg_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid-780.h b/drivers/media/platform/qcom/camss/camss-csid-780.h new file mode 100644 index 000000000000..a990c66a60ff --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-780.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * camss-csid-780.h + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module Generation 3 + * + * Copyright (c) 2024 Qualcomm Technologies, Inc. + */ +#ifndef __QC_MSM_CAMSS_CSID_780_H__ +#define __QC_MSM_CAMSS_CSID_780_H__ + +#define DECODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 +#define DECODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 +#define DECODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 +#define DECODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 +#define DECODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 +#define DECODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 +#define DECODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 +#define DECODE_FORMAT_PAYLOAD_ONLY 0xf + +#define PLAIN_FORMAT_PLAIN8 0x0 /* supports DPCM, UNCOMPRESSED_6/8_BIT */ +#define PLAIN_FORMAT_PLAIN16 0x1 /* supports DPCM, UNCOMPRESSED_10/16_BIT */ +#define PLAIN_FORMAT_PLAIN32 0x2 /* supports UNCOMPRESSED_20_BIT */ + +#endif /* __QC_MSM_CAMSS_CSID_780_H__ */ diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 1369e7ea7219..4776166f3d8f 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -237,6 +237,7 @@ extern const struct csid_formats csid_formats_gen2; extern const struct csid_hw_ops csid_ops_4_1; extern const struct csid_hw_ops csid_ops_4_7; extern const struct csid_hw_ops csid_ops_gen2; +extern const struct csid_hw_ops csid_ops_780; /* * csid_is_lite - Check if CSID is CSID lite. diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 75073841156f..c0e336f3916b 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1741,6 +1741,88 @@ static const struct camss_subdev_resources csiphy_res_8550[] = { } }; +static const struct resources_wrapper csid_wrapper_res_sm8550 = { + .reg = "csid_wrapper", +}; + +static const struct camss_subdev_resources csid_res_8550[] = { + /* CSID0 */ + { + .regulators = {}, + .clock = { "csid", "csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_780, + .formats = &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators = {}, + .clock = { "csid", "csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_780, + .formats = &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators = {}, + .clock = { "csid", "csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_780, + .formats = &csid_formats_gen2 + } + }, + /* CSID3 */ + { + .regulators = {}, + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite0" }, + .interrupt = { "csid_lite0" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_780, + .formats = &csid_formats_gen2 + } + }, + /* CSID4 */ + { + .regulators = {}, + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite1" }, + .interrupt = { "csid_lite1" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_780, + .formats = &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_sm8550[] = { { .name = "ahb", @@ -2778,9 +2860,12 @@ static const struct camss_resources sm8550_resources = { .version = CAMSS_8550, .pd_name = "top", .csiphy_res = csiphy_res_8550, + .csid_res = csid_res_8550, + .csid_wrapper_res = &csid_wrapper_res_sm8550, .icc_res = icc_res_sm8550, .icc_path_num = ARRAY_SIZE(icc_res_sm8550), .csiphy_num = ARRAY_SIZE(csiphy_res_8550), + .csid_num = ARRAY_SIZE(csid_res_8550), .link_entities = camss_link_entities }; From patchwork Wed Dec 11 14:07:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Depeng Shao X-Patchwork-Id: 13903579 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84780246325; Wed, 11 Dec 2024 14:09:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 11 Dec 2024 14:09:43 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBE9hsJ019678 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 14:09:43 GMT Received: from hu-depengs-sha.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 06:09:36 -0800 From: Depeng Shao To: , , , , , , , CC: , , , , , , , Yongsheng Li Subject: [PATCH 16/16] media: qcom: camss: Add support for VFE 780 Date: Wed, 11 Dec 2024 19:37:38 +0530 Message-ID: <20241211140738.3835588-17-quic_depengs@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241211140738.3835588-1-quic_depengs@quicinc.com> References: <20241211140738.3835588-1-quic_depengs@quicinc.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6iDjbql2Cif2KryPwqt4JSk9S5pTdbRy X-Proofpoint-ORIG-GUID: 6iDjbql2Cif2KryPwqt4JSk9S5pTdbRy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110101 Add support for VFE found on SM8550 (Titan 780). This implementation is based on the titan 480 implementation. It supports the normal and lite VFE. Co-developed-by: Yongsheng Li Signed-off-by: Yongsheng Li Signed-off-by: Depeng Shao Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-vfe-780.c | 159 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss-vfe.h | 1 + drivers/media/platform/qcom/camss/camss.c | 121 +++++++++++++ 5 files changed, 284 insertions(+) create mode 100644 drivers/media/platform/qcom/camss/camss-vfe-780.c diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 9a723e8712a2..f6db5b3b5ace 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -17,6 +17,7 @@ qcom-camss-objs += \ camss-vfe-4-8.o \ camss-vfe-17x.o \ camss-vfe-480.o \ + camss-vfe-780.o \ camss-vfe-gen1.o \ camss-vfe.o \ camss-video.o \ diff --git a/drivers/media/platform/qcom/camss/camss-vfe-780.c b/drivers/media/platform/qcom/camss/camss-vfe-780.c new file mode 100644 index 000000000000..b9812d70f91b --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-vfe-780.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v780 (SM8550) + * + * Copyright (c) 2024 Qualcomm Technologies, Inc. + */ + +#include +#include +#include + +#include "camss.h" +#include "camss-vfe.h" + +#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x200 : 0xC00) + +#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08) +#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF) + +#define VFE_BUS_WM_TEST_BUS_CTRL (BUS_REG_BASE + 0xDC) + +#define VFE_BUS_WM_CFG(n) (BUS_REG_BASE + 0x200 + (n) * 0x100) +#define WM_CFG_EN BIT(0) +#define WM_VIR_FRM_EN BIT(1) +#define WM_CFG_MODE BIT(16) +#define VFE_BUS_WM_IMAGE_ADDR(n) (BUS_REG_BASE + 0x204 + (n) * 0x100) +#define VFE_BUS_WM_FRAME_INCR(n) (BUS_REG_BASE + 0x208 + (n) * 0x100) +#define VFE_BUS_WM_IMAGE_CFG_0(n) (BUS_REG_BASE + 0x20c + (n) * 0x100) +#define WM_IMAGE_CFG_0_DEFAULT_WIDTH (0xFFFF) +#define VFE_BUS_WM_IMAGE_CFG_2(n) (BUS_REG_BASE + 0x214 + (n) * 0x100) +#define WM_IMAGE_CFG_2_DEFAULT_STRIDE (0xFFFF) +#define VFE_BUS_WM_PACKER_CFG(n) (BUS_REG_BASE + 0x218 + (n) * 0x100) + +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (BUS_REG_BASE + 0x230 + (n) * 0x100) +#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (BUS_REG_BASE + 0x234 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (BUS_REG_BASE + 0x238 + (n) * 0x100) +#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (BUS_REG_BASE + 0x23c + (n) * 0x100) + +#define VFE_BUS_WM_MMU_PREFETCH_CFG(n) (BUS_REG_BASE + 0x260 + (n) * 0x100) +#define VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(n) (BUS_REG_BASE + 0x264 + (n) * 0x100) + +/* + * Bus client mapping: + * + * Full VFE: + * 23 = RDI0, 24 = RDI1, 25 = RDI2 + * + * VFE LITE: + * 0 = RDI0, 1 = RDI1, 2 = RDI3, 4 = RDI4 + */ +#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n)) + +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line) +{ + struct v4l2_pix_format_mplane *pix = + &line->video_out.active_fmt.fmt.pix_mp; + + wm = RDI_WM(wm); + + /* no clock gating at bus input */ + writel(WM_CGC_OVERRIDE_ALL, vfe->base + VFE_BUS_WM_CGC_OVERRIDE); + + writel(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL); + + writel(ALIGN(pix->plane_fmt[0].bytesperline, 16) * pix->height >> 8, + vfe->base + VFE_BUS_WM_FRAME_INCR(wm)); + writel((WM_IMAGE_CFG_0_DEFAULT_WIDTH & 0xFFFF), + vfe->base + VFE_BUS_WM_IMAGE_CFG_0(wm)); + writel(WM_IMAGE_CFG_2_DEFAULT_STRIDE, + vfe->base + VFE_BUS_WM_IMAGE_CFG_2(wm)); + writel(0, vfe->base + VFE_BUS_WM_PACKER_CFG(wm)); + + /* no dropped frames, one irq per frame */ + writel(0, vfe->base + VFE_BUS_WM_FRAMEDROP_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_FRAMEDROP_PATTERN(wm)); + writel(0, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(wm)); + writel(1, vfe->base + VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(wm)); + + writel(1, vfe->base + VFE_BUS_WM_MMU_PREFETCH_CFG(wm)); + writel(0xFFFFFFFF, vfe->base + VFE_BUS_WM_MMU_PREFETCH_MAX_OFFSET(wm)); + + writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm) +{ + wm = RDI_WM(wm); + writel(0, vfe->base + VFE_BUS_WM_CFG(wm)); +} + +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr, + struct vfe_line *line) +{ + wm = RDI_WM(wm); + writel((addr >> 8) & 0xFFFFFFFF, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm)); + + dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", + wm, addr); +} + +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) +{ + int port_id = line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, false); +} + +static inline void vfe_reg_update_clear(struct vfe_device *vfe, + enum vfe_line_id line_id) +{ + int port_id = line_id; + + camss_reg_update(vfe->camss, vfe->id, port_id, true); +} + +static const struct camss_video_ops vfe_video_ops_780 = { + .queue_buffer = vfe_queue_buffer_v2, + .flush_buffers = vfe_flush_buffers, +}; + +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) +{ + vfe->video_ops = vfe_video_ops_780; +} + +static void vfe_global_reset(struct vfe_device *vfe) +{ + vfe_isr_reset_ack(vfe); +} + +static irqreturn_t vfe_isr(int irq, void *dev) +{ + /* nop */ + return IRQ_HANDLED; +} + +static int vfe_halt(struct vfe_device *vfe) +{ + /* rely on vfe_disable_output() to stop the VFE */ + return 0; +} + +const struct vfe_hw_ops vfe_ops_780 = { + .global_reset = vfe_global_reset, + .hw_version = vfe_hw_version, + .isr = vfe_isr, + .pm_domain_off = vfe_pm_domain_off, + .pm_domain_on = vfe_pm_domain_on, + .reg_update = vfe_reg_update, + .reg_update_clear = vfe_reg_update_clear, + .subdev_init = vfe_subdev_init, + .vfe_disable = vfe_disable, + .vfe_enable = vfe_enable_v2, + .vfe_halt = vfe_halt, + .vfe_wm_start = vfe_wm_start, + .vfe_wm_stop = vfe_wm_stop, + .vfe_buf_done = vfe_buf_done, + .vfe_wm_update = vfe_wm_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 1c9b6569fbe5..c95b127a7e2e 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -344,6 +344,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_8550: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1964,6 +1965,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_8550: ret = 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h index 977710d6655e..2a2e2d82dd51 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.h +++ b/drivers/media/platform/qcom/camss/camss-vfe.h @@ -242,6 +242,7 @@ extern const struct vfe_hw_ops vfe_ops_4_7; extern const struct vfe_hw_ops vfe_ops_4_8; extern const struct vfe_hw_ops vfe_ops_170; extern const struct vfe_hw_ops vfe_ops_480; +extern const struct vfe_hw_ops vfe_ops_780; int vfe_get(struct vfe_device *vfe); void vfe_put(struct vfe_device *vfe); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index c0e336f3916b..e8cc96d3d0d2 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1823,6 +1823,125 @@ static const struct camss_subdev_resources csid_res_8550[] = { } }; +static const struct camss_subdev_resources vfe_res_8550[] = { + /* VFE0 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe0_fast_ahb", + "vfe0", "cpas_vfe0", "camnoc_axi" }, + .clock_rate = { { 0 }, + { 80000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 466000000, 594000000, 675000000, 785000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 } }, + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = true, + .pd_name = "ife0", + .hw_ops = &vfe_ops_780, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe1_fast_ahb", + "vfe1", "cpas_vfe1", "camnoc_axi" }, + .clock_rate = { { 0 }, + { 80000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 466000000, 594000000, 675000000, 785000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 } }, + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = true, + .pd_name = "ife1", + .hw_ops = &vfe_ops_780, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE2 */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe2_fast_ahb", + "vfe2", "cpas_vfe2", "camnoc_axi" }, + .clock_rate = { { 0 }, + { 80000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 466000000, 594000000, 675000000, 785000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 } }, + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = true, + .pd_name = "ife2", + .hw_ops = &vfe_ops_780, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE3 lite */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb", + "vfe_lite", "cpas_ife_lite", "camnoc_axi" }, + .clock_rate = { { 0 }, + { 80000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 400000000, 480000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 } }, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_780, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE4 lite */ + { + .regulators = {}, + .clock = { "gcc_axi_hf", "cpas_ahb", "cpas_fast_ahb_clk", "vfe_lite_ahb", + "vfe_lite", "cpas_ife_lite", "camnoc_axi" }, + .clock_rate = { { 0 }, + { 80000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 400000000, 480000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 } }, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_780, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, +}; + static const struct resources_icc icc_res_sm8550[] = { { .name = "ahb", @@ -2861,11 +2980,13 @@ static const struct camss_resources sm8550_resources = { .pd_name = "top", .csiphy_res = csiphy_res_8550, .csid_res = csid_res_8550, + .vfe_res = vfe_res_8550, .csid_wrapper_res = &csid_wrapper_res_sm8550, .icc_res = icc_res_sm8550, .icc_path_num = ARRAY_SIZE(icc_res_sm8550), .csiphy_num = ARRAY_SIZE(csiphy_res_8550), .csid_num = ARRAY_SIZE(csid_res_8550), + .vfe_num = ARRAY_SIZE(vfe_res_8550), .link_entities = camss_link_entities };