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Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index a36076e3c56b..6a2074297030 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2993,6 +2993,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie6a_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + status = "disabled"; }; @@ -3115,6 +3119,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie5_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; }; @@ -3235,6 +3241,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&pcie4_phy>; phy-names = "pciephy"; + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + status = "disabled"; pcie4_port0: pcie@0 { From patchwork Thu Dec 12 10:32:16 2024 Content-Type: text/plain; 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Thu, 12 Dec 2024 02:33:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IElanJ8KkR3sCWlb0GFEATrawGXJB1omKXePD/LX/rTbd5LgqiTium01uUQCjp1zG2hz9q8YA== X-Received: by 2002:a17:902:f68f:b0:215:2f00:67b1 with SMTP id d9443c01a7336-2177852005amr91703135ad.6.1733999581629; Thu, 12 Dec 2024 02:33:01 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2178db5b42asm11102335ad.244.2024.12.12.02.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2024 02:33:01 -0800 (PST) From: Krishna Chaitanya Chundru Date: Thu, 12 Dec 2024 16:02:16 +0530 Subject: [PATCH v2 2/4] PCI: of: Add API to retrieve equalization presets from device tree Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241212-preset_v2-v2-2-210430fbcd8a@oss.qualcomm.com> References: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> In-Reply-To: <20241212-preset_v2-v2-0-210430fbcd8a@oss.qualcomm.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio , Krishna Chaitanya Chundru , Krishna chaitanya chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 17 +++++++++++++++-- 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index dacea3fc5128..99e0e7ae12e9 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -826,3 +826,48 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + char name[20]; + void **preset; + void *temp; + int ret; + + if (of_property_present(dev->of_node, "eq-presets-8gts")) { + presets->eq_presets_8gts = devm_kzalloc(dev, sizeof(u16) * num_lanes, GFP_KERNEL); + if (!presets->eq_presets_8gts) + return -ENOMEM; + + ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + } + + for (int i = 1; i < sizeof(struct pci_eq_presets) / sizeof(void *); i++) { + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << i); + if (of_property_present(dev->of_node, name)) { + temp = devm_kzalloc(dev, sizeof(u8) * num_lanes, GFP_KERNEL); + if (!temp) + return -ENOMEM; + + ret = of_property_read_u8_array(dev->of_node, name, + temp, num_lanes); + if (ret) { + dev_err(dev, "Error %s %d\n", name, ret); + return ret; + } + + preset = (void **)((u8 *)presets + i * sizeof(void *)); + *preset = temp; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 14d00ce45bfa..82362d58bedc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -731,7 +731,12 @@ static inline u64 pci_rebar_size_to_bytes(int size) } struct device_node; - +struct pci_eq_presets { + void *eq_presets_8gts; + void *eq_presets_16gts; + void *eq_presets_32gts; + void *eq_presets_64gts; +}; #ifdef CONFIG_OF int of_pci_parse_bus_range(struct device_node *node, struct resource *res); int of_get_pci_domain_nr(struct device_node *node); @@ -746,7 +751,9 @@ void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); - +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes); #else static inline int of_pci_parse_bus_range(struct device_node *node, struct resource *res) @@ -793,6 +800,12 @@ static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_br return 0; } +static inline int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + return 0; +} #endif /* CONFIG_OF */ struct of_changeset; From patchwork Thu Dec 12 10:32:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13904959 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E468721170B for ; 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a=ed25519-sha256; t=1733999565; l=3448; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=5rxRkPnumzzfAdemdZBFDf4pCGC4z3dLReWUJOLysOk=; b=PfWVknQFvds1Vncgw8MASrZsGeAdq18UFhYaeSeVV0UZEfJnZ3Lq/buK38XEW+1jRTxbIcrum O73OaU8IybTBbBquqghOBSF5AbS0n20cNl5BcvOK+u7/yZW9aFD2UMF X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: OROoIe-SH_cQwJ_OAazBx7YaMVECbvLa X-Proofpoint-GUID: OROoIe-SH_cQwJ_OAazBx7YaMVECbvLa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1011 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120074 From: Krishna chaitanya chundru Currently even if the number of lanes hardware supports is equal to the number lanes provided in the devicetree, the driver is trying to configure again the maximum number of lanes which is not needed. Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3e41865c7290..2cd0acbf9e18 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + if (pci->num_lanes < 1) + pci->num_lanes = dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..acb2a963ae1a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -736,6 +736,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) } +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u32 lnkcap; + u8 cap; + + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) { u32 lnkcap, lwsc, plc; @@ -1069,6 +1079,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) void dw_pcie_setup(struct dw_pcie *pci) { + int num_lanes = dw_pcie_link_get_max_link_width(pci); u32 val; dw_pcie_link_set_max_speed(pci); @@ -1102,5 +1113,6 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); + if (num_lanes != pci->num_lanes) + dw_pcie_link_set_max_link_width(pci, pci->num_lanes); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..500e793c9361 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -486,6 +486,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci); int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, From patchwork Thu Dec 12 10:32:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 13904960 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CCD020B1F7 for ; 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Signed-off-by: Krishna chaitanya chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2cd0acbf9e18..5f017b7ab932 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -694,10 +694,28 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); +static int dw_pcie_host_start_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + return dw_pcie_start_link(pci); +} + +static void dw_pcie_host_stop_link(struct pci_bus *bus) +{ + struct dw_pcie_rp *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + dw_pcie_stop_link(pci); +} + static struct pci_ops dw_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, + .start_link = dw_pcie_host_start_link, + .stop_link = dw_pcie_host_stop_link, }; static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)