From patchwork Thu Dec 12 14:00:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905234 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75C4A2AF0E; Thu, 12 Dec 2024 14:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012179; cv=none; b=kndVHT+/YGAs+r63eQVAGkMm1idtVp8y7BXWkHCtA7kpFxWXS45+/JLpotRr2NZUzUe8b4VYjVq9kV4CJRxdzdMbyn9jmPbPJoyMrjtljqDNKadopoEwXQofdHNwFHJSfCpTSwxQjsBMOFogIqQh1XdedN4oIWULQKsUEQ6EyyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012179; c=relaxed/simple; bh=DmdYTP32GF7FMD0V8FptK4pVHw0QjiNU7SvaxwERjtE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=QJuGx2QJmmH+8fneYyXSj6WOyUTxclOUWdjOj9fgSCBJ7rNx2ZmdRMO6XKisEqhqi9VItP0CR8YMzfErfY022oiT4QUdDoIj1TOJOWGmAuoNbfqZPc+y2IlNABfs9yJDzkL3WImOJFjz2kh62QqQ5xX0VX+VEBxsbCrrrUPdRUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ePL0ia6f; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ePL0ia6f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734012178; x=1765548178; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=DmdYTP32GF7FMD0V8FptK4pVHw0QjiNU7SvaxwERjtE=; b=ePL0ia6fgSW0L3Z1R11mE4m9OXA/0ixRFYwlCEaI1hBsDG8EkmW102Wh cypaweGnb8V4Ccv43uTLEutUm7uYI+M7s0vnfnaVXMd2rZhW2eKV864r/ 5SUY4p5LWwippQuzzH4ddHt2az5AuRsD4BnBPXNav478WMxG/WBWERUso Z+8R4WWD+obg5wzrJb1LByTaGgI/t2UkHs/xZzDj4b0x5/uaBGi44i7vn ZXaRc3YU7korLJGgSB/oSdP4h2rwHuK7BT+ZQoI1Zk5qRZkroBcFQwDqZ m1fUuQduB4ybz05GEUdG5vLkTnsCEYLSBXOkBoxlcNajjhvbu8DfwfLCv Q==; X-CSE-ConnectionGUID: oiIFklUfTeaa22CstmnMIA== X-CSE-MsgGUID: n4yMmg0SSneF8NhRIX49+g== X-IronPort-AV: E=McAfee;i="6700,10204,11284"; a="34154972" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34154972" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:02:56 -0800 X-CSE-ConnectionGUID: 6srgGy58StuaSWtLR+dUzA== X-CSE-MsgGUID: VF+k8lvQRUqjGbfzCYmcAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465385" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:02:53 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 1/7] x86/mce: Make several functions return bool Date: Thu, 12 Dec 2024 22:00:57 +0800 Message-Id: <20241212140103.66964-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make several functions that return 0 or 1 return a boolean value for better readability. No functional changes are intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v5: - No changes. Changes in v4: - Don't rename mce_notify_irq() - Boris. Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Rename mce_notify_irq() to mce_notify_user() (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/include/asm/mce.h | 4 ++-- arch/x86/kernel/cpu/mce/amd.c | 10 +++++----- arch/x86/kernel/cpu/mce/core.c | 22 +++++++++++----------- arch/x86/kernel/cpu/mce/intel.c | 9 +++++---- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 4543cf2eb5e8..ea9ca7689f6b 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -276,7 +276,7 @@ static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} #endif -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); bool mce_usable_address(struct mce *m); @@ -296,7 +296,7 @@ enum mcp_flags { void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); -int mce_notify_irq(void); +bool mce_notify_irq(void); DECLARE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6ca80fff1fea..018874b554cb 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -381,7 +381,7 @@ static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) return msr_high_bits & BIT(28); } -static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) +static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; @@ -389,7 +389,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } if (apic != msr) { @@ -399,15 +399,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) * was set is reserved. Return early here: */ if (mce_flags.smca) - return 0; + return false; pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } - return 1; + return true; }; /* Reprogram MCx_MISC MSR behind this threshold bank. */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7fb5556a0b53..167965bd2ac0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -492,10 +492,10 @@ static noinstr void mce_gather_info(struct mce_hw_err *err, struct pt_regs *regs } } -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { if (mca_cfg.disabled) - return 0; + return false; return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } @@ -1778,7 +1778,7 @@ static void mce_timer_delete_all(void) * Can be called from interrupt context, but not from machine check/NMI * context. */ -int mce_notify_irq(void) +bool mce_notify_irq(void) { /* Not more than two messages every minute */ static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); @@ -1789,9 +1789,9 @@ int mce_notify_irq(void) if (__ratelimit(&ratelimit)) pr_info(HW_ERR "Machine check events logged\n"); - return 1; + return true; } - return 0; + return false; } EXPORT_SYMBOL_GPL(mce_notify_irq); @@ -2015,25 +2015,25 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) return 0; } -static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 != 5) - return 0; + return false; switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_p5_mcheck_init(c); mce_flags.p5 = 1; - return 1; + return true; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); mce_flags.winchip = 1; - return 1; + return true; default: - return 0; + return false; } - return 0; + return false; } /* diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index b3cd2c61b11d..f863df0ff42c 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS]; */ #define CMCI_STORM_THRESHOLD 32749 -static int cmci_supported(int *banks) +static bool cmci_supported(int *banks) { u64 cap; if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce) - return 0; + return false; /* * Vendor check is not strictly needed, but the initial @@ -89,10 +89,11 @@ static int cmci_supported(int *banks) */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) - return 0; + return false; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) - return 0; + return false; + rdmsrl(MSR_IA32_MCG_CAP, cap); *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); From patchwork Thu Dec 12 14:00:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905235 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42F3621171A; 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a="34155094" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34155094" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:23 -0800 X-CSE-ConnectionGUID: dOiWKAifQbaCgESBfPLycw== X-CSE-MsgGUID: djCujwWIR6OwHrB7SGF5Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465513" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:18 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 2/7] x86/mce/threshold: Remove the redundant this_cpu_dec_return() Date: Thu, 12 Dec 2024 22:00:58 +0800 Message-Id: <20241212140103.66964-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The 'storm' variable points to this_cpu_ptr(&storm_desc). Access the 'stormy_bank_count' field through the 'storm' to avoid calling this_cpu_*() on the same per-CPU variable twice. This minor optimization reduces the text size by 16 bytes. $ size threshold.o.* text data bss dec hex filename 1395 1664 0 3059 bf3 threshold.o.old 1379 1664 0 3043 be3 threshold.o.new No functional changes intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v5: - No changes. Changes in v4: - No changes. Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/kernel/cpu/mce/threshold.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/threshold.c b/arch/x86/kernel/cpu/mce/threshold.c index 89e31e1e5c9c..f4a007616468 100644 --- a/arch/x86/kernel/cpu/mce/threshold.c +++ b/arch/x86/kernel/cpu/mce/threshold.c @@ -90,7 +90,7 @@ void cmci_storm_end(unsigned int bank) storm->banks[bank].in_storm_mode = false; /* If no banks left in storm mode, stop polling. */ - if (!this_cpu_dec_return(storm_desc.stormy_bank_count)) + if (!--storm->stormy_bank_count) mce_timer_kick(false); } From patchwork Thu Dec 12 14:00:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905236 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E67B42AF0E; Thu, 12 Dec 2024 14:03:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012213; cv=none; b=rqNEhE8BJXZmrc/0vpF1MJ+qccQsrepEUUNX4bfx8dEL9L/wQsDRuaZDhi28WGiILMvy3yd1bXwnWg25g1ItE20lAtu6PcX6wWJb3mZfvql7e8vLzQtkQSSw70g3kqzZsTiFfybuI+EHm3tLdMpeOzxxTgdauiurH7j1uwlI1zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012213; c=relaxed/simple; bh=9AtoswEzvy6dedv1iFBC7Tp+vtUxFePfYFyh2Sbwe14=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=AEdBiyZNNN1yaAjuKHik9rTaoAiXpcpW6k6noKjzMErc7r3m35qyDyFyWRMjLDm7L6XBCTybkxDMcpZMGH9urRG6ZYEsEInFHAzEcaoJGc1DDDL2Pv2jv6YZYTC7HQq39SY37FIqp1qd6orO6JG2zv43/T4xqPxB9aLjU2ql2iM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=J6Umax10; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="J6Umax10" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734012212; x=1765548212; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=9AtoswEzvy6dedv1iFBC7Tp+vtUxFePfYFyh2Sbwe14=; b=J6Umax10gjhhiAsc58beU+hvooYxhDjcp4ABM/TNEgqvA673wacNRGN2 5OMCyduup+HHPTA9T6ESFsqKhQFwtwxCqLeQC3ZzYyXAOfqxD+wVfcG7S ttumGfYu4A3EFE6EfBb3bVpyKtJO2xsMvLuJgyFG6lCDD2/yQZKmFmIWL BNhGICixCnOdkUzHzBUupQWj3snJ2nOc5bswPpyAbWPgv3iyiLiAujtaw K6ZbjD+tkB6rvItUDb/lTsfeypsI4/MfnfGGCTL5rz6wVJCwQCxkvpHw1 NxcbZcWlANMD2z/F/7mg925Pejm2QhA4Msuh0T5tfzK29vsZaKMk/3F4X A==; X-CSE-ConnectionGUID: sNE8RfSgTG+DXf6RgAQNew== X-CSE-MsgGUID: pWBjosg/TbSdvJpzbP7YSA== X-IronPort-AV: E=McAfee;i="6700,10204,11284"; a="34155157" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34155157" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:30 -0800 X-CSE-ConnectionGUID: 0ygcj6xbQG2nVRpXlig4XQ== X-CSE-MsgGUID: h0bN8cvtREiO5R44HReaPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465533" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:27 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 3/7] x86/mce: Make four functions return bool Date: Thu, 12 Dec 2024 22:00:59 +0800 Message-Id: <20241212140103.66964-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make those functions whose callers only care about success or failure return a boolean value for better readability. Also, update the call sites accordingly as the polarities of all the return values have been flipped. No functional changes. Suggested-by: Thomas Gleixner Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v5: - Collect "Reviewed-by:" from Sohil. - Mention the polarities of return values are flipped in the commit message. Changes in v4: - New patch. arch/x86/kernel/cpu/mce/core.c | 12 ++++++------ arch/x86/kernel/cpu/mce/genpool.c | 29 ++++++++++++++--------------- arch/x86/kernel/cpu/mce/internal.h | 4 ++-- 3 files changed, 22 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 167965bd2ac0..ce6fe5e20805 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -151,7 +151,7 @@ EXPORT_PER_CPU_SYMBOL_GPL(injectm); void mce_log(struct mce_hw_err *err) { - if (!mce_gen_pool_add(err)) + if (mce_gen_pool_add(err)) irq_work_queue(&mce_irq_work); } EXPORT_SYMBOL_GPL(mce_log); @@ -1911,14 +1911,14 @@ static void __mcheck_cpu_check_banks(void) } /* Add per CPU specific workarounds here */ -static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); struct mca_config *cfg = &mca_cfg; if (c->x86_vendor == X86_VENDOR_UNKNOWN) { pr_info("unknown CPU type - not enabling MCE support\n"); - return -EOPNOTSUPP; + return false; } /* This should be disabled by the BIOS, but isn't always */ @@ -2012,7 +2012,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (cfg->bootlog != 0) cfg->panic_timeout = 30; - return 0; + return true; } static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) @@ -2279,12 +2279,12 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c) __mcheck_cpu_cap_init(); - if (__mcheck_cpu_apply_quirks(c) < 0) { + if (!__mcheck_cpu_apply_quirks(c)) { mca_cfg.disabled = 1; return; } - if (mce_gen_pool_init()) { + if (!mce_gen_pool_init()) { mca_cfg.disabled = 1; pr_emerg("Couldn't allocate MCE records pool!\n"); return; diff --git a/arch/x86/kernel/cpu/mce/genpool.c b/arch/x86/kernel/cpu/mce/genpool.c index d0be6dda0c14..3ca9c007a666 100644 --- a/arch/x86/kernel/cpu/mce/genpool.c +++ b/arch/x86/kernel/cpu/mce/genpool.c @@ -94,64 +94,63 @@ bool mce_gen_pool_empty(void) return llist_empty(&mce_event_llist); } -int mce_gen_pool_add(struct mce_hw_err *err) +bool mce_gen_pool_add(struct mce_hw_err *err) { struct mce_evt_llist *node; if (filter_mce(&err->m)) - return -EINVAL; + return false; if (!mce_evt_pool) - return -EINVAL; + return false; node = (void *)gen_pool_alloc(mce_evt_pool, sizeof(*node)); if (!node) { pr_warn_ratelimited("MCE records pool full!\n"); - return -ENOMEM; + return false; } memcpy(&node->err, err, sizeof(*err)); llist_add(&node->llnode, &mce_event_llist); - return 0; + return true; } -static int mce_gen_pool_create(void) +static bool mce_gen_pool_create(void) { int mce_numrecords, mce_poolsz, order; struct gen_pool *gpool; - int ret = -ENOMEM; void *mce_pool; order = order_base_2(sizeof(struct mce_evt_llist)); gpool = gen_pool_create(order, -1); if (!gpool) - return ret; + return false; mce_numrecords = max(MCE_MIN_ENTRIES, num_possible_cpus() * MCE_PER_CPU); mce_poolsz = mce_numrecords * (1 << order); mce_pool = kmalloc(mce_poolsz, GFP_KERNEL); if (!mce_pool) { gen_pool_destroy(gpool); - return ret; + return false; } - ret = gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1); - if (ret) { + + if (gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1)) { gen_pool_destroy(gpool); kfree(mce_pool); - return ret; + return false; } mce_evt_pool = gpool; - return ret; + return true; } -int mce_gen_pool_init(void) +bool mce_gen_pool_init(void) { /* Just init mce_gen_pool once. */ if (mce_evt_pool) - return 0; + return true; return mce_gen_pool_create(); } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 84f810598231..95a504ece43e 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -31,8 +31,8 @@ struct mce_evt_llist { void mce_gen_pool_process(struct work_struct *__unused); bool mce_gen_pool_empty(void); -int mce_gen_pool_add(struct mce_hw_err *err); -int mce_gen_pool_init(void); +bool mce_gen_pool_add(struct mce_hw_err *err); +bool mce_gen_pool_init(void); struct llist_node *mce_gen_pool_prepare_records(void); int mce_severity(struct mce *a, struct pt_regs *regs, char **msg, bool is_excp); From patchwork Thu Dec 12 14:01:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905241 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09D512135BA; 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a="34155204" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34155204" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:40 -0800 X-CSE-ConnectionGUID: +zW2Ui/UQ4qqWM2MwK+S2g== X-CSE-MsgGUID: mh4AtgyrTRmxt7fqIZq0ew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465567" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:35 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 4/7] x86/mce: Break up __mcheck_cpu_apply_quirks() Date: Thu, 12 Dec 2024 22:01:00 +0800 Message-Id: <20241212140103.66964-5-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Tony Luck Split each vendor specific part into its own helper function. Signed-off-by: Tony Luck Tested-by: Qiuxu Zhuo Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v5: - Collect "Reviewed-by:" from Sohil. Changes in v4: - Add necessary blank lines in apply_quirks_amd() (Yazen). - Use 'mca_cfg' instead of 'cfg' in apply_quirks_*(). (Yazen). Changes in v3: - New patch. arch/x86/kernel/cpu/mce/core.c | 192 ++++++++++++++++++--------------- 1 file changed, 104 insertions(+), 88 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ce6fe5e20805..3855ec2ed0e0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1910,101 +1910,117 @@ static void __mcheck_cpu_check_banks(void) } } +static void apply_quirks_amd(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + + /* This should be disabled by the BIOS, but isn't always */ + if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { + /* + * disable GART TBL walk error reporting, which + * trips off incorrectly with the IOMMU & 3ware + * & Cerberus: + */ + clear_bit(10, (unsigned long *)&mce_banks[4].ctl); + } + + if (c->x86 < 0x11 && mca_cfg.bootlog < 0) { + /* + * Lots of broken BIOS around that don't clear them + * by default and leave crap in there. Don't log: + */ + mca_cfg.bootlog = 0; + } + + /* + * Various K7s with broken bank 0 around. Always disable + * by default. + */ + if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) + mce_banks[0].ctl = 0; + + /* + * overflow_recov is supported for F15h Models 00h-0fh + * even though we don't have a CPUID bit for it. + */ + if (c->x86 == 0x15 && c->x86_model <= 0xf) + mce_flags.overflow_recov = 1; + + if (c->x86 >= 0x17 && c->x86 <= 0x1A) + mce_flags.zen_ifu_quirk = 1; +} + +static void apply_quirks_intel(struct cpuinfo_x86 *c) +{ + struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + + /* + * SDM documents that on family 6 bank 0 should not be written + * because it aliases to another special BIOS controlled + * register. + * But it's not aliased anymore on model 0x1a+ + * Don't ignore bank 0 completely because there could be a + * valid event later, merely don't write CTL0. + */ + if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) + mce_banks[0].init = false; + + /* + * All newer Intel systems support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && + mca_cfg.monarch_timeout < 0) + mca_cfg.monarch_timeout = USEC_PER_SEC; + + /* + * There are also broken BIOSes on some Pentium M and + * earlier systems: + */ + if (c->x86 == 6 && c->x86_model <= 13 && mca_cfg.bootlog < 0) + mca_cfg.bootlog = 0; + + if (c->x86_vfm == INTEL_SANDYBRIDGE_X) + mce_flags.snb_ifu_quirk = 1; + + /* + * Skylake, Cascacde Lake and Cooper Lake require a quirk on + * rep movs. + */ + if (c->x86_vfm == INTEL_SKYLAKE_X) + mce_flags.skx_repmov_quirk = 1; +} + +static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c) +{ + /* + * All newer Zhaoxin CPUs support MCE broadcasting. Enable + * synchronization with a one second timeout. + */ + if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { + if (mca_cfg.monarch_timeout < 0) + mca_cfg.monarch_timeout = USEC_PER_SEC; + } +} + /* Add per CPU specific workarounds here */ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) { - struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); struct mca_config *cfg = &mca_cfg; - if (c->x86_vendor == X86_VENDOR_UNKNOWN) { + switch (c->x86_vendor) { + case X86_VENDOR_UNKNOWN: pr_info("unknown CPU type - not enabling MCE support\n"); return false; - } - - /* This should be disabled by the BIOS, but isn't always */ - if (c->x86_vendor == X86_VENDOR_AMD) { - if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) { - /* - * disable GART TBL walk error reporting, which - * trips off incorrectly with the IOMMU & 3ware - * & Cerberus: - */ - clear_bit(10, (unsigned long *)&mce_banks[4].ctl); - } - if (c->x86 < 0x11 && cfg->bootlog < 0) { - /* - * Lots of broken BIOS around that don't clear them - * by default and leave crap in there. Don't log: - */ - cfg->bootlog = 0; - } - /* - * Various K7s with broken bank 0 around. Always disable - * by default. - */ - if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) - mce_banks[0].ctl = 0; - - /* - * overflow_recov is supported for F15h Models 00h-0fh - * even though we don't have a CPUID bit for it. - */ - if (c->x86 == 0x15 && c->x86_model <= 0xf) - mce_flags.overflow_recov = 1; - - if (c->x86 >= 0x17 && c->x86 <= 0x1A) - mce_flags.zen_ifu_quirk = 1; - - } - - if (c->x86_vendor == X86_VENDOR_INTEL) { - /* - * SDM documents that on family 6 bank 0 should not be written - * because it aliases to another special BIOS controlled - * register. - * But it's not aliased anymore on model 0x1a+ - * Don't ignore bank 0 completely because there could be a - * valid event later, merely don't write CTL0. - */ - - if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) - mce_banks[0].init = false; - - /* - * All newer Intel systems support MCE broadcasting. Enable - * synchronization with a one second timeout. - */ - if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && - cfg->monarch_timeout < 0) - cfg->monarch_timeout = USEC_PER_SEC; - - /* - * There are also broken BIOSes on some Pentium M and - * earlier systems: - */ - if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) - cfg->bootlog = 0; - - if (c->x86_vfm == INTEL_SANDYBRIDGE_X) - mce_flags.snb_ifu_quirk = 1; - - /* - * Skylake, Cascacde Lake and Cooper Lake require a quirk on - * rep movs. - */ - if (c->x86_vfm == INTEL_SKYLAKE_X) - mce_flags.skx_repmov_quirk = 1; - } - - if (c->x86_vendor == X86_VENDOR_ZHAOXIN) { - /* - * All newer Zhaoxin CPUs support MCE broadcasting. Enable - * synchronization with a one second timeout. - */ - if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) { - if (cfg->monarch_timeout < 0) - cfg->monarch_timeout = USEC_PER_SEC; - } + case X86_VENDOR_AMD: + apply_quirks_amd(c); + break; + case X86_VENDOR_INTEL: + apply_quirks_intel(c); + break; + case X86_VENDOR_ZHAOXIN: + apply_quirks_zhaoxin(c); + break; } if (cfg->monarch_timeout < 0) From patchwork Thu Dec 12 14:01:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905242 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3FB12144A6; Thu, 12 Dec 2024 14:04:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012265; cv=none; b=FLK07+otFLgBffeuE6kDUt/0zm0NJ742D+YHrnGCqFSppoByUA2uZK5TCbIs2bn0c0r9TLTOq1LOJQY102epw3amd4zuv6DJ2sJ/SXeLe27JwiyOlMvnE0cdi7XIvHc18SBljluaivj5iT3g2VlBQs/GPT5YwpgmzpooIcE9W7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012265; c=relaxed/simple; bh=CRnalEdgYhX9PXf7PXLXrNncXJsnuFzKijuQtScciGw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=WpMaHRsKASVKHXVmq55L8uqgItya9Atp/tAElUFCGq5SpVFOlj9b21U2Gzc4tcZi3KteOQgMs9exkl3JkdDRwfpaUF3qxCTbatQP7qOQU4v4Czq2E1OEKOlVDeMjVdwl5cBlw+a4B4AHtHVIqD6EDK+1HHdDR1DZ4lX1wamsGrk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CafTW9Rc; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CafTW9Rc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734012264; x=1765548264; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CRnalEdgYhX9PXf7PXLXrNncXJsnuFzKijuQtScciGw=; b=CafTW9RcCoxChL/3gQthdGD+At7iTZMxngL98/IleJxQoVrfIlDgyrPP sLaGegfr0cKLbHLM+BdwUvXKdjQjuBrO/AE4kiuk2G+p3rl+R9yR8cYPN AKjUIi38DZ7xJaw5JWH9nQU+97w7Ehgvf2YDxITeRQ6Uf8vwfVHydkzEN kkCXR131zTuox0AAz1w8Sh2jUhCZVd9MJo5zuAtXpnPLj0L6lVfGn/RVG Nksmf5kQ1wz09YPa4AskJz7NrmildVusFZJPJ6wl+fQdeH/1yER8eJVo+ F51GyxF26Hu7D4g6Xrc+o/1hx1MGOj1WuROjmYBaaLv1mHzLAMCF51kZ+ A==; X-CSE-ConnectionGUID: oY3SJGKrTDO29Ftms0lzQw== X-CSE-MsgGUID: tMdWeme0T3yjdxGrBdofRw== X-IronPort-AV: E=McAfee;i="6700,10204,11284"; a="34155237" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34155237" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:47 -0800 X-CSE-ConnectionGUID: zARhF+X5T52CA5rIVzNL/g== X-CSE-MsgGUID: u5d2uhgJS+SffjHOD0Qu+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465588" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:43 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 5/7] x86/mce: Convert family/model mixed checks to VFM-based checks Date: Thu, 12 Dec 2024 22:01:01 +0800 Message-Id: <20241212140103.66964-6-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Convert family/model mixed checks to VFM-based checks to make the code more compact. Also, as 'mce_num_banks' is an unsigned int, simplify the check from 'if (this_cpu_read(mce_num_banks) > 0)' to 'if (this_cpu_read(mce_num_banks))'. Suggested-by: Sohil Mehta Suggested-by: Dave Hansen Reviewed-by: Tony Luck Reviewed-by: Sohil Mehta Reviewed-by: Yazen Ghannam Signed-off-by: Qiuxu Zhuo --- Changes in v5: - Collect "Reviewed-by:" from Sohil & Yazen. - Reduce 'if (mce_num_banks > 0)' to 'if (mce_num_banks)' - Yazen. Changes in v4: - No changes but rebased. Changes in v3: - Newly added. arch/x86/kernel/cpu/mce/core.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 3855ec2ed0e0..f90cbcb31a62 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1936,7 +1936,7 @@ static void apply_quirks_amd(struct cpuinfo_x86 *c) * Various K7s with broken bank 0 around. Always disable * by default. */ - if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0) + if (c->x86 == 6 && this_cpu_read(mce_num_banks)) mce_banks[0].ctl = 0; /* @@ -1954,6 +1954,10 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + /* Older CPUs (prior to family 6) don't need quirks. */ + if (c->x86_vfm < INTEL_PENTIUM_PRO) + return; + /* * SDM documents that on family 6 bank 0 should not be written * because it aliases to another special BIOS controlled @@ -1962,22 +1966,21 @@ static void apply_quirks_intel(struct cpuinfo_x86 *c) * Don't ignore bank 0 completely because there could be a * valid event later, merely don't write CTL0. */ - if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0) + if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks)) mce_banks[0].init = false; /* * All newer Intel systems support MCE broadcasting. Enable * synchronization with a one second timeout. */ - if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && - mca_cfg.monarch_timeout < 0) + if (c->x86_vfm >= INTEL_CORE_YONAH && mca_cfg.monarch_timeout < 0) mca_cfg.monarch_timeout = USEC_PER_SEC; /* * There are also broken BIOSes on some Pentium M and * earlier systems: */ - if (c->x86 == 6 && c->x86_model <= 13 && mca_cfg.bootlog < 0) + if (c->x86_vfm < INTEL_CORE_YONAH && mca_cfg.bootlog < 0) mca_cfg.bootlog = 0; if (c->x86_vfm == INTEL_SANDYBRIDGE_X) From patchwork Thu Dec 12 14:01:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905243 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0D60215188; Thu, 12 Dec 2024 14:04:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012266; cv=none; b=ruOJQgVK+6wH35c0gOYU3k/662j2lqzyN6A0B2pM1WlPmYYFgm2u6lvMHWjFxYQh4cqRFa8gWpkRq8ggRv1cMaopxv+/VJsipjIKPWzMcSHiIlMz9x2WTHoO0yRaj5iXzIpAQID9l8LvnMwdoNub/rGHI11kKWgM8/KSMd6s/FE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012266; c=relaxed/simple; bh=JAjG1ocGNBjy11UcEoLMWl8vcDfQWxElwDAlTf8j6nw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=kxWycNMqoU5VrvqNxh8fV15OUMEmf2BmPHCffVVa12sDn5PYBAJl3D2jkL9QYkVXPhcUfhdLWp5SiBmfoGxKuSI1i+Ptc8iyHibxQnC8DQhhWvaSjeXffFP2hJSTRpOyEnOgItjUzgMBomLPcc7oKKNRSH+VTWBMie8c+uqnS9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=H6d7QD9E; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="H6d7QD9E" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734012265; x=1765548265; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=JAjG1ocGNBjy11UcEoLMWl8vcDfQWxElwDAlTf8j6nw=; b=H6d7QD9EHWmeRBdeYDUrAXPTs3E6T0wFSXNFXnJGMFS9KFxwdKmG67yo ard+1PaU44SjBFwxl9vIUZjqd5phXNrbUKpieqo4Ttemc2YpgyWbn7JB0 nUFLZMhoh8hC6MI+VQl/gHl/i3jg8FkgmU1kw+rMBv26OpKXYRAMr0L8S YahXbQu+wu+KJgdwNeYDLSdKBWfmtcvd+s2phoKDRy0/j5aLx+MefpMWo TSuglJMerkc30RpGHJ99ZJEbJcLZ5JH19znUxZdDZOCCykraZhPnaHV0S +bQXm1QmjafLl5nLl4+kusUQSCoyWF21oDpxR+dOaqWVFn9I/p2SsMmn0 A==; X-CSE-ConnectionGUID: nskkjHhqSu678MgTT3A43w== X-CSE-MsgGUID: TPtYfHCBS5GL/2zaFumbxw== X-IronPort-AV: E=McAfee;i="6700,10204,11284"; a="34155268" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34155268" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:53 -0800 X-CSE-ConnectionGUID: uJq4lcnFTcWHf167sw/7BQ== X-CSE-MsgGUID: lGvI3aS+RkWkFGukAX/LQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465605" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:49 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 6/7] x86/mce: Remove the redundant mce_hygon_feature_init() Date: Thu, 12 Dec 2024 22:01:02 +0800 Message-Id: <20241212140103.66964-7-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Get HYGON to directly call mce_amd_feature_init() and remove the redundant mce_hygon_feature_init(). Suggested-by: Yazen Ghannam Signed-off-by: Qiuxu Zhuo Reviewed-by: Sohil Mehta Reviewed-by: Yazen Ghannam --- Changes in v5: - New patch. arch/x86/include/asm/mce.h | 2 -- arch/x86/kernel/cpu/mce/core.c | 8 ++------ 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index ea9ca7689f6b..eb2db07ef39c 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -386,8 +386,6 @@ static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } #endif -static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } - unsigned long copy_mc_fragile_handle_tail(char *to, char *from, unsigned len); #endif /* _ASM_X86_MCE_H */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index f90cbcb31a62..0dc00c9894c7 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2118,14 +2118,10 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_intel_feature_init(c); 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d="scan'208";a="96465621" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:03:56 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 7/7] x86/mce/amd: Remove unnecessary NULL pointer initializations Date: Thu, 12 Dec 2024 22:01:03 +0800 Message-Id: <20241212140103.66964-8-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Remove unnecessary NULL pointer initializations from variables that are already initialized before use. Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Reviewed-by: Yazen Ghannam Signed-off-by: Qiuxu Zhuo --- Changes in v5: - Collect "Reviewed-by:" Yazen. Changes in v4: - No changes. Changes in v3: - Collect "Reviewed-by:" Nikolay & Sohil. - Remove the variables' names from the commit message (Sohil). arch/x86/kernel/cpu/mce/amd.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 018874b554cb..c79a82912d38 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -921,8 +921,8 @@ static void log_and_reset_block(struct threshold_block *block) */ static void amd_threshold_interrupt(void) { - struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; struct threshold_bank **bp = this_cpu_read(threshold_banks); + struct threshold_block *first_block, *block, *tmp; unsigned int bank, cpu = smp_processor_id(); /* @@ -1201,8 +1201,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb static int __threshold_add_blocks(struct threshold_bank *b) { struct list_head *head = &b->blocks->miscj; - struct threshold_block *pos = NULL; - struct threshold_block *tmp = NULL; + struct threshold_block *pos, *tmp; int err = 0; err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); @@ -1312,8 +1311,7 @@ static void deallocate_threshold_blocks(struct threshold_bank *bank) static void __threshold_remove_blocks(struct threshold_bank *b) { - struct threshold_block *pos = NULL; - struct threshold_block *tmp = NULL; + struct threshold_block *pos, *tmp; kobject_put(b->kobj);