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Signed-off-by: Yunxiang Li --- drivers/vfio/pci/vfio_pci_config.c | 8 ++------ drivers/vfio/pci/vfio_pci_core.c | 10 ++-------- drivers/vfio/pci/vfio_pci_rdwr.c | 3 --- 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index ea2745c1ac5e6..e41c3a965663e 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -511,13 +511,9 @@ static void vfio_bar_fixup(struct vfio_pci_core_device *vdev) mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); mask |= PCI_ROM_ADDRESS_ENABLE; *vbar &= cpu_to_le32((u32)mask); - } else if (pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW) { - mask = ~(0x20000 - 1); - mask |= PCI_ROM_ADDRESS_ENABLE; - *vbar &= cpu_to_le32((u32)mask); - } else + } else { *vbar = 0; + } vdev->bardirty = false; } diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index 1ab58da9f38a6..b49dd9cdc072a 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1057,14 +1057,8 @@ static int vfio_pci_ioctl_get_region_info(struct vfio_pci_core_device *vdev, /* Report the BAR size, not the ROM size */ info.size = pci_resource_len(pdev, info.index); - if (!info.size) { - /* Shadow ROMs appear as PCI option ROMs */ - if (pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW) - info.size = 0x20000; - else - break; - } + if (!info.size) + break; /* * Is it really there? Enable memory decode for implicit access diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 66b72c2892841..a1eeacad82120 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -244,9 +244,6 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, if (pci_resource_start(pdev, bar)) end = pci_resource_len(pdev, bar); - else if (bar == PCI_ROM_RESOURCE && - pdev->resource[bar].flags & IORESOURCE_ROM_SHADOW) - end = 0x20000; else return -EINVAL; From patchwork Thu Dec 12 20:50:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Yunxiang (Teddy)" X-Patchwork-Id: 13905970 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2063.outbound.protection.outlook.com [40.107.92.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48CAD54723 for ; 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Thu, 12 Dec 2024 14:51:00 -0600 From: Yunxiang Li To: , CC: , , , , Yunxiang Li Subject: [PATCH 2/3] vfio/pci: refactor vfio_pci_bar_rw Date: Thu, 12 Dec 2024 15:50:49 -0500 Message-ID: <20241212205050.5737-2-Yunxiang.Li@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241212205050.5737-1-Yunxiang.Li@amd.com> References: <20241212205050.5737-1-Yunxiang.Li@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004682:EE_|CY8PR12MB7514:EE_ X-MS-Office365-Filtering-Correlation-Id: a1f7a539-7e9b-4b0c-0920-08dd1aeeaff9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: jguzQv7oAeVfjv8cT8PbnJlExLrSoSS9sSZ93uZdJS8iQeJ1IKxb9tzSTLe/3ID4Tvlsr0H5ymYK6a5RKLv+XmlPT0eQyxKOoDVMVTaWNz95b4x3TA7Rg+sWRq3DFeQJazi4boWYAE05e+NHYOEwG43E0p+G3z1FZ4GvjW6/JyJOuWggrBtMjgnViMDQrsBzAVD6Q9TLm1a1kjEGaPGe3r4lD3kJj0m0dgaFqBLEggJVvIuxI4bEXVrwecrYAFiWvPNYctSyqCmsSdiY1UzUXyCJySBd1PS4DIKoS3HUpqlMhnUzGggE6UH9+w9vwAY10Lr3ODEw1ZGClRsQ7eHwodDKUukwV3dSdoARSoZM2mjxpwZRLF0o4Iy5wRnGtfW5NyVvak3lcEvNZ7kzbHe4yy+kdvtPjG8FzUrzg5q3wH5+WsJzyHk5/ZJR5CgZJx9Jh8WTBkGjbNRDDj0e4kCUtzja40VJ0zk94R4sukL3q9p6USL68bYTqLxkvc1TynuTGtgdyxra1w9/1XpPwh+tz2n4rGNY636Jfi8G4nvpSQqvFNNHtXxlfCrNYxsaD+8QguDXSmd62gvX0+xeWZmdEP+KPIC0OBtccBSXy7FTusPusZONrrPbZCmNJl9o+1nu50h1zrVXoDIf19l1ZfEJ4F8nM8RPmmYykGhv+vL1yX2+UfUKrzeLr4g+kv6RBJB2Mpcw5k5GKumuuIpG+fVrN7NUkYBQGkVnCncHTne3ehUBPJ//EvNr6q1t6CqGHlKBuFG3AnP4mXpFcUrkjJX93rNDHRPo6gcDomawUgoTtEfC9r6AOQgDqrwCjFhh+unl2yRfJpREPd5jx+/GpegZhkpgRLxoN5wRo0i+2Ht/dQqDA5t8kjX8x6rlNa40yJuIBFS8Vzwq/eeyNvBvpCtR9Fz0kT7ic5VwOKNQGScUf3F3BAqBHvjPeEOfvr83tIo7e+KyerHAe9KUQ6uzUvu+SS1Pfa3lmVUjoP+JdTQ8R6URjZOTO2AKbFcunXiqxLG/8zEGYY1j5UieIXhC6lp7QvIZwPpp6gzf3e81s0zipjdEReaHMwnWfr0DHrUwsB5NNyZupZGun1PhLuwL+eyMzebQ94wQZ1cFzxqKqMqjsjIZl+pFyhfqH27M0n7r/D3vYnJxe7VSHtnwMSrO2hxCYo7743WIZIK6aktFF5x2rgSz4wRpxoOdwMuCp9jFc+TFjhruuF+yk1y1QMsY1rew8V2ZjnQUJ/0/OclzkDRFdzY32GFB0KfXotYcOaJWifs1BBkpaZ89bUerBUCGkXcPmrrWpydlzwBfiNJNCcV84NC8fT6S7O8q96ciYkg3Wr/g5Z5L4SrQP4P/mfcQDaleoUhPgvs0xsBS84qt2nSgeqJ1VO/O+U+Sx4+L8KSqnAXlLbMRBxyr6qlqrouhayHNwwt6ptPJVoUOtMrywMrvDgq/3COkECPURIpTLoAGh53l X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:51:01.2725 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1f7a539-7e9b-4b0c-0920-08dd1aeeaff9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7514 In the next patch the logic for reading ROM will get more complicated, so decouple the ROM path from the normal path. Also check that for ROM write is not allowed. Signed-off-by: Yunxiang Li --- drivers/vfio/pci/vfio_pci_rdwr.c | 47 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index a1eeacad82120..4bed9fd5af50f 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -236,10 +236,9 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, struct pci_dev *pdev = vdev->pdev; loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK; int bar = VFIO_PCI_OFFSET_TO_INDEX(*ppos); - size_t x_start = 0, x_end = 0; + size_t x_start, x_end; resource_size_t end; void __iomem *io; - struct resource *res = &vdev->pdev->resource[bar]; ssize_t done; if (pci_resource_start(pdev, bar)) @@ -253,41 +252,43 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, count = min(count, (size_t)(end - pos)); if (bar == PCI_ROM_RESOURCE) { + if (iswrite) + return -EINVAL; /* * The ROM can fill less space than the BAR, so we start the * excluded range at the end of the actual ROM. This makes * filling large ROM BARs much faster. */ io = pci_map_rom(pdev, &x_start); - if (!io) { - done = -ENOMEM; - goto out; - } + if (!io) + return -ENOMEM; x_end = end; + + done = vfio_pci_core_do_io_rw(vdev, 1, io, buf, pos, + count, x_start, x_end, 0); + + pci_unmap_rom(pdev, io); } else { - int ret = vfio_pci_core_setup_barmap(vdev, bar); - if (ret) { - done = ret; - goto out; - } + done = vfio_pci_core_setup_barmap(vdev, bar); + if (done) + return done; io = vdev->barmap[bar]; - } - if (bar == vdev->msix_bar) { - x_start = vdev->msix_offset; - x_end = vdev->msix_offset + vdev->msix_size; - } + if (bar == vdev->msix_bar) { + x_start = vdev->msix_offset; + x_end = vdev->msix_offset + vdev->msix_size; + } else { + x_start = 0; + x_end = 0; + } - done = vfio_pci_core_do_io_rw(vdev, res->flags & IORESOURCE_MEM, io, buf, pos, + done = vfio_pci_core_do_io_rw(vdev, pci_resource_flags(pdev, bar) & IORESOURCE_MEM, io, buf, pos, count, x_start, x_end, iswrite); - - if (done >= 0) - *ppos += done; - - if (bar == PCI_ROM_RESOURCE) - pci_unmap_rom(pdev, io); + } out: + if (done > 0) + *ppos += done; return done; } From patchwork Thu Dec 12 20:50:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Yunxiang (Teddy)" X-Patchwork-Id: 13905971 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68E5C1B6D1C for ; Thu, 12 Dec 2024 20:51:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734036671; cv=fail; b=VL5LbX1fByColbicMMWURfp0yrvAZ0WSPKz52UxSL6anRLRQAChxS3HmS3QEMEGvUQm8hbeCUDKE+qwKwDbWLwtDR/ZsF9Zrny+UoABGPA9dYuf9Er8fr7oJs1/y3hpVl3UOjINvNlYHx8atbEfZf5EXocJSOW/w5Pbg/yP1xag= ARC-Message-Signature: i=2; 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Thu, 12 Dec 2024 20:51:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00004682.mail.protection.outlook.com (10.167.243.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8251.15 via Frontend Transport; Thu, 12 Dec 2024 20:51:02 +0000 Received: from MKM-L10-YUNXIA9.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Dec 2024 14:51:00 -0600 From: Yunxiang Li To: , CC: , , , , Yunxiang Li Subject: [PATCH 3/3] vfio/pci: Expose setup ROM at ROM bar when needed Date: Thu, 12 Dec 2024 15:50:50 -0500 Message-ID: <20241212205050.5737-3-Yunxiang.Li@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241212205050.5737-1-Yunxiang.Li@amd.com> References: <20241212205050.5737-1-Yunxiang.Li@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004682:EE_|SJ1PR12MB6196:EE_ X-MS-Office365-Filtering-Correlation-Id: ea85f077-6216-490a-b41f-08dd1aeeb085 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2024 20:51:02.1788 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea85f077-6216-490a-b41f-08dd1aeeb085 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004682.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6196 If ROM bar is missing for any reason, we can fallback to using pdev->rom to expose the ROM content to the guest. This fixes some passthrough use cases where the upstream bridge does not have enough address window. Signed-off-by: Yunxiang Li --- drivers/vfio/pci/vfio_pci_config.c | 4 ++++ drivers/vfio/pci/vfio_pci_core.c | 35 +++++++++++++++--------------- drivers/vfio/pci/vfio_pci_rdwr.c | 14 ++++++++++-- 3 files changed, 34 insertions(+), 19 deletions(-) diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index e41c3a965663e..4c673d842fb35 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -511,6 +511,10 @@ static void vfio_bar_fixup(struct vfio_pci_core_device *vdev) mask = ~(pci_resource_len(pdev, PCI_ROM_RESOURCE) - 1); mask |= PCI_ROM_ADDRESS_ENABLE; *vbar &= cpu_to_le32((u32)mask); + } else if (pdev->rom && pdev->romlen) { + mask = ~(roundup_pow_of_two(pdev->romlen) - 1); + mask |= PCI_ROM_ADDRESS_ENABLE; + *vbar &= cpu_to_le32((u32)mask); } else { *vbar = 0; } diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c index b49dd9cdc072a..3120c1e9f22cb 100644 --- a/drivers/vfio/pci/vfio_pci_core.c +++ b/drivers/vfio/pci/vfio_pci_core.c @@ -1049,30 +1049,31 @@ static int vfio_pci_ioctl_get_region_info(struct vfio_pci_core_device *vdev, break; case VFIO_PCI_ROM_REGION_INDEX: { void __iomem *io; - size_t size; + size_t dont_care; u16 cmd; info.offset = VFIO_PCI_INDEX_TO_OFFSET(info.index); info.flags = 0; + info.size = 0; - /* Report the BAR size, not the ROM size */ - info.size = pci_resource_len(pdev, info.index); - if (!info.size) - break; - - /* - * Is it really there? Enable memory decode for implicit access - * in pci_map_rom(). - */ - cmd = vfio_pci_memory_lock_and_enable(vdev); - io = pci_map_rom(pdev, &size); - if (io) { + if (pci_resource_start(pdev, PCI_ROM_RESOURCE)) { + /* Check ROM content is valid. Need to enable memory + * decode for ROM access in pci_map_rom(). + */ + cmd = vfio_pci_memory_lock_and_enable(vdev); + io = pci_map_rom(pdev, &dont_care); + if (io) { + info.flags = VFIO_REGION_INFO_FLAG_READ; + /* Report the BAR size, not the ROM size. */ + info.size = pci_resource_len(pdev, PCI_ROM_RESOURCE); + pci_unmap_rom(pdev, io); + } + vfio_pci_memory_unlock_and_restore(vdev, cmd); + } else if (pdev->rom && pdev->romlen) { info.flags = VFIO_REGION_INFO_FLAG_READ; - pci_unmap_rom(pdev, io); - } else { - info.size = 0; + /* Report BAR size as power of two. */ + info.size = roundup_pow_of_two(pdev->romlen); } - vfio_pci_memory_unlock_and_restore(vdev, cmd); break; } diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c index 4bed9fd5af50f..4ea983cf499d9 100644 --- a/drivers/vfio/pci/vfio_pci_rdwr.c +++ b/drivers/vfio/pci/vfio_pci_rdwr.c @@ -243,6 +243,8 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, if (pci_resource_start(pdev, bar)) end = pci_resource_len(pdev, bar); + else if (bar == PCI_ROM_RESOURCE && pdev->rom && pdev->romlen) + end = roundup_pow_of_two(pdev->romlen); else return -EINVAL; @@ -259,7 +261,12 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, * excluded range at the end of the actual ROM. This makes * filling large ROM BARs much faster. */ - io = pci_map_rom(pdev, &x_start); + if (pci_resource_start(pdev, bar)) { + io = pci_map_rom(pdev, &x_start); + } else { + io = ioremap(pdev->rom, pdev->romlen); + x_start = pdev->romlen; + } if (!io) return -ENOMEM; x_end = end; @@ -267,7 +274,10 @@ ssize_t vfio_pci_bar_rw(struct vfio_pci_core_device *vdev, char __user *buf, done = vfio_pci_core_do_io_rw(vdev, 1, io, buf, pos, count, x_start, x_end, 0); - pci_unmap_rom(pdev, io); + if (pci_resource_start(pdev, bar)) + pci_unmap_rom(pdev, io); + else + iounmap(io); } else { done = vfio_pci_core_setup_barmap(vdev, bar); if (done)