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Fri, 13 Dec 2024 02:39:51 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , Mohan Kumar D Subject: [PATCH v2 1/2] dt-bindings: dma: Support channel page to nvidia,tegra210-adma Date: Fri, 13 Dec 2024 16:09:38 +0530 Message-ID: <20241213103939.3851827-2-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213103939.3851827-1-mkumard@nvidia.com> References: <20241213103939.3851827-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD5:EE_|PH7PR12MB6537:EE_ X-MS-Office365-Filtering-Correlation-Id: e7892e99-2e8b-4766-ca42-08dd1b628395 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: QbzjfaUt6dLukBcdQXE3uFRIq0uHYchFXNduq+ztan+NtMRYFDijU8OLUoVMB4LtH2It/0la4ypHks4/Ic8BLNiJb4yiQpbuFePRF+gxEVY0H8qaE+2cKLkyN9o4sIvC8nHszfCchk4Kahk9wmgUfMnGzmNjUO2dgh60FV89SUVxOMfNgDtCrqyPxdY3snrn9fA3+SxfOSEVTrwRu8f0IEvsID4zDRSGq6Te3n6eGBvwCLcfRk7ANimRcSbXmmNu/5qyivkEa7Nnvn7UyNQV6AjSR1ApnMtM3sBByps/g7OaHC0WaXfeXpn5cYWcJqz1OJG6TMqAOmOOlzwQAl3jCdsJZ5NhZX/qQRrnv4GpbhS5mrcIrRVEQ+iDSjO5DzxWlhHUSLXXnlWEOnm5qzPIRb8kTAXeRJCeDcpQZnAZomjfR3kaGtTFOQJtNYbNl5YYJv7WnpKAYqKPopq+ec33ZTggUuwcZKfXpspbaZn10m5bXQE7fQjwOspQ0I2YYT6mRpsebRIDA7dEMVe6PVyVYBXwcFxqYYrr6/zn6T39Cv5do6MfLOv6xpXqbew0cSH1jLdfChoOse+koCprKl8cJmYlQdQ/7tkNgSr51eFeFqRuo16UcOyG2EtHHvZumKRRy6MGYVtrzeiXzDwdF6VGlNPyEADISuUqhqNBMJKyCJMdvVwOkjy84DgemWdYtetk2PdQnj2vvCHclOCcReW/aV9awVe26WG3NR+b7pWxWsbahSrtsLs/GK+q2MbJo+ntYMpkAcvmPUuBQ9Kkooz1DeNvccQwDHqzIdOUdTXn/0YyrVpjDYPE5kml+mHd2HrRNEi3qbxCBXXhh3L0hQSTdiUAPCcSPq7Ek8oGQjlPwJ+B0lKIopHzT2ZwNqYI87/PYXlMDUwTn0/IvsRo8ODLTRTWDEu8qmZa9hPljENGcS3rdmNj4V+Ff7o2vxjzw+IeQWPho/KshYnNsk8bJx3bACSArZlOAhEg7jLNVfY66Vux6tmqeUmQrbRUIORv7joYyS/xcjYnKLikUI1lF7E72KENl9wqSdS20vSSnvUgBWTrM8Kz2DemHZkjbW7mm4KN/P3goWgJPtP0GCol02eRrhvtN6XoTDag2DdSuCornTkHPnpxxi9/Xxq9hA70H0slbHWZolZyCIR71tEQ/fluqTTAd30kVrHZQiJxl5CfM1LTUMqFX7Vsf6WauYOdMkb70JvvxGmJTFwkvvJSjf1dg/o9mBEK563BGMpXHofmoAj+pBOPsTVrTMFcPo/T9PznIJ9QSWyKVgLawXGTSbtmDfAJA3VNPSBNi5T4ruHtf8pZpy135xYmdrH2x1mZuorCdWrGEW+h9h7RySuT2ssYDkL68hL3WGE4x6pMKJPpwRA+8dMA0YslsRyoermqUXXzM2L5YFfmwWmqekFvUqN0t3N/gskdNBijVsFkWoMnEYd74GLI9GRgNbOQHXHEddGd X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Dec 2024 10:40:08.3761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7892e99-2e8b-4766-ca42-08dd1b628395 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6537 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D --- .../bindings/dma/nvidia,tegra210-adma.yaml | 60 +++++++++++++++++-- 1 file changed, 56 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index 877147e95ecc..d3f8c269916c 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -13,9 +13,6 @@ description: | maintainers: - Jon Hunter -allOf: - - $ref: dma-controller.yaml# - properties: compatible: oneOf: @@ -29,7 +26,19 @@ properties: - const: nvidia,tegra186-adma reg: - maxItems: 1 + description: + The 'page' region describes the address space of the page + used for accessing the DMA channel registers. The 'global' + region describes the address space of the global DMA registers. + In the absence of the 'reg-names' property, there must be a + single entry that covers the address space of the global DMA + registers and the DMA channel registers. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 interrupts: description: | @@ -63,6 +72,49 @@ required: - clocks - clock-names +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-adma + then: + properties: + reg: + items: + - description: Full address space range of DMA registers. + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + anyOf: + - properties: + reg: + items: + - description: Full address space range of DMA registers. + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + reg-names: + items: + - const: page + - properties: + reg: + items: + - description: Channel Page address space range of DMA registers. + - description: Global Page address space range of DMA registers. + reg-names: + items: + - const: page + - const: global + additionalProperties: false examples: From patchwork Fri Dec 13 10:39:39 2024 Content-Type: text/plain; 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Fri, 13 Dec 2024 02:39:55 -0800 From: Mohan Kumar D To: , , , CC: , , , , , , , Mohan Kumar D Subject: [PATCH v2 2/2] dmaengine: tegra210-adma: Support channel page Date: Fri, 13 Dec 2024 16:09:39 +0530 Message-ID: <20241213103939.3851827-3-mkumard@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241213103939.3851827-1-mkumard@nvidia.com> References: <20241213103939.3851827-1-mkumard@nvidia.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|PH7PR12MB5783:EE_ X-MS-Office365-Filtering-Correlation-Id: e89c7fe4-3932-49ce-5e4a-08dd1b628588 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: gaMn3aOgLsW+8LaK/3CO3WiNxrjNmQx3zGBisHWOPtyWKzJHRbFkgJ0/XzPKv3GekCwyv35xLudr3z+EALOkhGGFfGtw4Agc2PvVCq0hSUqm+k+oRznHScSRqyH2beLCJ1b+NWtOFiG2vZ8JD4nIoz1iHGHM8LVgXj/Hhf4af2E4wvyD9EiEgMDDgQhNotxfcRnPuEFmtdJcMJYbkGej3Qq91P8I9DsvKU21eAkid5Jo+/HYGj+ygceNNiViWpsoD+0kbq1PCIBQp8kuRJU3HRgVg+BSF2HPWurb6m7O6uOuWc5M3OfFMpHpGIpHSSJPlOmvWwnDrSu4aR7dukfVQlU3qeJh+C32isHs6Db3Dmfa8c+XnN79ZVAnGSJv/Zs6HRmViGGcW4E7LByjRV1sTjjA4QvXpLpb7Eu8CeyESlUDN1mf0r9rIVLYdsNdGZrgVe6ly2FOj2z6iMU8vStgNl2CusmZmju6YXYcUeb6kaf/zSjoyTNv3K0LZBwtAHN1/ipKTIuCkjTCEO4N0igcCFGxaeC7tHfhLvghR2MpYYNZjLiMqZm8VDhKbqbfTd48yxHk4ZhYgnZ9GTJjVH3SyKOOaSsmJ1Z2llKuFe25A3GfMid77p+1cu+uAM46LvqlautkEh6zjh5umQ0utD3I1O2PRFJwYBcvXUP8GCUkVpNj0JljMSKyAEhIZIYKANnizCc0qm7h3IK2RwkMj82SQlVvUwCATa3B2QlIOOLKguVH48wOqpRuR9Rd7ZLWQq37WdcZVBHLluM99O/tj5ls6uxtDCDBghOWloC572mCGM5qcnQwiLhkpbxm2/xdtCKdYp/BgIu4H1TFouhVt8cYZwnuun867fydq6n20m1cEsu8l4eLjAMm1MyaXh5XWcCFOYn6ho3ABuctRocEsSmD02IqGvp6O0cqrN5feVMupO0czUE4X9DElJGO6X/L4DEeoQNjcJC4TIvcRCAIatXrCt8X341TuApTTr7/FN8eVluTxZ/nN7r+giP59/q6viAj5oI26NCE1yR2YsFIJMLs9EPCgt8c3BCDTL8eDa4DmAjXuS26x9cHKtFa49LZSX888jcoJgfw3PG+ewVp0pkCqLR/i9aGu8rNZM7BR8GG9xwmatwwD5vNYN3wDaB7UPGFgQFfCsnqxTdj10ixynRBZ1ueBd6yr4rVaJQdmnuTK/3HjzFXN152X/nPTt80oJl9oJGPL1N3sgsyNEZh0TEF4b/p9TTbJMKfWOjnG84urFOJMLj/KhMGvbYl9VeFGGP2btjAt/raE5eSgg+pecKoodGuBF5ddjvLBi3kCTjdWwRQe3nGvEMhmj8hGbSx758j2ZsQEYsQbdTyalTPpZoewTygtFVp3XnIxnPPGlWEbiUbN3imqaAVrsY8cj1FRX/lAGOcPyQAFO0Ut4oLC6wKIokhv4AdI1v9w0dqi9uY+EveqkwN3LPExPzxpcoVcz5F X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Dec 2024 10:40:11.6123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e89c7fe4-3932-49ce-5e4a-08dd1b628588 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5783 Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. - Add support in the tegra adma driver to handle selective channel page usage - Make global register programming optional Signed-off-by: Mohan Kumar D --- drivers/dma/tegra210-adma.c | 86 ++++++++++++++++++++++++++++++++----- 1 file changed, 76 insertions(+), 10 deletions(-) diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c index 2953008d42ef..6896da8ac7ef 100644 --- a/drivers/dma/tegra210-adma.c +++ b/drivers/dma/tegra210-adma.c @@ -43,6 +43,10 @@ #define ADMA_CH_CONFIG_MAX_BUFS 8 #define TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(reqs) (reqs << 4) +#define TEGRA186_ADMA_GLOBAL_PAGE_CHGRP 0x30 +#define TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ 0x70 +#define TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ 0x84 + #define ADMA_CH_FIFO_CTRL 0x2c #define ADMA_CH_TX_FIFO_SIZE_SHIFT 8 #define ADMA_CH_RX_FIFO_SIZE_SHIFT 0 @@ -96,6 +100,7 @@ struct tegra_adma_chip_data { unsigned int ch_fifo_size_mask; unsigned int sreq_index_offset; bool has_outstanding_reqs; + void (*set_global_pg_config)(struct tegra_adma *tdma); }; /* @@ -151,6 +156,7 @@ struct tegra_adma { struct dma_device dma_dev; struct device *dev; void __iomem *base_addr; + void __iomem *ch_base_addr; struct clk *ahub_clk; unsigned int nr_channels; unsigned long *dma_chan_mask; @@ -159,6 +165,7 @@ struct tegra_adma { /* Used to store global command register state when suspending */ unsigned int global_cmd; + unsigned int ch_page_no; const struct tegra_adma_chip_data *cdata; @@ -176,6 +183,11 @@ static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg) return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); } +static inline void tdma_ch_global_write(struct tegra_adma *tdma, u32 reg, u32 val) +{ + writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg); +} + static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) { writel(val, tdc->chan_addr + reg); @@ -217,13 +229,30 @@ static int tegra_adma_slave_config(struct dma_chan *dc, return 0; } +static void tegra186_adma_global_page_config(struct tegra_adma *tdma) +{ + /* + * Clear the default page1 channel group configs and program + * the global registers based on the actual page usage + */ + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ, 0); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_CHGRP + (tdma->ch_page_no * 0x4), 0xff); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_RX_REQ + (tdma->ch_page_no * 0x4), 0x1ffffff); + tdma_write(tdma, TEGRA186_ADMA_GLOBAL_PAGE_TX_REQ + (tdma->ch_page_no * 0x4), 0xffffff); +} + static int tegra_adma_init(struct tegra_adma *tdma) { u32 status; int ret; - /* Clear any interrupts */ - tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); + /* Clear any channels group global interrupts */ + tdma_ch_global_write(tdma, tdma->cdata->global_int_clear, 0x1); + + if (!tdma->base_addr) + return 0; /* Assert soft reset */ tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); @@ -237,6 +266,9 @@ static int tegra_adma_init(struct tegra_adma *tdma) if (ret) return ret; + if (tdma->cdata->set_global_pg_config) + tdma->cdata->set_global_pg_config(tdma); + /* Enable global ADMA registers */ tdma_write(tdma, ADMA_GLOBAL_CMD, 1); @@ -736,7 +768,9 @@ static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) struct tegra_adma_chan *tdc; int i; - tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (tdma->base_addr) + tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); + if (!tdma->global_cmd) goto clk_disable; @@ -777,7 +811,11 @@ static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) dev_err(dev, "ahub clk_enable failed: %d\n", ret); return ret; } - tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + if (tdma->base_addr) { + tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); + if (tdma->cdata->set_global_pg_config) + tdma->cdata->set_global_pg_config(tdma); + } if (!tdma->global_cmd) return 0; @@ -817,6 +855,7 @@ static const struct tegra_adma_chip_data tegra210_chip_data = { .ch_fifo_size_mask = 0xf, .sreq_index_offset = 2, .has_outstanding_reqs = false, + .set_global_pg_config = NULL, }; static const struct tegra_adma_chip_data tegra186_chip_data = { @@ -833,6 +872,7 @@ static const struct tegra_adma_chip_data tegra186_chip_data = { .ch_fifo_size_mask = 0x1f, .sreq_index_offset = 4, .has_outstanding_reqs = true, + .set_global_pg_config = tegra186_adma_global_page_config, }; static const struct of_device_id tegra_adma_of_match[] = { @@ -846,7 +886,8 @@ static int tegra_adma_probe(struct platform_device *pdev) { const struct tegra_adma_chip_data *cdata; struct tegra_adma *tdma; - int ret, i; + struct resource *res_page, *res_base; + int ret, i, page_no; cdata = of_device_get_match_data(&pdev->dev); if (!cdata) { @@ -865,9 +906,35 @@ static int tegra_adma_probe(struct platform_device *pdev) tdma->nr_channels = cdata->nr_channels; platform_set_drvdata(pdev, tdma); - tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(tdma->base_addr)) - return PTR_ERR(tdma->base_addr); + res_page = platform_get_resource_byname(pdev, IORESOURCE_MEM, "page"); + if (res_page) { + tdma->ch_base_addr = devm_ioremap_resource(&pdev->dev, res_page); + if (IS_ERR(tdma->ch_base_addr)) + return PTR_ERR(tdma->ch_base_addr); + + res_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global"); + if (res_base) { + page_no = (res_page->start - res_base->start) / cdata->ch_base_offset; + if (page_no <= 0) + return -EINVAL; + tdma->ch_page_no = page_no - 1; + tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + } + } else { + /* If no 'page' property found, then reg DT binding would be legacy */ + res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res_base) { + tdma->base_addr = devm_ioremap_resource(&pdev->dev, res_base); + if (IS_ERR(tdma->base_addr)) + return PTR_ERR(tdma->base_addr); + } else { + return -ENODEV; + } + + tdma->ch_base_addr = tdma->base_addr + cdata->ch_base_offset; + } tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); if (IS_ERR(tdma->ahub_clk)) { @@ -900,8 +967,7 @@ static int tegra_adma_probe(struct platform_device *pdev) if (!test_bit(i, tdma->dma_chan_mask)) continue; - tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset - + (cdata->ch_reg_size * i); + tdc->chan_addr = tdma->ch_base_addr + (cdata->ch_reg_size * i); tdc->irq = of_irq_get(pdev->dev.of_node, i); if (tdc->irq <= 0) {