From patchwork Fri Dec 13 14:33:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13907242 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBC0E1E1C0F; Fri, 13 Dec 2024 14:33:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100410; cv=none; b=BlNTFH0osdgr4D7OygfVxC2U2JywZERXc7GP7FYPNEWw77RKIGc9UWF1gubmNKlCL3cry+bNtSDDSlG9rlqMFh2y3sl1NZVeBOgfm5n7fQclBteH+VD2eXjywXmVlZrr93JWqupybjp1SXATrJ0mxw5cTacYlU2+qWvIg6NS6Zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100410; c=relaxed/simple; bh=hf3uPTsI8CFcJFUPNdC68/VsTO/Oc1Od5Tl6oCQzNgs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UwJ5oDkfZQ01PFHgcO+McCfrNK3YcZU+RgszfCqIoaWcPedLuPkSbNHaofRNOgxUmVyTlvqOKOJp48XfjwGsXjLeo6oZFuSQ75gXmVdQzpTvSVsZ9szF7MNOBJ8e8RSFBVleNp3ts+z+yD/PchbusflyhAPJBlxskab/WScX19A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LJE3ZyhX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LJE3ZyhX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8CF6EC4CED0; Fri, 13 Dec 2024 14:33:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734100409; bh=hf3uPTsI8CFcJFUPNdC68/VsTO/Oc1Od5Tl6oCQzNgs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LJE3ZyhXqbMTrh21qkf7fSIuuCt5O7ZVy8jshQSMR/9B6neJf9pkYw82a+P00jcOH Xus4Nliq82zT2tKTSj+5kDK0HsZqfvfgWfLQOBWFDWufrYTH1nJYJjjDw65IOhg9kB upcloYBvfpYixjZZMPGH9/43q2D3dd6YkIb67HYM4lVZA5u972qRD4p6KBbGDMWIc7 BbW0J+5P5LnTRZx/mFssov+bMAu1fpYFkr8o3vVDR3PfxmlDokNZw/sZQKET8vkG/U t+qWYEob1DQ73uw5xNJ0WaJJSG2L6mz4od3JV6oBvjhdThsgtdTQztN3WYZKA/MtwW uAaIWP2QDp8/Q== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , stable@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 1/6] PCI: dwc: ep: Write BAR_MASK before iATU registers in pci_epc_set_bar() Date: Fri, 13 Dec 2024 15:33:02 +0100 Message-ID: <20241213143301.4158431-9-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241213143301.4158431-8-cassel@kernel.org> References: <20241213143301.4158431-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2752; i=cassel@kernel.org; h=from:subject; bh=hf3uPTsI8CFcJFUPNdC68/VsTO/Oc1Od5Tl6oCQzNgs=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJjXBct6Wbb8SJTfM7maG5177wXy+Ijz1/lea/tmb8s1 urys8rqjlIWBjEuBlkxRRbfHy77i7vdpxxXvGMDM4eVCWQIAxenAExEeiYjw0veA68dfAJV7388 eTt6f4iRvel6rz/XLoqf6WKduCPI3ZzhD5dw2jHmaz9nP/LgdLtu9/LFTwatySv6/otNdV13NXB jBhsA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA The "DesignWare Cores PCI Express Controller Register Descriptions, Version 4.60a", section "1.21.70 IATU_LWR_TARGET_ADDR_OFF_INBOUND_i", fields LWR_TARGET_RW and LWR_TARGET_HW both state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. If we do not write the BAR_MASK before writing the iATU registers, we are relying the reset value of the BAR_MASK being larger than the requested BAR size (which is supplied in the struct pci_epf_bar which is passed to pci_epc_set_bar()). The reset value of the BAR_MASK is SoC dependent. Thus, if the struct pci_epf_bar requests a BAR size that is larger than the reset value of the BAR_MASK, the iATU will try to write to read-only bits, which will cause the iATU to end up redirecting to a physical address that is different from the address that was intended. Thus, we should always write the iATU registers after writing the BAR_MASK. Cc: stable@vger.kernel.org Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support") Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 28 ++++++++++--------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index f3ac7d46a855..bad588ef69a4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -222,19 +222,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) return -EINVAL; - reg = PCI_BASE_ADDRESS_0 + (4 * bar); - - if (!(flags & PCI_BASE_ADDRESS_SPACE)) - type = PCIE_ATU_TYPE_MEM; - else - type = PCIE_ATU_TYPE_IO; - - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); - if (ret) - return ret; - if (ep->epf_bar[bar]) - return 0; + goto config_atu; + + reg = PCI_BASE_ADDRESS_0 + (4 * bar); dw_pcie_dbi_ro_wr_en(pci); @@ -246,9 +237,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, dw_pcie_ep_writel_dbi(ep, func_no, reg + 4, 0); } - ep->epf_bar[bar] = epf_bar; dw_pcie_dbi_ro_wr_dis(pci); +config_atu: + if (!(flags & PCI_BASE_ADDRESS_SPACE)) + type = PCIE_ATU_TYPE_MEM; + else + type = PCIE_ATU_TYPE_IO; + + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + if (ret) + return ret; + + ep->epf_bar[bar] = epf_bar; + return 0; } From patchwork Fri Dec 13 14:33:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13907243 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8821F1E1023; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="EytmmJsX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 37DB0C4CED0; Fri, 13 Dec 2024 14:33:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734100413; bh=hUIuEzkuObWfcaT7ire0dHFb9zefHWiHTHS+omNaE1g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EytmmJsXkE4HcNPe3IraDR0GQetCebSuTsl8lfOgp9K7kY9Vkvy8poSYLDwJBMho6 uYOUZBUhkhqbDysSqvbAbUcOjwfIbJ53WXCjKfSJpTitgjkPNW6lu8wFwuGsKunkJf EQ3+AyNdmFlDPagYawrTH9wEtJvwu3ZF57HmrWbVW2CD9UO3f/KMD51QoVa4g+mFNN fzoBouiNVImy5tzkRcQJpZ5eMz7NMeKfa1aWCUC6hbcmunYLvEPMQrzAYaoYdEs8aN ZKqE5FwrSpWVSfZz7AsArR89fUDcY8SsNP3uO+GUMnOx7zZDoCA8vSElnMobBzlAk5 HpMNocudVmd8w== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Frank Li , Jon Mason Cc: Damien Le Moal , Jesper Nilsson , Niklas Cassel , stable@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 2/6] PCI: dwc: ep: Prevent changing BAR size/flags in pci_epc_set_bar() Date: Fri, 13 Dec 2024 15:33:03 +0100 Message-ID: <20241213143301.4158431-10-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241213143301.4158431-8-cassel@kernel.org> References: <20241213143301.4158431-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2690; i=cassel@kernel.org; h=from:subject; bh=hUIuEzkuObWfcaT7ire0dHFb9zefHWiHTHS+omNaE1g=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJjXBdp3btlsFNz323lvfOmG1lzc9fe+LL+7NwpLyvuN EzestPkTkcpC4MYF4OsmCKL7w+X/cXd7lOOK96xgZnDygQyhIGLUwAmYt7E8D/sWktlgbOY1MeD TzT06y7fUyn+2bOQZ41Tt4ZG9LzF7Q0M/3RD1ibNVs7iubpwlmyf+f74CNGlVyRlZ4hvWWWk9yr AhhsA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA In commit 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address") set_bar() was modified to support dynamically changing the backing physical address of a BAR that was already configured. This means that set_bar() can be called twice, without ever calling clear_bar() (as calling clear_bar() would clear the BAR's PCI address assigned by the host). This can only be done if the new BAR size/flags does not differ from the existing BAR configuration. Add these missing checks. If we allow set_bar() to set e.g. a new BAR size that differs from the existing BAR size, the new address translation range will be smaller than the BAR size already determined by the host, which would mean that a read past the new BAR size would pass the iATU untranslated, which could allow the host to read memory not belonging to the new struct pci_epf_bar. While at it, add comments which clarifies the support for dynamically changing the physical address of a BAR. (Which was also missing.) Cc: stable@vger.kernel.org Fixes: 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address") Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- .../pci/controller/dwc/pcie-designware-ep.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index bad588ef69a4..44a617d54b15 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -222,8 +222,28 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, if ((flags & PCI_BASE_ADDRESS_MEM_TYPE_64) && (bar & 1)) return -EINVAL; - if (ep->epf_bar[bar]) + /* + * Certain EPF drivers dynamically change the physical address of a BAR + * (i.e. they call set_bar() twice, without ever calling clear_bar(), as + * calling clear_bar() would clear the BAR's PCI address assigned by the + * host). + */ + if (ep->epf_bar[bar]) { + /* + * We can only dynamically change a BAR if the new BAR size and + * BAR flags do not differ from the existing configuration. + */ + if (ep->epf_bar[bar]->barno != bar || + ep->epf_bar[bar]->size != size || + ep->epf_bar[bar]->flags != flags) + return -EINVAL; + + /* + * When dynamically changing a BAR, skip writing the BAR reg, as + * that would clear the BAR's PCI address assigned by the host. + */ goto config_atu; + } reg = PCI_BASE_ADDRESS_0 + (4 * bar); From patchwork Fri Dec 13 14:33:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13907244 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1AD01E22E2 for ; Fri, 13 Dec 2024 14:33:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100417; cv=none; b=NUVthzgDl/KruBz9skD6WTZ9xVOYgOjCUEJdVHJfymT5KKm1eTzm6Fb7dE5jw9aiOVREMVyKt7tluIrEyIf/ndIeGrzEHCjjcPYz/jn2LKQrWl3CICasR67QMG3odQLDQq66hh6deC9Tx29KtoGaRvXN22r0AaCdakScNfj9NlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100417; c=relaxed/simple; bh=0VouYiquPy2It5bjWm9fqPZiiVDMP+venn6AQh1bAEU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ezEqr6IbBcpW+94OyjVgScfXkosiUA6bJTmlICugjZurk1gIXNY1XFGYFHLqNN4owSL47n644rmnIQtGjC556JfgZX91FKwJsUaaa29eo/lwDk65nlWPk97GsUq00YsYCwy35gcpQY9pV3wIb7R3Lqg4lgk0bBLo+sTHNoSxs/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TwxAlPXn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TwxAlPXn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5E5DC4CED0; Fri, 13 Dec 2024 14:33:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734100416; bh=0VouYiquPy2It5bjWm9fqPZiiVDMP+venn6AQh1bAEU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TwxAlPXnFwOkBGntUnPSMjPs2Qxqf31jIXW2W6fEPcHGl8lkGp8/cbDQIr1Oi46ED RUI64QwVtjSFjzEwgoRdL0UL3xGpQb+dvALDYtDmz+hRrinRGD6rptWs/8ZACxgBAg 616QaMs4UkIQk/OlSperZ2WerIlVUAOxsDa2QgfmaDyXXZ7shvCMprD8EqRNHZbkma Ccfc71ca6C0dn9n8VPRSiv8+eX1bCpMJ9PshXV6sp9Tfvsf69EZBPbmVzJQKPQDHcH EDe3lU4wiApbY8/n5rRMxxj9Yi7e6ciqjr8Lq9f0LqOBC/eGJiJbArAO9meLdZqM1v qsD9GBN4eibmQ== From: Niklas Cassel To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v6 3/6] PCI: dwc: ep: Add 'address' alignment to 'size' check in dw_pcie_prog_ep_inbound_atu() Date: Fri, 13 Dec 2024 15:33:04 +0100 Message-ID: <20241213143301.4158431-11-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241213143301.4158431-8-cassel@kernel.org> References: <20241213143301.4158431-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4323; i=cassel@kernel.org; h=from:subject; bh=0VouYiquPy2It5bjWm9fqPZiiVDMP+venn6AQh1bAEU=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJjXBc/EzyeoZgxm+PIpNxfp4/IMD/h6I25MM+Uu0S69 +6bnV+7O0pZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjCRjY0M/0MTBB8tbdgg/v3u hkCmp/M3V5bO/eYQdIH7TeyRurer46cz/BVufLhLtPuRUjjztXUalU8837488bXtn2dC8tvgr+L TZRgA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA dw_pcie_prog_ep_inbound_atu() is used to program an inbound iATU in "BAR Match Mode". A memory address returned by e.g. kmalloc() is guaranteed to have natural alignment (aligned to the size of the allocation). It is however not guaranteed that pci_epc_set_bar() (and thus dw_pcie_prog_ep_inbound_atu()) is supplied an address that has natural alignment. (An EPF driver can send in an arbitrary physical address to pci_epc_set_bar().) The DWC Databook description for the LWR_TARGET_RW and LWR_TARGET_HW fields in the IATU_LWR_TARGET_ADDR_OFF_INBOUND_i registers state that: "Field size depends on log2(BAR_MASK+1) in BAR match mode." I.e. only the upper bits are writable, and the number of writable bits is dependent on the configured BAR_MASK. Add a check to ensure that the physical address programmed in the iATU is aligned to the size of the BAR (BAR_MASK+1), as without this, we can get hard to debug errors, as we could write to bits that are read-only (without getting a write error), which could cause the iATU to end up redirecting to a physical address that is different from the address that we intended. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 8 +++++--- drivers/pci/controller/dwc/pcie-designware.c | 5 +++-- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 44a617d54b15..8e07d432e74f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -128,7 +128,8 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, - dma_addr_t cpu_addr, enum pci_barno bar) + dma_addr_t cpu_addr, enum pci_barno bar, + size_t size) { int ret; u32 free_win; @@ -145,7 +146,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, } ret = dw_pcie_prog_ep_inbound_atu(pci, func_no, free_win, type, - cpu_addr, bar); + cpu_addr, bar, size); if (ret < 0) { dev_err(pci->dev, "Failed to program IB window\n"); return ret; @@ -265,7 +266,8 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, else type = PCIE_ATU_TYPE_IO; - ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar); + ret = dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar, + size); if (ret) return ret; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 6d6cbc8b5b2c..3c683b6119c3 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -597,11 +597,12 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, } int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar) + int type, u64 cpu_addr, u8 bar, size_t size) { u32 retries, val; - if (!IS_ALIGNED(cpu_addr, pci->region_align)) + if (!IS_ALIGNED(cpu_addr, pci->region_align) || + !IS_ALIGNED(cpu_addr, size)) return -EINVAL; dw_pcie_writel_atu_ib(pci, index, PCIE_ATU_LOWER_TARGET, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 347ab74ac35a..fc0872711672 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -491,7 +491,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u64 size); int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u8 bar); + int type, u64 cpu_addr, u8 bar, size_t size); void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index); void dw_pcie_setup(struct dw_pcie *pci); void dw_pcie_iatu_detect(struct dw_pcie *pci); From patchwork Fri Dec 13 14:33:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13907245 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6C291E2318 for ; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fwu/WgSg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EF2F0C4CED2; Fri, 13 Dec 2024 14:33:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734100419; bh=YkSK1OJRY9aMlx2OTK8VC5n9q/GmDamEjTb97bvOfC4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fwu/WgSgpHuGU9ZnThHrI6iQf0q9x47yEKhPJJrYeyUaivRCrGqUksF6fliHmqip1 qtbxkzS69SRw606h2QlenkevALPp83hgkdp1D0prO5V7FQohexx8T2nUZF41Lqj6E5 xMog9UgFAgfOV27Ucn8+ZZwFunm1G8EZByhIosi4B7gVqv84f26IEN3LZ3qzB7tIVp WLC5Rjic0AIko0SQB0gXxx/KlfLaAMowy6bGNNNrKnoKSDMAhxpxsl52T5Vc9ibAQg dr4qwRCyXOIjCqKc5TnZKVAl+1JB/TtbHYE9xRtMXxL03Ay9HNAfFWNE6WA3F5hUWR datEUEKuPt/ug== From: Niklas Cassel To: Jesper Nilsson , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Niklas Cassel , linux-arm-kernel@axis.com, linux-pci@vger.kernel.org Subject: [PATCH v6 4/6] PCI: artpec6: Implement dw_pcie_ep operation get_features Date: Fri, 13 Dec 2024 15:33:05 +0100 Message-ID: <20241213143301.4158431-12-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241213143301.4158431-8-cassel@kernel.org> References: <20241213143301.4158431-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1719; i=cassel@kernel.org; h=from:subject; bh=YkSK1OJRY9aMlx2OTK8VC5n9q/GmDamEjTb97bvOfC4=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJjXBfvDTzttXQlH+fnv3PYunc0u6y7e83LyFfXzbb7t bOQO39ORykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACYir8zIcJtzh9FrH/tJlmwG C06URJ+TOH/2956Oa3uMdvy3KTC/kMbIsPeVuCKX6Bafa5+U1ktOKqmolps+1dzZeb9s3e+Tmdw sTAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA All non-DWC EPC drivers implement (struct pci_epc *)->ops->get_features(). All DWC EPC drivers implement (struct dw_pcie_ep *)->ops->get_features(), except for pcie-artpec6.c. epc_features has been required in pci-epf-test.c since commit 6613bc2301ba ("PCI: endpoint: Fix NULL pointer dereference for ->get_features()"). A follow-up commit will make further use of epc_features in EPC core code. Implement epc_features in the only EPC driver where it is currently not implemented. Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam Acked-by: Jesper Nilsson Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-artpec6.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index f8e7283dacd4..234c8cbcae3a 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -369,9 +369,22 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } +static const struct pci_epc_features artpec6_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, +}; + +static const struct pci_epc_features * +artpec6_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &artpec6_pcie_epc_features; +} + static const struct dw_pcie_ep_ops pcie_ep_ops = { .init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, + .get_features = artpec6_pcie_get_features, }; static int artpec6_pcie_probe(struct platform_device *pdev) From patchwork Fri Dec 13 14:33:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13907246 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A83BE1E0E10 for ; Fri, 13 Dec 2024 14:33:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100422; cv=none; b=CMdX4Bw8xZ9jL33T3MCHzmySPwcO84WDTlpMKTTTTyQo+jA3vZJNAxT9cjmQ0QImzJA9TeKgyMXs+A7RHv0tqUd7Hx7+xtW3+nG064PBVA0ifSqiNKvhWgkJAUT/lgjSzX1uZgx04ohvbDQEJ+BpTkH+ueybFb0huqhfhN5lj3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100422; c=relaxed/simple; bh=zv0UrLQJcLbh4LKqOpzblK7DRJPEARLfSBhrVvqoUII=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bFH/uCbMgFMOvnS9fn0/Ew21dITPXdkm3ZNCKyq00+8FBOYbGFI4gntx4Ye7MTPLdhZpk/5NJpAN8kazzu0CkD5UQiUkQvFvWho64IO6oyfPckK968yL66+sabXl9JeymPtGUFCznug3WToXaG9ul9jT+rZJ8q4xA8Om9r8x6v0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JtX4T4U9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JtX4T4U9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0FE2C4CED2; Fri, 13 Dec 2024 14:33:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734100422; bh=zv0UrLQJcLbh4LKqOpzblK7DRJPEARLfSBhrVvqoUII=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JtX4T4U9i7KTutiv5gqdVh38VOkCLV60y8NGgJFcIflkazTWxoSS7QaoHUQuHSIHT ZYTwKTLjBFz32VERKSSXhLkML9DP2XBez8fxRUVgkm/oIrSGTVBEtI2zAYtH7CztCL fnPJF2KiDqL8H7OIq6wfWsXwtOAkaCwXluAs/Yq1BQkfLIr4hJcS5/OkfuJTE/qEZd 25z3CJptZhgCcffdhEPmgyxvzUuPriDt9qhwX1AX9JwGXhlx7fPVryrngAHy0GWK+0 6foypsNoDMWQ9sAvzhPA6BVKaRBBGi8nwIOvoaN5OX12IBhgq0+fMzLtSl18TZpy98 ET0xOlg7RrtFQ== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v6 5/6] PCI: endpoint: Add size check for fixed size BARs in pci_epc_set_bar() Date: Fri, 13 Dec 2024 15:33:06 +0100 Message-ID: <20241213143301.4158431-13-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241213143301.4158431-8-cassel@kernel.org> References: <20241213143301.4158431-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1895; i=cassel@kernel.org; h=from:subject; bh=zv0UrLQJcLbh4LKqOpzblK7DRJPEARLfSBhrVvqoUII=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJjXJfsjVqe/21hTkbBZQE7s/sb1125a1BzyL9J4fMu6 1MzjGx8O0pZGMS4GGTFFFl8f7jsL+52n3Jc8Y4NzBxWJpAhDFycAjARtk2MDB8/lDDKR/+z05a6 r521+UzpefV9qYZ7TTId1intS7JZasnI8KpNgqFfPZ03165RZx/Tq2sBecm5ciVRz/V/H7him8b PBAA= X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA A BAR of type BAR_FIXED has a fixed BAR size (the size cannot be changed). When using pci_epf_alloc_space() to allocate backing memory for a BAR, pci_epf_alloc_space() will always set the size to the fixed BAR size if the BAR type is BAR_FIXED (and will give an error if you the requested size is larger than the fixed BAR size). However, some drivers might not call pci_epf_alloc_space() before calling pci_epc_set_bar(), so add a check in pci_epc_set_bar() to ensure that an EPF driver cannot set a size different from the fixed BAR size, if the BAR type is BAR_FIXED. The pci_epc_function_is_valid() check is removed because this check is now done by pci_epc_get_features(). Reviewed-by: Frank Li Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epc-core.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index bed7c7d1fe3c..c69c133701c9 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -609,10 +609,17 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar); int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { - int ret; + const struct pci_epc_features *epc_features; + enum pci_barno bar = epf_bar->barno; int flags = epf_bar->flags; + int ret; - if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + epc_features = pci_epc_get_features(epc, func_no, vfunc_no); + if (!epc_features) + return -EINVAL; + + if (epc_features->bar[bar].type == BAR_FIXED && + (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || From patchwork Fri Dec 13 14:33:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13907247 X-Patchwork-Delegate: kw@linux.com Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 391881E0E08 for ; Fri, 13 Dec 2024 14:33:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100425; cv=none; b=Zf8AlrbXXZZVx6L8w3g8n1zfSBmml0TMbjuClQgUN+MayGFEwZ915R+bgCNFSQVQBAZAzDhVH8Yt/+sgUxz58VbFQfgQJE7Ds6aOGg1mYX79i7Yn516Y/hQaVIWqCUutVY6tLkbiofUQuvWIFJw+q2iZTA785t74yhazs8xp/bQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734100425; c=relaxed/simple; bh=TogfjNWvw13U7UTT/BFwsTkPYIc7m/zcJdIlaNZz+ek=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ThPI0o++ow9uUN38B+kYmBkl/vWikH+QhSBRxRCjUzx3iirqOZp4tGOnZLytotTHr8nMhLPOuglOIzNrhB/7GNGSyTazGUVX1s3siIE392oiBTLUhlVWGk6uZwizlOGp2IveeSEjhngA64TGlvjKab6DUMtomjIkjxhu2Hj6k7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tpvL2rh5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tpvL2rh5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4DBAC4CED7; Fri, 13 Dec 2024 14:33:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734100424; bh=TogfjNWvw13U7UTT/BFwsTkPYIc7m/zcJdIlaNZz+ek=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tpvL2rh5PmMxm506U0ZFrbTmMc2RH/r9+LB0CYavcLOJ/+aOmN59Ec4v13UHJT7pS rQD93Y4wuBkXNYm6bI89PskA2K+UOC9No6DtSmmJNh0CZWkvXDcexGtxmiSmWuxSMI 2P+GLFljgOnwoZPnzJ0xN8TUSehRzyol73DSQx9schss5pNwJWjxliOc0B+o9XzNFx vn4/K1Kd9U4fCRV1IGwSab9tfLbhckcVdPWxISLptYdMCHEdBShL/mutRll1PRqPoL 3d1gcMeaeh9aOMyUe9znmk+uAjV2kr/2y2gWjJhmOjw6RPFpMO/8HoxzU33QB0gvvY D8ZY5HSgTk+5Q== From: Niklas Cassel To: Manivannan Sadhasivam , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Damien Le Moal , Frank Li , Jesper Nilsson , Niklas Cassel , linux-pci@vger.kernel.org Subject: [PATCH v6 6/6] PCI: endpoint: Verify that requested BAR size is a power of two Date: Fri, 13 Dec 2024 15:33:07 +0100 Message-ID: <20241213143301.4158431-14-cassel@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241213143301.4158431-8-cassel@kernel.org> References: <20241213143301.4158431-8-cassel@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1205; i=cassel@kernel.org; h=from:subject; bh=TogfjNWvw13U7UTT/BFwsTkPYIc7m/zcJdIlaNZz+ek=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGNJjXJf8y7DcfO/4cyeOZYV2xyInxS5d934T9+yzB/etU BYQDk1b1VHKwiDGxSArpsji+8Nlf3G3+5TjindsYOawMoEMYeDiFICJTE9hZHhbZbP87CqZZZOc 3ZS3mmcGZa48oDt/fkJJRgbHj0PXNixi+O98znjehClHrbvmPZyqpm1olzN3z+5ZJSZPtJ1iugo 3PmQGAA== X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA When allocating a BAR using pci_epf_alloc_space(), there are checks that round up the size to a power of two. However, there is no check in pci_epc_set_bar() which verifies that the requested BAR size is a power of two. Add a power of two check in pci_epc_set_bar(), so that we don't need to add such a check in each and every PCI endpoint controller driver. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- drivers/pci/endpoint/pci-epc-core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index c69c133701c9..6062677e9ffe 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -622,6 +622,9 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, (epc_features->bar[bar].fixed_size != epf_bar->size)) return -EINVAL; + if (!is_power_of_2(epf_bar->size)) + return -EINVAL; + if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || (flags & PCI_BASE_ADDRESS_SPACE_IO && flags & PCI_BASE_ADDRESS_IO_MASK) ||