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Fri, 13 Dec 2024 08:45:17 -0800 (PST) From: Peter Griffin Date: Fri, 13 Dec 2024 16:44:38 +0000 Subject: [PATCH 1/4] dt-bindings: soc: samsung: exynos-pmu: gs101: add pmu-intr-gen reg region Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-1-c72978f63713@linaro.org> References: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-0-c72978f63713@linaro.org> In-Reply-To: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-0-c72978f63713@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Krzysztof Kozlowski , Lee Jones Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 also requires access to the pmu interrupt generation register region. Update the exynos-pmu bindings documentation to reflect this. Signed-off-by: Peter Griffin --- .../bindings/soc/samsung/exynos-pmu.yaml | 29 +++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 6cdfe7e059a3..5ac4864e4cde 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -73,7 +73,11 @@ properties: - const: syscon reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + maxItems: 2 '#clock-cells': const: 1 @@ -186,6 +190,29 @@ allOf: properties: dp-phy: false + - if: + properties: + compatible: + contains: + enum: + - google,gs101-pmu + then: + properties: + reg: + items: + - description: PMU register region + - description: PMU Interrupt Generation register region + reg-names: + items: + - const: pmu + - const: pmu-intr-gen + else: + properties: + reg: + maxItems: 1 + reg-name: + maxItems: 1 + examples: - | #include From patchwork Fri Dec 13 16:44:39 2024 Content-Type: text/plain; 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Fri, 13 Dec 2024 08:45:18 -0800 (PST) From: Peter Griffin Date: Fri, 13 Dec 2024 16:44:39 +0000 Subject: [PATCH 2/4] dt-bindings: mfd: syscon: allow two reg regions for gs101-pmu Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-2-c72978f63713@linaro.org> References: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-0-c72978f63713@linaro.org> In-Reply-To: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-0-c72978f63713@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Krzysztof Kozlowski , Lee Jones Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA To avoid dtschema warnings allow google,gs101-pmu to have two reg regions. Signed-off-by: Peter Griffin --- I don't really like this patch, but also didn't want to submit the series with a dtschema warning ;-) Possibly a better solution is when Robs patch `mfd: syscon: Allow syscon nodes without a "syscon" compatible` [1] gets updated with a v2, we could remove syscon compatible from gs101.dtsi (an ABI issue). If I understood his patch correctly, it would mean this yaml update would then no longer be required. Let me know your thoughts [1] https://lore.kernel.org/lkml/20241211-syscon-fixes-v1-0-b5ac8c219e96@kernel.org/T/#m5ad1ed5c69f693d2a5cc54342a87fbdf3df756d2 --- Documentation/devicetree/bindings/mfd/syscon-common.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon-common.yaml b/Documentation/devicetree/bindings/mfd/syscon-common.yaml index 451cbad467a3..9cd9739d5e97 100644 --- a/Documentation/devicetree/bindings/mfd/syscon-common.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon-common.yaml @@ -59,6 +59,16 @@ allOf: compatible: minItems: 3 maxItems: 5 + - if: + properties: + compatible: + contains: + const: + - google,gs101-pmu + then: + properties: + reg: + maxItems: 2 additionalProperties: true From patchwork Fri Dec 13 16:44:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13907508 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C61631F12F6 for ; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA These registers are required for cpu hotplug. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 302c5beb224a..93db14e16246 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1393,7 +1393,9 @@ sysreg_apm: syscon@174204e0 { pmu_system_controller: system-controller@17460000 { compatible = "google,gs101-pmu", "syscon"; - reg = <0x17460000 0x10000>; + reg = <0x17460000 0x10000>, + <0x17470000 0x10000>; + reg-names = "pmu", "pmu-intr-gen"; poweroff: syscon-poweroff { compatible = "syscon-poweroff"; From patchwork Fri Dec 13 16:44:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13907509 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E5F01F1308 for ; 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Fri, 13 Dec 2024 08:45:22 -0800 (PST) Received: from gpeter-l.roam.corp.google.com ([145.224.66.83]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43625550523sm53900665e9.7.2024.12.13.08.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 08:45:22 -0800 (PST) From: Peter Griffin Date: Fri, 13 Dec 2024 16:44:41 +0000 Subject: [PATCH 4/4] soc: samsung: exynos-pmu: enable CPU hotplug support for gs101 Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-4-c72978f63713@linaro.org> References: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-0-c72978f63713@linaro.org> In-Reply-To: <20241213-contrib-pg-cpu-hotplug-suspend2ram-fixes-v1-v1-0-c72978f63713@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Krzysztof Kozlowski , Lee Jones Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, willmcvicker@google.com, kernel-team@android.com, Peter Griffin X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Some additional register writes are required when hotplugging CPUs on gs101, without these the system hangs when hotplugging. Specifically a CPU_INFORM register needs to be programmed with a hint value which is used by the EL3 firmware (el3mon) and the pmu-intr-gen registers need to be programmed. With this patch applied, and corresponding DT update CPU hotplug now works as expected. e.g. echo 0 > /sys/devices/system/cpu/cpu6/online echo 1 > /sys/devices/system/cpu/cpu6/online Note: to maintain compatibility with older DTs that didn't specify pmu-intr-gen register region only a warning is issued if the registers can't be mapped, and the old behaviour is maintained. Signed-off-by: Peter Griffin --- drivers/soc/samsung/exynos-pmu.c | 73 ++++++++++++++++++++++++++++- drivers/soc/samsung/exynos-pmu.h | 1 + include/linux/soc/samsung/exynos-regs-pmu.h | 11 +++++ 3 files changed, 84 insertions(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index d8c53cec7f37..68eb4eb3813b 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -6,6 +6,7 @@ // Exynos - CPU PMU(Power Management Unit) support #include +#include #include #include #include @@ -32,6 +33,7 @@ struct exynos_pmu_context { struct device *dev; const struct exynos_pmu_data *pmu_data; struct regmap *pmureg; + void __iomem *pmuintrgen_base; }; void __iomem *pmu_base_addr; @@ -221,7 +223,8 @@ static const struct regmap_config regmap_smccfg = { }; static const struct exynos_pmu_data gs101_pmu_data = { - .pmu_secure = true + .pmu_secure = true, + .pmu_cpuhp = true, }; /* @@ -325,6 +328,52 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct device_node *np, } EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle); +/* + * CPU_INFORM register hint values which are used by + * EL3 firmware (el3mon). + */ +#define CPU_INFORM_CLEAR 0 +#define CPU_INFORM_C2 1 + +static int cpuhp_pmu_online(unsigned int cpu) +{ + void __iomem *base = pmu_context->pmuintrgen_base; + u32 reg; + u32 mask; + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpu), + CPU_INFORM_CLEAR); + + mask = (1 << cpu); + + writel(((0 << cpu) & mask), base + GS101_GRP2_INTR_BID_ENABLE); + + reg = readl(base + GS101_GRP2_INTR_BID_UPEND) & mask; + writel(reg & mask, base + GS101_GRP2_INTR_BID_CLEAR); + + return 0; +} + +static int cpuhp_pmu_offline(unsigned int cpu) +{ + void __iomem *base = pmu_context->pmuintrgen_base; + u32 reg, mask; + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpu), + CPU_INFORM_C2); + + writel((1 << cpu), base + GS101_GRP2_INTR_BID_ENABLE); + + mask = ((1 << cpu) | (1 << (cpu+8))); + + reg = readl(base + GS101_GRP1_INTR_BID_UPEND) & mask; + writel(reg & mask, base + GS101_GRP1_INTR_BID_CLEAR); + + return 0; +} + static int exynos_pmu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -377,6 +426,28 @@ static int exynos_pmu_probe(struct platform_device *pdev) pmu_context->pmureg = regmap; pmu_context->dev = dev; + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_cpuhp) { + + pmu_context->pmuintrgen_base = + devm_platform_ioremap_resource_byname(pdev, "pmu-intr-gen"); + /* + * To maintain support for older DTs that didn't specify pmu-intr-gen + * register region, just issue a warning rather than fail to probe. + */ + if (IS_ERR(pmu_context->pmuintrgen_base)) { + dev_warn(&pdev->dev, + "failed to map pmu-intr-gen registers\n"); + } else { + cpuhp_setup_state(CPUHP_BP_PREPARE_DYN, + "soc/exynos-pmu:prepare", + cpuhp_pmu_online, NULL); + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, + "soc/exynos-pmu:online", + NULL, cpuhp_pmu_offline); + } + } + if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_init) pmu_context->pmu_data->pmu_init(); diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 0a49a2c9a08e..0938bb4fe15f 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -22,6 +22,7 @@ struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; const struct exynos_pmu_conf *pmu_config_extra; bool pmu_secure; + bool pmu_cpuhp; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h index ce1a3790d6fb..0d5a17ea8fb8 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -658,9 +658,20 @@ #define EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION (0x32A8) /* For Tensor GS101 */ +/* PMU ALIVE */ #define GS101_SYSIP_DAT0 (0x810) +#define GS101_CPU0_INFORM (0x860) +#define GS101_CPU_INFORM(cpu) \ + (GS101_CPU0_INFORM + (cpu*4)) #define GS101_SYSTEM_CONFIGURATION (0x3A00) #define GS101_PHY_CTRL_USB20 (0x3EB0) #define GS101_PHY_CTRL_USBDP (0x3EB4) +/* PMU INTR GEN */ +#define GS101_GRP1_INTR_BID_UPEND (0x0108) +#define GS101_GRP1_INTR_BID_CLEAR (0x010c) +#define GS101_GRP2_INTR_BID_ENABLE (0x0200) +#define GS101_GRP2_INTR_BID_UPEND (0x0208) +#define GS101_GRP2_INTR_BID_CLEAR (0x020c) + #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */