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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4361ec75410sm104456185e9.1.2024.12.14.14.04.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Dec 2024 14:04:51 -0800 (PST) From: Ivaylo Ivanov To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] dt-bindings: i2c: exynos5: Add samsung,exynos8895-hsi2c compatible Date: Sun, 15 Dec 2024 00:04:18 +0200 Message-ID: <20241214220419.723100-2-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241214220419.723100-1-ivo.ivanov.ivanov1@gmail.com> References: <20241214220419.723100-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add samsung,exynos8895-hsi2c dedicated compatible for representing I2C of Exynos8895 SoC. Since there are I2C buses that aren't implemented as a part of USIv1 blocks, they only require a single clock. Signed-off-by: Ivaylo Ivanov --- .../devicetree/bindings/i2c/i2c-exynos5.yaml | 26 ++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index cc8bba553..b029be88e 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420 - samsung,exynos5260-hsi2c # Exynos5260 - samsung,exynos7-hsi2c # Exynos7 + - samsung,exynos8895-hsi2c - samsung,exynosautov9-hsi2c - items: - enum: @@ -94,9 +95,28 @@ allOf: - clock-names else: - properties: - clocks: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - samsung,exynos8895-hsi2c + + then: + properties: + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + required: + - clock-names + + else: + properties: + clocks: + maxItems: 1 unevaluatedProperties: false From patchwork Sat Dec 14 22:04:19 2024 Content-Type: text/plain; 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[91.139.201.119]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4361ec75410sm104456185e9.1.2024.12.14.14.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Dec 2024 14:04:53 -0800 (PST) From: Ivaylo Ivanov To: Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] i2c: exynos5: Add support for Exynos8895 SoC Date: Sun, 15 Dec 2024 00:04:19 +0200 Message-ID: <20241214220419.723100-3-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241214220419.723100-1-ivo.ivanov.ivanov1@gmail.com> References: <20241214220419.723100-1-ivo.ivanov.ivanov1@gmail.com> Precedence: bulk X-Mailing-List: linux-samsung-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Exynos8895 functioning logic mostly follows I2C_TYPE_EXYNOS7, but timing and temp calculations are slightly changed according to the following logic: FPCLK / FI2C = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 2 * ((FLT_CYCLE + 3) - (FLT_CYCLE + 3) % (CLK_DIV + 1)) temp := (FPCLK / FI2C) - (FLT_CYCLE + 3) * 2 Signed-off-by: Ivaylo Ivanov --- drivers/i2c/busses/i2c-exynos5.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c index e33001508..8d8ee42ba 100644 --- a/drivers/i2c/busses/i2c-exynos5.c +++ b/drivers/i2c/busses/i2c-exynos5.c @@ -168,6 +168,7 @@ enum i2c_type_exynos { I2C_TYPE_EXYNOS5, I2C_TYPE_EXYNOS7, I2C_TYPE_EXYNOSAUTOV9, + I2C_TYPE_EXYNOS8895, }; struct exynos5_i2c { @@ -240,6 +241,11 @@ static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = { .hw = I2C_TYPE_EXYNOSAUTOV9, }; +static const struct exynos_hsi2c_variant exynos8895_hsi2c_data = { + .fifo_depth = 64, + .hw = I2C_TYPE_EXYNOS8895, +}; + static const struct of_device_id exynos5_i2c_match[] = { { .compatible = "samsung,exynos5-hsi2c", @@ -256,6 +262,9 @@ static const struct of_device_id exynos5_i2c_match[] = { }, { .compatible = "samsung,exynosautov9-hsi2c", .data = &exynosautov9_hsi2c_data + }, { + .compatible = "samsung,exynos8895-hsi2c", + .data = &exynos8895_hsi2c_data }, {}, }; MODULE_DEVICE_TABLE(of, exynos5_i2c_match); @@ -331,6 +340,14 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) * clk_cycle := TSCLK_L + TSCLK_H * temp := (CLK_DIV + 1) * (clk_cycle + 2) * + * In case of HSI2C controllers in Exynos8895 + * FPCLK / FI2C = + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + + * 2 * ((FLT_CYCLE + 3) - (FLT_CYCLE + 3) % (CLK_DIV + 1)) + * + * clk_cycle := TSCLK_L + TSCLK_H + * temp := (FPCLK / FI2C) - (FLT_CYCLE + 3) * 2 + * * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510 * * To split SCL clock into low, high periods appropriately, one @@ -352,11 +369,19 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) * */ t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; - temp = clkin / op_clk - 8 - t_ftl_cycle; + if (i2c->variant->hw == I2C_TYPE_EXYNOS8895) + temp = clkin / op_clk - (t_ftl_cycle + 3) * 2; + else + temp = clkin / op_clk - 8 - t_ftl_cycle; if (i2c->variant->hw != I2C_TYPE_EXYNOS7) temp -= t_ftl_cycle; div = temp / 512; - clk_cycle = temp / (div + 1) - 2; + + if (i2c->variant->hw == I2C_TYPE_EXYNOS8895) + clk_cycle = (temp + ((t_ftl_cycle + 3) % (div + 1)) * 2) / + (div + 1) - 2; + else + clk_cycle = temp / (div + 1) - 2; if (temp < 4 || div >= 256 || clk_cycle < 2) { dev_err(i2c->dev, "%s clock set-up failed\n", hs_timings ? "HS" : "FS"); @@ -491,6 +516,8 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id) switch (i2c->variant->hw) { case I2C_TYPE_EXYNOSAUTOV9: fallthrough; + case I2C_TYPE_EXYNOS8895: + fallthrough; case I2C_TYPE_EXYNOS7: if (int_status & HSI2C_INT_TRANS_DONE) { i2c->trans_done = 1;