From patchwork Mon Dec 16 03:13:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13909148 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86BD31514DC for ; Mon, 16 Dec 2024 03:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318834; cv=none; b=sGzcCyamvbfWu77MH807zFChbTcmyNlO12Syi1UdCF6mUCr+ZrmprT74y2+8HtjykmfHbnTuH6ejOHnpCEGvcPijs/TU9CDy+bmtePyjhAP9qLJP/xqlWi1yTwVknNV48V6btamRA+5zF1TD48aecOf/wDfQ2wPsIOlwz+7rp0s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318834; c=relaxed/simple; bh=t3UDuB/k/6gJH28l6NNeiKh5cTQaX1PP5+VSQRwTTrY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D0/5mGprtnnolL4M1A5iZtFny4xfTldDwJlfrMhwYPx5lYXvDeGUUc50Lr0AQ6Keo+AxokCYeis5tqNE7d7euVasE7Lzo26QtHi//euNHN+KwCaMFQn6X4vUygHoOTTSkm7zHvbYt9zu5RYpHUqoUmDGk681faMmXad9FbwNzks= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=IKjPTUtm; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="IKjPTUtm" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 400842C02A8; Mon, 16 Dec 2024 16:13:49 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1734318829; bh=u8A0pZjwNNzs8FNwLXJeDrO2LOMmvwLBf+tlQXB1tAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IKjPTUtmcaVuMWRp0gpiwPCYUOqm/afvUCZl2cKmfxL2d2o7rcVmsHid3RWUF9DTc igtbdS6jwqPeNca43Kr03Pf2Zu76wxNTK6xrlADGWq4+R3kNuuJyIcKkzWZz4QXPCI cOEEulvbVPB7RE67Ofy2dsTedkSrKW2PkPBOHtIgLANbSUwnhD9kf5vMo8vrsusZtH hgYNYM62tjJaZWLMLO48UaomVtTj5jzqcL+qYu/86omDhRX2lXF/dFqIWzHobsQBRQ T1+ql6ee/3WExZtw0oRx2YIT8lU0VJURA10kH0+lF187oAdJLZOn9Z2hMuGlqcitx5 VTr4sIWqqNvEQ== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 16 Dec 2024 16:13:48 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id E56D413EE7B; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id DF4332803EA; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v2 1/4] dt-bindings: net: Add Realtek MDIO controller Date: Mon, 16 Dec 2024 16:13:43 +1300 Message-ID: <20241216031346.2626805-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> References: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=BNQQr0QG c=1 sm=1 tr=0 ts=675f9aed a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=RZcAm9yDv7YA:10 a=gEfo2CItAAAA:8 a=G3VztrOQQWe42Su9FKoA:9 a=3ZKOabzyN94A:10 a=d8afv_qLQQFTBC2_4BOH:22 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add dtschema for the MDIO controller found in the RTL9300 SoCs. The controller is slightly unusual in that direct MDIO communication is not possible. Instead, the SMI bus and PHY address are associated with a switch port and the port number is used when talking to the PHY. Signed-off-by: Chris Packham Reviewed-by: Conor Dooley --- Notes: Changes in v2: - None .../bindings/net/realtek,rtl9301-mdio.yaml | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml new file mode 100644 index 000000000000..95ed77ff8dcc --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL9300 MDIO Controller + +maintainers: + - Chris Packham + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - const: realtek,rtl9301-mdio + - const: realtek,rtl9301-mdio + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + '^ethernet-phy(@[a-f0-9]+)?': + type: object + $ref: ethernet-phy.yaml# + + properties: + reg: + description: + The MDIO communication on the RTL9300 is abstracted by the switch. At + the software level communication uses the switch port to address the + PHY with the actual MDIO bus and address having been setup via the + realtek,smi-address property. + + realtek,smi-address: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: SMI interface and address for the connected PHY + items: + - description: SMI interface number associated with the port. + - description: SMI address of the PHY for the port. + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mdio@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + realtek,smi-address = <0 1>; + }; + + ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + realtek,smi-address = <1 1>; + }; + }; From patchwork Mon Dec 16 03:13:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13909151 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 972221547C9 for ; Mon, 16 Dec 2024 03:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318836; cv=none; b=Q6Ns1tiXysh9J/x/ocOtNYso/dMIRjAt6wbvx/BAt9qzpAI/UC03/lvpUMgMvW2wZPWP+4LSqfZYdg2txWMeRgJwzaHapDwtTK0XurMq+hA8vB7s/6BEhbv11WXNZOIEf3AEeHpFelyV+/vnCsUJG/pOtZTujDP8DPPLQydtwNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318836; c=relaxed/simple; bh=EZMxsaSZyVTLl+wyd+Suo9rEvaWxLJNZbUuoR1n9dLQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=s8K4SSfvcn1kktQih1QvAr4bSsefnmIuM0+LYgASLNTQEjytJXbTv9hhyVCRfulvWZ7RpqkgFWwXcMUbpNqCzzriESU6IXhudsGZftbhoWR9RWtFOWNwAcBAn3LnqZDVxbQHdtlndiyJlnLHBMiTL+ZvQ7WQEMjFwy5sq3NImQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=QU4Z7gzu; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="QU4Z7gzu" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6D0702C06AE; Mon, 16 Dec 2024 16:13:49 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1734318829; bh=ija5y22i7nvrG7FYKFouDM3FeHuFJwf9xq2lkRzkIu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QU4Z7gzu5duX/ec9QI26WXFEswSBoXDvU9ERJ+T6+3LUxHrbA8Sf25OFH77LJjumN +e5YLXkvJhn7YosxBfDDSActqYB5agQCAMe+aBKh1Xj033xCwVwDG6zjkM8x6gLMvh HWUBvj/oOJ9Z8zzaQ5yTTdaBIz6cnFHhSO/agQWt7iF2l0dI29z0dj4IqIPN/JEhh2 Sw5+Q9mFsHdLPkVipL/mhqBQevHEnTwjTmH7M6t/IgGD54BOZN1jOhrzBHPcb9+Mlc c4M9aT2VLfczYAMhw0rnmUjGhza8hmMal7UbNEZvHlRVZqZlUuROWygP8FraAdgkTG vKNqjEB9S3gcQ== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 16 Dec 2024 16:13:49 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id E6D5313EE87; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E1452280E23; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v2 2/4] dt-bindings: mfd: Add MDIO interface to rtl9301-switch Date: Mon, 16 Dec 2024 16:13:44 +1300 Message-ID: <20241216031346.2626805-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> References: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=BNQQr0QG c=1 sm=1 tr=0 ts=675f9aed a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=RZcAm9yDv7YA:10 a=0DcZ6JciK6r0_laEW2MA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat The MDIO controller is part of the switch on the RTL9300 family of devices. Add a $ref to the mfd binding for these devices. Signed-off-by: Chris Packham Acked-by: Conor Dooley --- Notes: Changes in v2: - None .../bindings/mfd/realtek,rtl9301-switch.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml index f053303ab1e6..eeb08e7435fa 100644 --- a/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml +++ b/Documentation/devicetree/bindings/mfd/realtek,rtl9301-switch.yaml @@ -41,6 +41,9 @@ patternProperties: 'i2c@[0-9a-f]+$': $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# + 'mdio@[0-9a-f]+$': + $ref: /schemas/net/realtek,rtl9301-mdio.yaml# + required: - compatible - reg @@ -110,5 +113,17 @@ examples: }; }; }; + + mdio0: mdio@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + realtek,smi-address = <0 1>; + }; + }; }; From patchwork Mon Dec 16 03:13:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13909149 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A04F153838 for ; Mon, 16 Dec 2024 03:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318834; cv=none; b=rJjMSxqKx9vkqWm5rIug8ABBFWQ8sD73mP1Bn07t37M3xOaZWHmmSvXuMbkS313wXnK8Yu0ZFYXOrIXxhOMJqUkLtJ7bGVVphxaYAmFMZ+nohUFWchxWipc/jY8nvF/rJ+uz6mRIr0UrFS9z6I3L5tjmi6tbFX3sEaKA5n3AFiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318834; c=relaxed/simple; bh=4YuwduCfBsNI/ZZRIrKfSByqrHYRKxO8YlQow50f150=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ah2W1tOyBqESvDM9BkSAj3nh6qyWmEbAZje4orZmf53zsc4/6zjnmz6+xIOy3mBQXebphE4qZiLn8s/r3R/dQ4VzyNx0/Nm3dG/u3Qp3J3Km/J98oMHAiycq8wHKfygwOSyk/qGFxaciCtgktUjdxHWa1SCEF+LqqljzsDeyFyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=zH79mazP; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="zH79mazP" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 538262C03C9; Mon, 16 Dec 2024 16:13:49 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1734318829; bh=xtR+AxlzuLdejKgbyVaUoBSVjOifbyU2B/fA9f1XLhU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zH79mazPK6IxSi0zOeiJNDHH2AYo9ZsR5SPirLAoqE6qJY+UV4M181q8K48rRUvuG ITskolipC4ZlDlMmU590a9xw0Ioi3/KxnXwDdqH4Shw8tDFNlEX6i0XGkfPnTrCKF7 S+dPMSdUjX+VPHDeBh3m/YyJ1fgzyNQ1Ja3LuWNx95ZpRlSb2pzgyr0UkcSUyc5rsd z5iTgBghTZLlxpACzC2Erb6Z5zYbcNYlhvt9gWG9IRZLQtNDKi1D5d5UtqmqJ+86tH 4R5sBsuJY8txGDNbUrj5U+OShjr2FyNjnr6YblarnNuWtHQUY1W2F1uzzXzs8JT6Wx TI+9xuXu2FEoA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 16 Dec 2024 16:13:49 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id EA5F213EE9B; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id E72302803EA; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v2 3/4] mips: dts: realtek: Add MDIO controller Date: Mon, 16 Dec 2024 16:13:45 +1300 Message-ID: <20241216031346.2626805-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> References: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=BNQQr0QG c=1 sm=1 tr=0 ts=675f9aed a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=RZcAm9yDv7YA:10 a=k4-7ynMye8UXlDNHH0IA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add a device tree node for the MDIO controller on the RTL9300 chips. Signed-off-by: Chris Packham --- Notes: Changes in v2: - None arch/mips/boot/dts/realtek/rtl930x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi index 17577457d159..5f74d121ce84 100644 --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi @@ -57,6 +57,14 @@ i2c1: i2c@388 { #size-cells = <0>; status = "disabled"; }; + + mdio0: mdio@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; From patchwork Mon Dec 16 03:13:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 13909147 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86ADC1422B8 for ; Mon, 16 Dec 2024 03:13:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.36.163.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318834; cv=none; b=RC99bHnkM1FKJ+ntXfLTna9nk6u6WKM7wtU2+j5dJ00KlQuy9wAwBZNPjpn3ITo/BWvFKIyUws2XBCow+/Cf95Mqy3hkqd2EFLLMJypQH9RXSTuDMG4FFQXI5gGSM41zHEcYdFsbCrsASb/RjD20uc9TJjkz1K8PEHuAf7xX9TE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734318834; c=relaxed/simple; bh=dTxUYroMkkS6yYemGfRDl3QZZF8yWEGI0ldNnuZpgB0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aTKraBH2KoJ2cj+aAIdQzhSAHnVxpzsomIT5OJ7eyqya/Sqwf2NAER81gTkmTKQItkNQTufKMvf1zC2ezXw2unBOXi5LrKdct+wqnK2AOOYLNHUPYROlR3Zg0n/ySJFWCyE0MhXv9pW/HM+HDBZ6TG5+Mu+dWdl5iprWaPkRsW4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz; spf=pass smtp.mailfrom=alliedtelesis.co.nz; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b=ot8+dGVh; arc=none smtp.client-ip=202.36.163.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=alliedtelesis.co.nz Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="ot8+dGVh" Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6253B2C04EA; Mon, 16 Dec 2024 16:13:49 +1300 (NZDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1734318829; bh=dAFqooAZLwvN37SBMg+rsgoIlHkI6A6yh+3k1eVyeJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ot8+dGVhy2xDkIe6Wz4Fn0nI6GztPKBq7X5Hn+pZVSSKgyR7IrV+QXvKH3zsyUgT4 25WuR//1ggXmv+MCdfH/IKjwN+X7WYFx1Ft+bl4a5jYAf2GIFejJr06Ca7TzJHF+T+ Ml5zHWHqJNOnPzZHo8sPFcd0XC28XBEJeZoo0fjqBrEH/wJ3CH0W3TxWbVR3eN2YlF wU3Iq8tcAjJjW83xWRCnIQDaZr3mczp3BHS2VVBXWHdLE7HOYGBQnUvaQ9TncYDEX6 /Pp+plJdS0D5TEGjm/t4/GQxb5QGMAJlzcinsnM1T8+XwtaZzLDisfyQjXEXoxiek7 Yv+uo+6AxEP/Q== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Mon, 16 Dec 2024 16:13:49 +1300 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id EEC3013EE9C; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id EBA452803EA; Mon, 16 Dec 2024 16:13:48 +1300 (NZDT) From: Chris Packham To: lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, tsbogend@alpha.franken.de, hkallweit1@gmail.com, linux@armlinux.org.uk, markus.stockhausen@gmx.de Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-mips@vger.kernel.org, Chris Packham Subject: [PATCH v2 4/4] net: mdio: Add RTL9300 MDIO driver Date: Mon, 16 Dec 2024 16:13:46 +1300 Message-ID: <20241216031346.2626805-5-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> References: <20241216031346.2626805-1-chris.packham@alliedtelesis.co.nz> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.4 cv=BNQQr0QG c=1 sm=1 tr=0 ts=675f9aed a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=RZcAm9yDv7YA:10 a=PLFZzS6RjvMAOK3DgDUA:9 a=3ZKOabzyN94A:10 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Add a driver for the MDIO controller on the RTL9300 family of Ethernet switches with integrated SoC. There are 4 physical SMI interfaces on the RTL9300 but access is done using the switch ports so a single MDIO bus is presented to the rest of the system. Signed-off-by: Chris Packham --- Notes: Changes in v2: - Add clause 22 support - Remove commented out code - Formatting cleanup - Set MAX_PORTS correctly for MDIO interface - Fix off-by-one error in pn check drivers/net/mdio/Kconfig | 7 + drivers/net/mdio/Makefile | 1 + drivers/net/mdio/mdio-realtek-rtl.c | 341 ++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/net/mdio/mdio-realtek-rtl.c diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig index 4a7a303be2f7..0c6240c4a7e9 100644 --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig @@ -185,6 +185,13 @@ config MDIO_IPQ8064 This driver supports the MDIO interface found in the network interface units of the IPQ8064 SoC +config MDIO_REALTEK_RTL + tristate "Realtek RTL9300 MDIO interface support" + depends on MACH_REALTEK_RTL || COMPILE_TEST + help + This driver supports the MDIO interface found in the Realtek + RTL9300 family of Ethernet switches with integrated SoC. + config MDIO_REGMAP tristate help diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile index 1015f0db4531..2cd8b491f301 100644 --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o +obj-$(CONFIG_MDIO_REALTEK_RTL) += mdio-realtek-rtl.o obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o diff --git a/drivers/net/mdio/mdio-realtek-rtl.c b/drivers/net/mdio/mdio-realtek-rtl.c new file mode 100644 index 000000000000..a13b84279138 --- /dev/null +++ b/drivers/net/mdio/mdio-realtek-rtl.c @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MDIO controller for RTL9300 switches with integrated SoC. + * + * The MDIO communication is abstracted by the switch. At the software level + * communication uses the switch port to address the PHY with the actual MDIO + * bus and address having been setup via the realtek,smi-address property. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMI_GLB_CTRL 0x000 +#define GLB_CTRL_INTF_SEL(intf) BIT(16 + (intf)) +#define SMI_PORT0_15_POLLING_SEL 0x008 +#define SMI_ACCESS_PHY_CTRL_0 0x170 +#define SMI_ACCESS_PHY_CTRL_1 0x174 +#define PHY_CTRL_RWOP BIT(2) +#define PHY_CTRL_TYPE BIT(1) +#define PHY_CTRL_CMD BIT(0) +#define PHY_CTRL_FAIL BIT(25) +#define SMI_ACCESS_PHY_CTRL_2 0x178 +#define SMI_ACCESS_PHY_CTRL_3 0x17c +#define SMI_PORT0_5_ADDR_CTRL 0x180 + +#define MAX_PORTS 28 +#define MAX_SMI_BUSSES 4 +#define MAX_SMI_ADDR 0x1f + +struct realtek_mdio_priv { + struct regmap *regmap; + u8 smi_bus[MAX_PORTS]; + u8 smi_addr[MAX_PORTS]; + bool smi_bus_isc45[MAX_SMI_BUSSES]; + u32 reg_base; +}; + +static int realtek_mdio_wait_ready(struct realtek_mdio_priv *priv) +{ + struct regmap *regmap = priv->regmap; + u32 reg_base = priv->reg_base; + u32 val; + + return regmap_read_poll_timeout(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 500); +} + +static int realtek_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum) +{ + struct realtek_mdio_priv *priv = bus->priv; + struct regmap *regmap = priv->regmap; + u32 reg_base = priv->reg_base; + u32 val; + int err; + + err = realtek_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, phy_id << 16); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + regnum << 20 | 0x1f << 15 | 0xfff << 3 | PHY_CTRL_CMD); + if (err) + return err; + + err = realtek_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_read(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return val & 0xffff; +} + +static int realtek_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value) +{ + struct realtek_mdio_priv *priv = bus->priv; + struct regmap *regmap = priv->regmap; + u32 reg_base = priv->reg_base; + u32 val; + int err; + + err = realtek_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_0, BIT(phy_id)); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, value << 16); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + regnum << 20 | 0x1f << 15 | 0xfff << 3 | PHY_CTRL_RWOP | PHY_CTRL_CMD); + if (err) + return err; + + err = regmap_read_poll_timeout(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int realtek_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum) +{ + struct realtek_mdio_priv *priv = bus->priv; + struct regmap *regmap = priv->regmap; + u32 reg_base = priv->reg_base; + u32 val; + int err; + + err = realtek_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, phy_id << 16); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_3, + dev_addr << 16 | (regnum & 0xffff)); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_TYPE | PHY_CTRL_CMD); + if (err) + return err; + + err = realtek_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_read(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, &val); + if (err) + return err; + + return val & 0xffff; +} + +static int realtek_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr, + int regnum, u16 value) +{ + struct realtek_mdio_priv *priv = bus->priv; + struct regmap *regmap = priv->regmap; + u32 reg_base = priv->reg_base; + u32 val; + int err; + + err = realtek_mdio_wait_ready(priv); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_0, BIT(phy_id)); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_2, value << 16); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_3, + dev_addr << 16 | (regnum & 0xffff)); + if (err) + return err; + + err = regmap_write(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + PHY_CTRL_RWOP | PHY_CTRL_TYPE | PHY_CTRL_CMD); + if (err) + return err; + + err = regmap_read_poll_timeout(regmap, reg_base + SMI_ACCESS_PHY_CTRL_1, + val, !(val & PHY_CTRL_CMD), 10, 100); + if (err) + return err; + + if (val & PHY_CTRL_FAIL) + return -ENXIO; + + return 0; +} + +static int realtek_mdiobus_init(struct realtek_mdio_priv *priv) +{ + u32 glb_ctrl_mask = 0, glb_ctrl_val = 0; + struct regmap *regmap = priv->regmap; + u32 reg_base = priv->reg_base; + u32 port_addr[5] = { 0 }; + u32 poll_sel[2] = { 0 }; + int i, err; + + /* Associate the port with the SMI interface and PHY */ + for (i = 0; i < MAX_PORTS; i++) { + int pos; + + if (priv->smi_bus[i] > 3) + continue; + + pos = (i % 6) * 5; + port_addr[i / 6] |= priv->smi_addr[i] << pos; + + pos = (i % 16) * 2; + poll_sel[i / 16] |= priv->smi_bus[i] << pos; + } + + /* Put the interfaces into C45 mode if required */ + for (i = 0; i < MAX_SMI_BUSSES; i++) { + if (priv->smi_bus_isc45[i]) { + glb_ctrl_mask |= GLB_CTRL_INTF_SEL(i); + glb_ctrl_val |= GLB_CTRL_INTF_SEL(i); + } + } + + err = regmap_bulk_write(regmap, reg_base + SMI_PORT0_5_ADDR_CTRL, + port_addr, 5); + if (err) + return err; + + err = regmap_bulk_write(regmap, reg_base + SMI_PORT0_15_POLLING_SEL, + poll_sel, 2); + if (err) + return err; + + err = regmap_update_bits(regmap, reg_base + SMI_GLB_CTRL, + glb_ctrl_mask, glb_ctrl_val); + if (err) + return err; + + return 0; +} + +static int realtek_mdiobus_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct realtek_mdio_priv *priv; + struct fwnode_handle *child; + struct mii_bus *bus; + int err; + + bus = devm_mdiobus_alloc_size(dev, sizeof(*priv)); + if (!bus) + return -ENOMEM; + + bus->name = "Reaktek Switch MDIO Bus"; + bus->read = realtek_mdio_read_c22; + bus->write = realtek_mdio_write_c22; + bus->read_c45 = realtek_mdio_read_c45; + bus->write_c45 = realtek_mdio_write_c45; + bus->parent = dev; + priv = bus->priv; + + priv->regmap = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + err = device_property_read_u32(dev, "reg", &priv->reg_base); + if (err) + return err; + + snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); + + device_for_each_child_node(dev, child) { + u32 pn, smi_addr[2]; + + err = fwnode_property_read_u32(child, "reg", &pn); + if (err) + return err; + + if (pn >= MAX_PORTS) + return dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn); + + err = fwnode_property_read_u32_array(child, "realtek,smi-address", smi_addr, 2); + if (err) { + smi_addr[0] = 0; + smi_addr[1] = pn; + } + + if (smi_addr[0] > MAX_SMI_BUSSES) + return dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", + smi_addr[0]); + + if (smi_addr[1] > MAX_SMI_ADDR) + return dev_err_probe(dev, -EINVAL, "illegal smi addr %d\n", smi_addr[1]); + + if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45")) + priv->smi_bus_isc45[smi_addr[0]] = true; + + priv->smi_bus[pn] = smi_addr[0]; + priv->smi_addr[pn] = smi_addr[1]; + } + + err = realtek_mdiobus_init(priv); + if (err) + return dev_err_probe(dev, err, "failed to initialise MDIO bus controller\n"); + + err = devm_of_mdiobus_register(dev, bus, dev->of_node); + if (err) + return dev_err_probe(dev, err, "cannot register MDIO bus\n"); + + return 0; +} + +static const struct of_device_id realtek_mdio_ids[] = { + { .compatible = "realtek,rtl9301-mdio" }, + { .compatible = "realtek,rtl9302b-mdio" }, + { .compatible = "realtek,rtl9302c-mdio" }, + { .compatible = "realtek,rtl9303-mdio" }, + {} +}; +MODULE_DEVICE_TABLE(of, realtek_mdio_ids); + +static struct platform_driver rtl9300_mdio_driver = { + .probe = realtek_mdiobus_probe, + .driver = { + .name = "mdio-rtl9300", + .of_match_table = realtek_mdio_ids, + }, +}; + +module_platform_driver(rtl9300_mdio_driver); + +MODULE_DESCRIPTION("RTL9300 MDIO driver"); +MODULE_LICENSE("GPL");