From patchwork Mon Dec 16 17:56:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910143 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4360206F09; Mon, 16 Dec 2024 17:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371815; cv=none; b=QIHb6hbnnd7DYUhfcZsB0O2eryEQGr2WrW2NT3eic2wJV9nDoExokqaDODTpeV+xPK+4ADvrwInoj0kewHYUAy5B4RUnSi0qrL82AIcmfLRDM9qaBXAjzTfdtIwYM+5LX2WfIC6YnRL9UhENML04RmmwJ53SOfA75F8N+eQPzaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371815; c=relaxed/simple; bh=6kTJno/nt11ujNvZctMxK8UbaiHyzJnwfjvF5S4R/Mo=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=n182t9AsCSDynfESPvhT3RtTb9rf9NATn0ou+thLT3FLyMnFkxFNKPKLhmObTl3+6y7xqfJJ0prAhZN8GypghGWlIFN4eUH6ahigCYlf7gGCQNb6cz5jE9ltwjssYl7JmaALO4m/4/uQ7fUSZgChDiDiDDQYFtvXy1rNE/ljY6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MTp0uK0R; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MTp0uK0R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371814; x=1765907814; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=6kTJno/nt11ujNvZctMxK8UbaiHyzJnwfjvF5S4R/Mo=; b=MTp0uK0RX4TTZWXCViZsFktyUzn5lXg1zGV1yK30Xjazx2utkdaecUCP NkIlGe6R7Kqeey8WNLXW71azmL7Hk2ioPCXbSrt9ALqnlZgxBQs4zfk0D 0BYrEV5CGUtmc3V4RXmYveDEIQ7lXHVnbWQMmyQGQPcriWqvGWX/p+d5z T7yOmEa6rsnTAZMYr8txXDczfQinI3ejVr7ebwXuuoSZrCyOfQSNKZ7nw flC8Q/eOUh1Lap9GfuSQSbH7t/5ygzmx6Hc7VM2X7ZkUYca+OXTCktQao lrXrAldWbD3GG/7GKEw7/E3/hyxrHfmTSwy5H/BezuBQ8iYVQUYkEQ66Z w==; X-CSE-ConnectionGUID: Z1MVKtY6RcSaT0nrC84lLg== X-CSE-MsgGUID: IYVs1/7yQPKO9n+PdX9ejw== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="45465706" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="45465706" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:56:53 -0800 X-CSE-ConnectionGUID: rMD2mwsAQ5CJigKmW8Dfgw== X-CSE-MsgGUID: JGmNdwIAQAGu8JXoRMKY6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="97309279" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:56:50 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , Mika Westerberg , =?utf-8?q?Ilpo_J=C3=A4rv?= =?utf-8?q?inen?= , linux-kernel@vger.kernel.org Subject: [PATCH 01/25] PCI: Remove add_align overwrite unrelated to size0 Date: Mon, 16 Dec 2024 19:56:08 +0200 Message-Id: <20241216175632.4175-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The commit 566f1dd52816 ("PCI: Relax bridge window tail sizing rules") relaxed bridge window tail alignment rule for the non-optional part (size0, no add_size/add_align). The change, however, also overwrite add_align that is only related to case where optional size1 related entry is added into realloc head. Correct this by removing the add_align overwrite. Fixes: 566f1dd52816 ("PCI: Relax bridge window tail sizing rules") Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 5e00cecf1f1a..d92832e1f4a1 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1149,7 +1149,6 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, min_align = 1ULL << (max_order + __ffs(SZ_1M)); min_align = max(min_align, win_align); size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), win_align); - add_align = win_align; pci_info(bus->self, "bridge window %pR to %pR requires relaxed alignment rules\n", b_res, &bus->busn_res); } From patchwork Mon Dec 16 17:56:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910144 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 438ED2066E0; Mon, 16 Dec 2024 17:57:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371825; cv=none; b=s+ldoxMkjaQMkxfuacakx+orkUUbUflFUCvNY7kV+gZIQdROLY6z4/Gik8cfOAYe2lEFq/L8IEI7u6ZMm5lqLtSw33ANCOrtx9UCFDW1bQtrAELdIektK9buzpXGoFRH1F4svB0uIRKqTb6Dg5bewi0Cj/NvcrLSvvUFc2PHSvE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371825; c=relaxed/simple; bh=h+FgumeOC/q2PKTlkJhvmfVs/+GxY2pDU60CX54A8K4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=erdwTvuK9Kiny8VAlcu4mqVon3fc3wlbT3aJ7aUPOPLUCcX1h5klRYt3nirUXgHM4utLZxbglWTKwL4AeaEef7PnPPQO3OvBJXq54PNrbgPEKnkfKmD6yv/VTSmRAAeVB32+1WhIptoInxN1bLQih6A/TQ5Qor8XE4k6r6MP1OI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a1UBBTyw; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a1UBBTyw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371823; x=1765907823; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h+FgumeOC/q2PKTlkJhvmfVs/+GxY2pDU60CX54A8K4=; b=a1UBBTywgyBKHL+x1e1zOWVPbxQpWTQq9aHugHrRpHm4QKrDzisk2gZh +RCJLVMZXFOsPmSW9U4nmaYNn1IANs3vUyt/P0fGHOOYT82Qb0EBPN2JC o4w/PM6ztX17e7r+DP5zOAiPFJMvLZdgJM2p3QOX4qFJWnf5MBGQM9VlI WxStp/NSOFr+z7E2ZDlbZ9JT0fZFhPGmk0G95er7rjFV4NAZxMSJgYEUy 0FZHXiWb0yITXXymITRyEivOl6E/ssA8r8e9jwZLi9IdhWwRWmjWCQ3Ip M2eVbYklIyR/cz56Lf5mIolltBsVV9p4Fk4L7s/VulCVxRhBX0JE7bV78 g==; X-CSE-ConnectionGUID: WeVP3ZP6QBST9qV1uTUIbw== X-CSE-MsgGUID: wpKBCj6iRyiH3Ic1AoYwTg== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="45465713" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="45465713" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:02 -0800 X-CSE-ConnectionGUID: MzE7bZkzQo+EA0RxkbCPxQ== X-CSE-MsgGUID: k/bM3eEFRcu4jmxFTvIzoQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="97309333" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:56:58 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 02/25] PCI: size0 is unrelated to add_align Date: Mon, 16 Dec 2024 19:56:09 +0200 Message-Id: <20241216175632.4175-3-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The commit 566f1dd52816 ("PCI: Relax bridge window tail sizing rules") relaxed bridge window tail alignment rule for the non-optional part (size0, no add_size/add_align). The required alignment given for pbus_upstream_space_available(), however, was add_align which relates only to size1 alignment. As pbus_upstream_space_available() only selects between normal and relaxed tail alignment of the bridge window, the different alignment only makes relaxed tail alignment to be used more often than what was intended which should be harmless because relaxed tail alignment itself should work in all cases. For consistency, change pbus_upstream_space_available() call to use min_align which is the alignment that is going to be used for the bridge window in the case where size0 sized allocation is attempted. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index d92832e1f4a1..09c275f8d088 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1145,7 +1145,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, if (bus->self && size0 && !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type, - size0, add_align)) { + size0, min_align)) { min_align = 1ULL << (max_order + __ffs(SZ_1M)); min_align = max(min_align, win_align); size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), win_align); From patchwork Mon Dec 16 17:56:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910145 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE5492066E0; Mon, 16 Dec 2024 17:57:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371831; cv=none; b=SJRUZJvylEW3CpCSmQyyMkEgV7xfFYypExNbpq2sP4sHHsmIwsJo4F2QOrJ7a07CQD0wYWBL+WX24yr6Y+TXuMRKPQPkrQagYVG62OmYozZLtGrsCbY/c7gsS73x31aHUYwSe7Z9LWePyPBrWsI6pn6r48HZGa1iEBbHv2AVgh8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371831; c=relaxed/simple; bh=7QpAk4U4dEoeFYRN5VbFA6twq16iBTBhGQ2Jo7UTpjU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Hdn5JAcbwV/BJ/YSlcwVaLM0PC8uvZKOuQ1EVL834J9FrmqgjTpQUoynea4+iuxqyZcK+2DsZKMQKiZUEYOJNN3M2kWA5mmE4gZ106eig0wfKBlVGBDXNh2oNT4Tx3ilmaRUQdWlh+vpxz10ES9DVV/VZ5oMFd/GSCTq7D+5aC0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=j1CEVvI/; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="j1CEVvI/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371829; x=1765907829; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7QpAk4U4dEoeFYRN5VbFA6twq16iBTBhGQ2Jo7UTpjU=; b=j1CEVvI/9Xar15r/ufsP+YPxatHvSRffahDmdylUHuHoxQAjiAEyB+Tn He8ed7ubkogeb3nwmpWS1jecMMAVodYHwZWVjOiWERfla2nCsY7tn4hPX f8ONySgHtR1DxCctZImnUwTUWUpBKi8hguMmXu16oilroYnIDZ/qpxfah SXi/FN0GW3mj7pOp9u0mCflisQJv1oRE4NyxB8qiPePueQmWuCDDvydvQ sO/0fqViC65z380EuoR6RRIM5uenK1Uk6dDHNaVZV3gQajL0ks+ea0Uxu OGUcNKlE6xm5aEsVlYBv8cPGIaeu7iIQ9RpAWK82HEqb9WXiOOLYLW4aq A==; X-CSE-ConnectionGUID: H6BwEfqXRX2YJXHFlHIruw== X-CSE-MsgGUID: VNwkBbMNQ6mGoe9AHGburg== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="45465722" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="45465722" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:09 -0800 X-CSE-ConnectionGUID: 9JJd7Z5xSXS31r/tyzD5Yw== X-CSE-MsgGUID: QQ0f7n+ORyuXAV1rVgBkBQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="97309411" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:06 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 03/25] PCI: Simplify size1 assignment logic Date: Mon, 16 Dec 2024 19:56:10 +0200 Message-Id: <20241216175632.4175-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In pbus_size_io() and pbus_size_mem(), a complex ?: operation is performed to set size1 which becomes easier to read when decomposed. In the case of pbus_size_mem(), simply initializing size1 to zero ensures the size1 checks work as expected. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 09c275f8d088..7f4680a23c13 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -927,9 +927,14 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, size0 = calculate_iosize(size, min_size, size1, 0, 0, resource_size(b_res), min_align); - size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 : - calculate_iosize(size, min_size, size1, add_size, children_add_size, - resource_size(b_res), min_align); + + size1 = size0; + if (realloc_head && (add_size > 0 || children_add_size > 0)) { + size1 = calculate_iosize(size, min_size, size1, add_size, + children_add_size, resource_size(b_res), + min_align); + } + if (!size0 && !size1) { if (bus->self && (b_res->start || b_res->end)) pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n", @@ -1058,7 +1063,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, struct list_head *realloc_head) { struct pci_dev *dev; - resource_size_t min_align, win_align, align, size, size0, size1; + resource_size_t min_align, win_align, align, size, size0, size1 = 0; resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */ int order, max_order; struct resource *b_res = find_bus_resource_of_type(bus, @@ -1153,9 +1158,11 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, b_res, &bus->busn_res); } - size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? 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This can manifest, e.g., as a failure to resize a BAR back to its original size after it was first shrunk when device has a VF BAR resource because the bridge window (size1) is enlarged beyond what is strictly required to fit the downstream resources. Allow using relaxed bridge window tail sizing rules also with the optional resources (size1) so that the remove/realloc cycle during BAR resize (smaller and back to the original size) does not fail unexpectedly due to sudden increase in bridge window size demand. Move also add_align calculation into more logical place next to size1 assignment as they are strongly related to each other. Fixes: 566f1dd52816 ("PCI: Relax bridge window tail sizing rules") Reported-by: Michał Winiarski Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 7f4680a23c13..31f051cdac68 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1146,7 +1146,6 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, min_align = calculate_mem_align(aligns, max_order); min_align = max(min_align, win_align); size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align); - add_align = max(min_align, add_align); if (bus->self && size0 && !pbus_upstream_space_available(bus, mask | IORESOURCE_PREFETCH, type, @@ -1159,8 +1158,21 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, } if (realloc_head && (add_size > 0 || children_add_size > 0)) { + add_align = max(min_align, add_align); size1 = calculate_memsize(size, min_size, add_size, children_add_size, resource_size(b_res), add_align); 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a="57250866" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="57250866" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:25 -0800 X-CSE-ConnectionGUID: yysNd/oMQd+dGFvwKGtUig== X-CSE-MsgGUID: rMbAnVoFQaGWsz1/whtTpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="101418741" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:22 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 05/25] PCI: Fix old_size lower bound in calculate_iosize() too Date: Mon, 16 Dec 2024 19:56:12 +0200 Message-Id: <20241216175632.4175-6-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The commit 903534fa7d30 ("PCI: Fix resource double counting on remove & rescan") fixed double counting of mem resources because of old_size being applied too early. Fix a similar counting bug on the io resource side. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 31f051cdac68..ca544fb83700 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -814,11 +814,9 @@ static resource_size_t calculate_iosize(resource_size_t size, size = (size & 0xff) + ((size & ~0xffUL) << 2); #endif size = size + size1; - if (size < old_size) - size = old_size; - size = ALIGN(max(size, add_size) + children_add_size, align); - return size; + size = max(size, add_size) + children_add_size; + return ALIGN(max(size, old_size), align); } static resource_size_t calculate_memsize(resource_size_t size, From patchwork Mon Dec 16 17:56:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910148 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B13C20765E; Mon, 16 Dec 2024 17:57:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371858; cv=none; b=ZX6nNVLX9imqcSXua++tjFNFB7tjg+IZQ3CP3KtnFxjTC087E6DZ393TsZY38qOSZJdYWi8nnazGIUH+Qgn9rIy2R5sZJVj0gUOTy0afs8RRl/i9urFOIQEfmzJ2xH5jqCZSdXt2Kp7pjRHCDelivAq4D7MNK1PfUfqHS+SDvB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371858; c=relaxed/simple; bh=0cS8QYl05pYZeyUF+nQ9DcYCIw9aTu3c3ij04mOXpns=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=L3LZnkaLM4E4kRgZpT27RhKW38fpGgfEClF1rX1WdNuFqbDmoMzR1nhjMrLmLaFXd3VcPSCmYQM1xB9tMqlQ6qB4l3tr6LC6F9jgcprltV+2YJOx8HyuaKTb0byT2AXcN7kL9Jwqs/awYqukVtEVXYX/eXDQxPWNGn7yFwJNdq8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fK6JDjdC; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fK6JDjdC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371857; x=1765907857; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0cS8QYl05pYZeyUF+nQ9DcYCIw9aTu3c3ij04mOXpns=; b=fK6JDjdC1uSAyk65FJu2kYvaL9QmtA2RUZ5OhQQR2Ts9+YJhS/D6AAfk wmiipdaUc3z5K6leabRCnmoxkXiyIifP/IaSg/pah58MkAFqnXB5LuXsp 025RjzXcVww3V2NUI43EUguk6XhD3F3dVasy0+4959/n7GrftLJxqj+yL 3gHWue+vut1aQCWpb2/seaqDpGxxHgKd7aG6o1q6oU9H1gJst0zuOVQYq dDhWWYbsYCvMmCRpKsx+wBZrSvDpT26UYY1ZhljWNPoFfFiSMqys5UrmG tsONnlH3BgXbKbwMMND1eFJD+OLUBimbcsXYwtnBmydrSI0RoHmJB/ezk Q==; X-CSE-ConnectionGUID: oC8B1LQPRju7e+RYJQLNwA== X-CSE-MsgGUID: hDksGtxMSMmAjlXsvL3LTw== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="57250877" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="57250877" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:37 -0800 X-CSE-ConnectionGUID: 24mIv8ViTh2KLAgsT0lgvA== X-CSE-MsgGUID: ZiEt2jPoR7+qPYuyBK2ORw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="101418801" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:33 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 06/25] PCI: Use SZ_* instead of literals in setup-bus.c Date: Mon, 16 Dec 2024 19:56:13 +0200 Message-Id: <20241216175632.4175-7-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Convert literals in setup-bus.c to SZ_* defines that make the size more human readable. As the code is now self-explanatory, the comments about the size can be eliminated. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ca544fb83700..303c4fbf2d14 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -841,9 +841,9 @@ resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus, return 1; } -#define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */ -#define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */ -#define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */ +#define PCI_P2P_DEFAULT_MEM_ALIGN SZ_1M +#define PCI_P2P_DEFAULT_IO_ALIGN SZ_4K +#define PCI_P2P_DEFAULT_IO_ALIGN_1K SZ_1K static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type) { @@ -908,7 +908,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, continue; r_size = resource_size(r); - if (r_size < 0x400) + if (r_size < SZ_1K) /* Might be re-aligned for ISA */ size += r_size; else From patchwork Mon Dec 16 17:56:14 2024 Content-Type: text/plain; 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16 Dec 2024 09:57:41 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 07/25] PCI: resource_set_range/size() conversions Date: Mon, 16 Dec 2024 19:56:14 +0200 Message-Id: <20241216175632.4175-8-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A few sites that could use resource_set_range/size() in setup-bus.c were not picked up earlier due to them no matching the usual pattern. Convert them now. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 303c4fbf2d14..dd9b06947621 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -413,10 +413,8 @@ static void __assign_resources_sorted(struct list_head *head, * consistent. */ if (add_align > dev_res->res->start) { - resource_size_t r_size = resource_size(dev_res->res); - - dev_res->res->start = add_align; - dev_res->res->end = add_align + r_size - 1; + resource_set_range(dev_res->res, add_align, + resource_size(dev_res->res)); list_for_each_entry(dev_res2, head, list) { align = pci_resource_alignment(dev_res2->dev, @@ -1100,7 +1098,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, if (realloc_head && i >= PCI_IOV_RESOURCES && i <= PCI_IOV_RESOURCE_END) { add_align = max(pci_resource_alignment(dev, r), add_align); - r->end = r->start - 1; + resource_set_size(r, 0); add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); children_add_size += r_size; continue; @@ -1180,8 +1178,8 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, b_res->flags = 0; return 0; } - b_res->start = min_align; - b_res->end = size0 + min_align - 1; + + resource_set_range(b_res, min_align, size0); b_res->flags |= IORESOURCE_STARTALIGN; if (bus->self && size1 > size0 && realloc_head) { add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align); @@ -1656,8 +1654,7 @@ static void pci_bridge_release_resources(struct pci_bus *bus, pci_info(dev, "resource %d %pR released\n", PCI_BRIDGE_RESOURCES + idx, r); /* Keep the old size */ - r->end = resource_size(r) - 1; - r->start = 0; + resource_set_range(r, 0, resource_size(r)); r->flags = 0; /* Avoiding touch the one without PREF */ From patchwork Mon Dec 16 17:56:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910150 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40694207662; 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X-CSE-ConnectionGUID: 2LCWezDPTvCFJ/c2/E9NnA== X-CSE-MsgGUID: tyjtpBf6RgaAiknQT0EO6g== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="38543998" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="38543998" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:53 -0800 X-CSE-ConnectionGUID: neOtWnoGStO0aM7YPIGroA== X-CSE-MsgGUID: J09FEm7QQKSzY8lXeKklmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="97149687" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:57:49 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= , =?utf-8?q?Christi?= =?utf-8?q?an_K=C3=B6nig?= Subject: [PATCH 08/25] PCI: Add a helper to identify IOV resources Date: Mon, 16 Dec 2024 19:56:15 +0200 Message-Id: <20241216175632.4175-9-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Michał Winiarski There are multiple places where special handling is required for IOV resources. Extract it to pci_resource_is_iov() helper and drop a few ifdefs. Signed-off-by: Michał Winiarski Reviewed-by: Ilpo Järvinen Reviewed-by: Christian König --- drivers/pci/pci.h | 19 +++++++++++++++---- drivers/pci/setup-bus.c | 7 +++---- drivers/pci/setup-res.c | 4 +--- 3 files changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 2e40fc63ba31..25bae4bfebea 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -621,6 +621,10 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); +static inline bool pci_resource_is_iov(int resno) +{ + return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; +} extern const struct attribute_group sriov_pf_dev_attr_group; extern const struct attribute_group sriov_vf_dev_attr_group; #else @@ -630,12 +634,21 @@ static inline int pci_iov_init(struct pci_dev *dev) } static inline void pci_iov_release(struct pci_dev *dev) { } static inline void pci_iov_remove(struct pci_dev *dev) { } +static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } +static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, + int resno) +{ + return 0; +} static inline void pci_restore_iov_state(struct pci_dev *dev) { } static inline int pci_iov_bus_range(struct pci_bus *bus) { return 0; } - +static inline bool pci_resource_is_iov(int resno) +{ + return false; +} #endif /* CONFIG_PCI_IOV */ #ifdef CONFIG_PCIE_TPH @@ -669,12 +682,10 @@ unsigned long pci_cardbus_resource_alignment(struct resource *); static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, struct resource *res) { -#ifdef CONFIG_PCI_IOV int resno = res - dev->resource; - if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) + if (pci_resource_is_iov(resno)) return pci_sriov_resource_alignment(dev, resno); -#endif if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) return pci_cardbus_resource_alignment(res); return resource_alignment(res); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index dd9b06947621..3907930da00d 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1093,17 +1093,16 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, (r->flags & mask) != type3)) continue; r_size = resource_size(r); -#ifdef CONFIG_PCI_IOV + /* Put SRIOV requested res to the optional list */ - if (realloc_head && i >= PCI_IOV_RESOURCES && - i <= PCI_IOV_RESOURCE_END) { + if (realloc_head && pci_resource_is_iov(i)) { add_align = max(pci_resource_alignment(dev, r), add_align); resource_set_size(r, 0); add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); children_add_size += r_size; continue; } -#endif + /* * aligns[0] is for 1MB (since bridge memory * windows are always at least 1MB aligned), so diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index ca14576bf2bf..79c7ef349856 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -127,10 +127,8 @@ void pci_update_resource(struct pci_dev *dev, int resno) { if (resno <= PCI_ROM_RESOURCE) pci_std_update_resource(dev, resno); -#ifdef CONFIG_PCI_IOV - else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) + else if (pci_resource_is_iov(resno)) pci_iov_update_resource(dev, resno); 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Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 3907930da00d..63c134b087d5 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -285,8 +285,11 @@ static void assign_requested_resources_sorted(struct list_head *head, list_for_each_entry(dev_res, head, list) { res = dev_res->res; idx = res - &dev_res->dev->resource[0]; - if (resource_size(res) && - pci_assign_resource(dev_res->dev, idx)) { + + if (!resource_size(res)) + continue; + + if (pci_assign_resource(dev_res->dev, idx)) { if (fail_head) { /* * If the failed resource is a ROM BAR and From patchwork Mon Dec 16 17:56:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910152 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D460209F58; Mon, 16 Dec 2024 17:58:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371891; cv=none; b=n9YQA1izi/v2ONhAMqaC8ztD2f6HpURPZX51QwuzHY7TPRD/A3au7c31eLfFUG+JnCk4gewe/TqJHNoy4VN1dJ4y/DlpzwK7P6DD3oDTmCj8GvP3FvvhTUm4hzVljnf7VYc36qVJQnMOmuzDEEGHjEEcbo8JztWiZS3evQXNnxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371891; c=relaxed/simple; bh=CBkcy5rzYd/eqjdXBU1hkT0sjsV59h1TDhZErEvno4k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=j3PmMRWs3/xDiJVb29Ap+IiqGjLvoclGYWW4ePBCz6xeZeaGabNUm9kX9k8UPP/kTDO1J5bswODDh2znAKlMaFJ6M9yi/0J2Vbp4h+kTR46W3tJaOov942KJkRPGbo3oCdRqWcUIODW8fK7Lbac7PeSlfXa1vIE8E82fifQS63M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WxYGcOOm; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WxYGcOOm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371890; x=1765907890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CBkcy5rzYd/eqjdXBU1hkT0sjsV59h1TDhZErEvno4k=; b=WxYGcOOmyNeXTuetnzIcr0q+Zh68JZ+DpYNdNW1HTCbeWVERraqJ/icK 0aTjF23d0ZGltRMZ1Z12N1n4FTcNpBn2CsGDVEQkzv+tNT3v2hV79RUaT cakmEO1P2sRrYAQFrIROOlF0V5phodgTIWRhIH6FmXXDDKKIUXunKaKyz xUopZGdT2+r/Kggk8tN2wYcb7/m9fFbjNbDE7VNYha/Cdx9PkLhm6+LQ2 4/cKiQGUCG3W+nE1U8gFyJPyAiLPWke1UJevQiAlCvdN4k5pjkmRx1GBY oYlPWGc5yLboq5d+Ko6AQiMo5WzKz+P+qWFpNP5qXeVbB1DIXrVyhKpVF A==; X-CSE-ConnectionGUID: 0Y5vUwNPRa+5FGvO61IXHw== X-CSE-MsgGUID: YEC+tb7nQU6hNr+a3/8wPg== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="38544015" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="38544015" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:09 -0800 X-CSE-ConnectionGUID: AmrWqJSmRdOIysjgUHgzGg== X-CSE-MsgGUID: zVKvHnL+QNGNo2cyViiWiQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="97149730" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:05 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 10/25] PCI: Add pci_resource_num() helper Date: Mon, 16 Dec 2024 19:56:17 +0200 Message-Id: <20241216175632.4175-11-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 A few places in PCI code, mainly in setup-bus.c, need to reverse lookup the index of a resource in pci_dev's resource array. Create pci_resource_num() helper to avoid repeating the pointer arithmetic trick used to calculate the index. Signed-off-by: Ilpo Järvinen --- drivers/pci/pci.h | 24 +++++++++++++++++++++++- drivers/pci/setup-bus.c | 10 +++++----- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 25bae4bfebea..0b722d158b6a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -330,6 +330,28 @@ void pci_walk_bus_locked(struct pci_bus *top, const char *pci_resource_name(struct pci_dev *dev, unsigned int i); +/** + * pci_resource_num - Reverse lookup resource number from device resources + * @dev: PCI device + * @res: Resource to lookup index for (MUST be a @dev's resource) + * + * Perform reverse lookup to determine the resource number for @res within + * @dev resource array. NOTE: The caller is responsible for ensuring @res is + * among @dev's resources! + * + * Returns: resource number. + */ +static inline int pci_resource_num(const struct pci_dev *dev, + const struct resource *res) +{ + int resno = res - &dev->resource[0]; + + /* Passing a resource that is not among dev's resources? */ + WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); + + return resno; +} + void pci_reassigndev_resource_alignment(struct pci_dev *dev); void pci_disable_bridge_window(struct pci_dev *dev); struct pci_bus *pci_bus_get(struct pci_bus *bus); @@ -682,7 +704,7 @@ unsigned long pci_cardbus_resource_alignment(struct resource *); static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, struct resource *res) { - int resno = res - dev->resource; + int resno = pci_resource_num(dev, res); if (pci_resource_is_iov(resno)) return pci_sriov_resource_alignment(dev, resno); diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 63c134b087d5..8831365418d6 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -242,7 +242,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head, if (!found_match) /* Just skip */ continue; - idx = res - &add_res->dev->resource[0]; + idx = pci_resource_num(add_res->dev, res); res_name = pci_resource_name(add_res->dev, idx); add_size = add_res->add_size; align = add_res->min_align; @@ -284,7 +284,7 @@ static void assign_requested_resources_sorted(struct list_head *head, list_for_each_entry(dev_res, head, list) { res = dev_res->res; - idx = res - &dev_res->dev->resource[0]; + idx = pci_resource_num(dev_res->dev, res); if (!resource_size(res)) continue; @@ -2211,7 +2211,7 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) res->flags = fail_res->flags; if (pci_is_bridge(fail_res->dev)) { - idx = res - &fail_res->dev->resource[0]; + idx = pci_resource_num(fail_res->dev, res); if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END) res->flags = 0; @@ -2295,7 +2295,7 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) res->flags = fail_res->flags; if (pci_is_bridge(fail_res->dev)) { - idx = res - &fail_res->dev->resource[0]; + idx = pci_resource_num(fail_res->dev, res); if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END) res->flags = 0; @@ -2402,7 +2402,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) struct resource *res = dev_res->res; bridge = dev_res->dev; - i = res - bridge->resource; + i = pci_resource_num(bridge, res); res->start = dev_res->start; res->end = dev_res->end; From patchwork Mon Dec 16 17:56:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910153 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E544E20B200; Mon, 16 Dec 2024 17:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; 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d="scan'208";a="38544022" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:16 -0800 X-CSE-ConnectionGUID: dStXW45TTgGTsPhb4Ql6hQ== X-CSE-MsgGUID: 7Dddt8boSoWIVyejvLP4sA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="97149756" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:13 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 11/25] PCI: Add dev & res local variables to resource assignment funcs Date: Mon, 16 Dec 2024 19:56:18 +0200 Message-Id: <20241216175632.4175-12-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Many PCI resource allocation related functions process struct pci_dev_resource items which hold the struct pci_dev and resource pointers. Reduce the number of lines that need indirection by adding 'dev' and 'res' local variable to hold the pointers. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 66 +++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 29 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 8831365418d6..6b4318da1147 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -216,10 +216,11 @@ static inline void reset_resource(struct resource *res) static void reassign_resources_sorted(struct list_head *realloc_head, struct list_head *head) { - struct resource *res; - const char *res_name; struct pci_dev_resource *add_res, *tmp; struct pci_dev_resource *dev_res; + struct pci_dev *dev; + struct resource *res; + const char *res_name; resource_size_t add_size, align; int idx; @@ -227,6 +228,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head, bool found_match = false; res = add_res->res; + dev = add_res->dev; /* Skip resource that has been reset */ if (!res->flags) @@ -242,20 +244,19 @@ static void reassign_resources_sorted(struct list_head *realloc_head, if (!found_match) /* Just skip */ continue; - idx = pci_resource_num(add_res->dev, res); - res_name = pci_resource_name(add_res->dev, idx); + idx = pci_resource_num(dev, res); + res_name = pci_resource_name(dev, idx); add_size = add_res->add_size; align = add_res->min_align; if (!resource_size(res)) { resource_set_range(res, align, add_size); - if (pci_assign_resource(add_res->dev, idx)) + if (pci_assign_resource(dev, idx)) reset_resource(res); } else { res->flags |= add_res->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); - if (pci_reassign_resource(add_res->dev, idx, - add_size, align)) - pci_info(add_res->dev, "%s %pR: failed to add %llx\n", + if (pci_reassign_resource(dev, idx, add_size, align)) + pci_info(dev, "%s %pR: failed to add %llx\n", res_name, res, (unsigned long long) add_size); } @@ -278,18 +279,20 @@ static void reassign_resources_sorted(struct list_head *realloc_head, static void assign_requested_resources_sorted(struct list_head *head, struct list_head *fail_head) { - struct resource *res; struct pci_dev_resource *dev_res; + struct resource *res; + struct pci_dev *dev; int idx; list_for_each_entry(dev_res, head, list) { res = dev_res->res; - idx = pci_resource_num(dev_res->dev, res); + dev = dev_res->dev; + idx = pci_resource_num(dev, res); if (!resource_size(res)) continue; - if (pci_assign_resource(dev_res->dev, idx)) { + if (pci_assign_resource(dev, idx)) { if (fail_head) { /* * If the failed resource is a ROM BAR and @@ -298,8 +301,7 @@ static void assign_requested_resources_sorted(struct list_head *head, */ if (!((idx == PCI_ROM_RESOURCE) && (!(res->flags & IORESOURCE_ROM_ENABLE)))) - add_to_list(fail_head, - dev_res->dev, res, + add_to_list(fail_head, dev, res, 0 /* don't care */, 0 /* don't care */); } @@ -377,6 +379,7 @@ static void __assign_resources_sorted(struct list_head *head, LIST_HEAD(local_fail_head); struct pci_dev_resource *save_res; struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; + struct resource *res; unsigned long fail_type; resource_size_t add_align, align; @@ -394,8 +397,9 @@ static void __assign_resources_sorted(struct list_head *head, /* Update res in head list with add_size in realloc_head list */ list_for_each_entry_safe(dev_res, tmp_res, head, list) { - dev_res->res->end += get_res_add_size(realloc_head, - dev_res->res); + res = dev_res->res; + + res->end += get_res_add_size(realloc_head, res); /* * There are two kinds of additional resources in the list: @@ -403,10 +407,10 @@ static void __assign_resources_sorted(struct list_head *head, * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN * Here just fix the additional alignment for bridge */ - if (!(dev_res->res->flags & IORESOURCE_STARTALIGN)) + if (!(res->flags & IORESOURCE_STARTALIGN)) continue; - add_align = get_res_add_align(realloc_head, dev_res->res); + add_align = get_res_add_align(realloc_head, res); /* * The "head" list is sorted by alignment so resources with @@ -415,9 +419,8 @@ static void __assign_resources_sorted(struct list_head *head, * need to reorder the list by alignment to make it * consistent. */ - if (add_align > dev_res->res->start) { - resource_set_range(dev_res->res, add_align, - resource_size(dev_res->res)); + if (add_align > res->start) { + resource_set_range(res, add_align, resource_size(res)); list_for_each_entry(dev_res2, head, list) { align = pci_resource_alignment(dev_res2->dev, @@ -448,24 +451,29 @@ static void __assign_resources_sorted(struct list_head *head, /* Check failed type */ fail_type = pci_fail_res_type_mask(&local_fail_head); /* Remove not need to be released assigned res from head list etc */ - list_for_each_entry_safe(dev_res, tmp_res, head, list) - if (dev_res->res->parent && - !pci_need_to_release(fail_type, dev_res->res)) { + list_for_each_entry_safe(dev_res, tmp_res, head, list) { + res = dev_res->res; + + if (res->parent && !pci_need_to_release(fail_type, res)) { /* Remove it from realloc_head list */ - remove_from_list(realloc_head, dev_res->res); - remove_from_list(&save_head, dev_res->res); + remove_from_list(realloc_head, res); + remove_from_list(&save_head, res); list_del(&dev_res->list); kfree(dev_res); } + } free_list(&local_fail_head); /* Release assigned resource */ - list_for_each_entry(dev_res, head, list) - if (dev_res->res->parent) - release_resource(dev_res->res); + list_for_each_entry(dev_res, head, list) { + res = dev_res->res; + + if (res->parent) + release_resource(res); + } /* Restore start/end/flags from saved list */ list_for_each_entry(save_res, &save_head, list) { - struct resource *res = save_res->res; + res = save_res->res; res->start = save_res->start; res->end = save_res->end; From patchwork Mon Dec 16 17:56:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910154 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7DF620CCDC; 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a="57250930" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="57250930" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:24 -0800 X-CSE-ConnectionGUID: 1GCzlevXTjumfLGnWuUGMA== X-CSE-MsgGUID: INcC9lW2QxeaUZO6BnveKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="101419048" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:21 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 12/25] PCI: Converge return paths in __assign_resources_sorted() Date: Mon, 16 Dec 2024 19:56:19 +0200 Message-Id: <20241216175632.4175-13-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 All return paths want to free head list in __assign_resources_sorted() so add a label and use goto. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 6b4318da1147..ad7bc6166b23 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -444,8 +444,7 @@ static void __assign_resources_sorted(struct list_head *head, list_for_each_entry(dev_res, head, list) remove_from_list(realloc_head, dev_res->res); free_list(&save_head); - free_list(head); - return; + goto out; } /* Check failed type */ @@ -488,6 +487,8 @@ static void __assign_resources_sorted(struct list_head *head, /* Try to satisfy any additional optional resource requests */ if (realloc_head) reassign_resources_sorted(realloc_head, head); + +out: free_list(head); } From patchwork Mon Dec 16 17:56:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910155 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B4D8C20E038; Mon, 16 Dec 2024 17:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371918; cv=none; b=nd/Qa3jjBMbSizANTOf2UXLACuo/ObSqBNPFyhXXNA21KbWA0cDiC68AMkk4+bCq6/JUNHydChxXw9p25zV+55XagW4dkiFpR7x1DFPdZeB0WCv22SEYfpGySm7D0l5nMfb/7wgy4w2boGhXJFvy/Tsv7FWNfqU+SLClr4N5Utk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371918; c=relaxed/simple; bh=vm6XgHjYOHoP+wOWdHcRPtAguPDJoFo34GGUVlmf8vo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=lewU0urBxVvuBItgbg2hGK2fxxMr/AO0nFXg0AIuaFYU0uacV7uXwQCZ31x0AYbgeOCV7WVPeP4MYHqJFyX76uFH0U46ox7BEZKH4+oOcawspAW/+pHw2qbxzqe+FtxR3OSIMo9ETC3DPs+rtlc03bkfYsD5mFY2eNFXMsZgCMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Le+c/Gek; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Le+c/Gek" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371917; x=1765907917; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vm6XgHjYOHoP+wOWdHcRPtAguPDJoFo34GGUVlmf8vo=; b=Le+c/Gek/+M388X/p7PI5GsYUu0YOPMosoT7+f4Lrl/fqNzM54yydh1J ItjKDbA9QyDLaVS/Aj5CHVeyG1qwbzLfTlfudrfcVxQrO+UGzgz0+UkZ6 Q15gOJbmC6FWlYrQjKd6kWcUj7poLToqTAmBSaUxc5ysTNuAFczDyEdpl 9z19urzZgYjuj4pCbwYBuYJTLrZFsJWrvvOWCZqmESMGd8S4D74IeYuBI NdkkeL1+5IhO4Zp1AWJFLtpS//DCcEzD9ShFK5XrT2l6daVnYv4L+GWAI ph/VB637ssuXjQiiRk01ALnrsmdqrY6BVs+19pIefroWkHu08xS5ROrcM Q==; X-CSE-ConnectionGUID: J/qYGVe8QWGVsOcoAdAg7w== X-CSE-MsgGUID: Mw+oUBeTQpqnb2OPzMl7Jw== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="57250957" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="57250957" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:32 -0800 X-CSE-ConnectionGUID: 8kKD6bYpRAOJQYki8BnUGg== X-CSE-MsgGUID: c1zu1P8bQN+FbuQI+eoxcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="101419065" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:29 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 13/25] PCI: Refactor pdev_sort_resources() & __dev_sort_resources() Date: Mon, 16 Dec 2024 19:56:20 +0200 Message-Id: <20241216175632.4175-14-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Reduce level of call nesting by calling pdev_sort_resources() directly and by moving the tests done inside __dev_sort_resources() into pdev_resources_assignable() helper. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 44 +++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ad7bc6166b23..ba935a050be3 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -127,12 +127,33 @@ static resource_size_t get_res_add_align(struct list_head *head, return dev_res ? dev_res->min_align : 0; } +static bool pdev_resources_assignable(struct pci_dev *dev) +{ + u16 class = dev->class >> 8, command; + + /* Don't touch classless devices or host bridges or IOAPICs */ + if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) + return false; + + /* Don't touch IOAPIC devices already enabled by firmware */ + if (class == PCI_CLASS_SYSTEM_PIC) { + pci_read_config_word(dev, PCI_COMMAND, &command); + if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) + return false; + } + + return true; +} + /* Sort resources by alignment */ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) { struct resource *r; int i; + if (!pdev_resources_assignable(dev)) + return; + pci_dev_for_each_resource(dev, r, i) { const char *r_name = pci_resource_name(dev, i); struct pci_dev_resource *dev_res, *tmp; @@ -176,25 +197,6 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) } } -static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head) -{ - u16 class = dev->class >> 8; - - /* Don't touch classless devices or host bridges or IOAPICs */ - if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) - return; - - /* Don't touch IOAPIC devices already enabled by firmware */ - if (class == PCI_CLASS_SYSTEM_PIC) { - u16 command; - pci_read_config_word(dev, PCI_COMMAND, &command); - if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) - return; - } - - pdev_sort_resources(dev, head); -} - static inline void reset_resource(struct resource *res) { res->start = 0; @@ -498,7 +500,7 @@ static void pdev_assign_resources_sorted(struct pci_dev *dev, { LIST_HEAD(head); - __dev_sort_resources(dev, &head); + pdev_sort_resources(dev, &head); __assign_resources_sorted(&head, add_head, fail_head); } @@ -511,7 +513,7 @@ static void pbus_assign_resources_sorted(const struct pci_bus *bus, LIST_HEAD(head); list_for_each_entry(dev, &bus->devices, bus_list) - __dev_sort_resources(dev, &head); + pdev_sort_resources(dev, &head); __assign_resources_sorted(&head, realloc_head, fail_head); } From patchwork Mon Dec 16 17:56:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910168 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41F11212B17; Mon, 16 Dec 2024 17:58:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; 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a="57250990" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="57250990" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:40 -0800 X-CSE-ConnectionGUID: VuyZKZT8RD6hocPrXKqwGw== X-CSE-MsgGUID: frhC2yjyT1CnwIDe5IKhXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="101419077" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:37 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 14/25] PCI: Use while loop and break instead of gotos Date: Mon, 16 Dec 2024 19:56:21 +0200 Message-Id: <20241216175632.4175-15-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 pci_assign_unassigned_root_bus_resources() and pci_assign_unassigned_bridge_resources() contain ad-hoc loops using backwards goto and gotos out of the loop. Replace them with while loops and break statements. While reindenting the loop bodies, do a few coding style tweaks (add braces & remove parenthesis). Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 212 ++++++++++++++++++++-------------------- 1 file changed, 106 insertions(+), 106 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ba935a050be3..bbe3472cfba9 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2162,78 +2162,79 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) max_depth, pci_try_num); } -again: - /* - * Last try will use add_list, otherwise will try good to have as must - * have, so can realloc parent bridge resource - */ - if (tried_times + 1 == pci_try_num) - add_list = &realloc_head; - /* - * Depth first, calculate sizes and alignments of all subordinate buses. - */ - __pci_bus_size_bridges(bus, add_list); + while (1) { + /* + * Last try will use add_list, otherwise will try good to + * have as must have, so can realloc parent bridge resource + */ + if (tried_times + 1 == pci_try_num) + add_list = &realloc_head; + /* + * Depth first, calculate sizes and alignments of all + * subordinate buses. + */ + __pci_bus_size_bridges(bus, add_list); - pci_root_bus_distribute_available_resources(bus, add_list); + pci_root_bus_distribute_available_resources(bus, add_list); - /* Depth last, allocate resources and update the hardware. */ - __pci_bus_assign_resources(bus, add_list, &fail_head); - if (add_list) - BUG_ON(!list_empty(add_list)); - tried_times++; + /* Depth last, allocate resources and update the hardware. */ + __pci_bus_assign_resources(bus, add_list, &fail_head); + if (add_list) + BUG_ON(!list_empty(add_list)); + tried_times++; - /* Any device complain? */ - if (list_empty(&fail_head)) - goto dump; + /* Any device complain? */ + if (list_empty(&fail_head)) + break; - if (tried_times >= pci_try_num) { - if (enable_local == undefined) - dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n"); - else if (enable_local == auto_enabled) - dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); + if (tried_times >= pci_try_num) { + if (enable_local == undefined) { + dev_info(&bus->dev, + "Some PCI device resources are unassigned, try booting with pci=realloc\n"); + } else if (enable_local == auto_enabled) { + dev_info(&bus->dev, + "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n"); + } + free_list(&fail_head); + break; + } - free_list(&fail_head); - goto dump; - } + dev_info(&bus->dev, "No. %d try to assign unassigned res\n", + tried_times + 1); - dev_info(&bus->dev, "No. %d try to assign unassigned res\n", - tried_times + 1); + /* Third times and later will not check if it is leaf */ + if (tried_times + 1 > 2) + rel_type = whole_subtree; + + /* + * Try to release leaf bridge's resources that doesn't fit + * resource of child device under that bridge. + */ + list_for_each_entry(fail_res, &fail_head, list) { + pci_bus_release_bridge_resources(fail_res->dev->bus, + fail_res->flags & PCI_RES_TYPE_MASK, + rel_type); + } - /* Third times and later will not check if it is leaf */ - if ((tried_times + 1) > 2) - rel_type = whole_subtree; + /* Restore size and flags */ + list_for_each_entry(fail_res, &fail_head, list) { + struct resource *res = fail_res->res; + int idx; - /* - * Try to release leaf bridge's resources that doesn't fit resource of - * child device under that bridge. - */ - list_for_each_entry(fail_res, &fail_head, list) - pci_bus_release_bridge_resources(fail_res->dev->bus, - fail_res->flags & PCI_RES_TYPE_MASK, - rel_type); + res->start = fail_res->start; + res->end = fail_res->end; + res->flags = fail_res->flags; - /* Restore size and flags */ - list_for_each_entry(fail_res, &fail_head, list) { - struct resource *res = fail_res->res; - int idx; - - res->start = fail_res->start; - res->end = fail_res->end; - res->flags = fail_res->flags; - - if (pci_is_bridge(fail_res->dev)) { - idx = pci_resource_num(fail_res->dev, res); - if (idx >= PCI_BRIDGE_RESOURCES && - idx <= PCI_BRIDGE_RESOURCE_END) - res->flags = 0; + if (pci_is_bridge(fail_res->dev)) { + idx = pci_resource_num(fail_res->dev, res); + if (idx >= PCI_BRIDGE_RESOURCES && + idx <= PCI_BRIDGE_RESOURCE_END) + res->flags = 0; + } } + free_list(&fail_head); } - free_list(&fail_head); - goto again; - -dump: - /* Dump the resource on buses */ pci_bus_dump_resources(bus); } @@ -2261,62 +2262,61 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) struct pci_dev_resource *fail_res; int retval; -again: - __pci_bus_size_bridges(parent, &add_list); + while (1) { + __pci_bus_size_bridges(parent, &add_list); - /* - * Distribute remaining resources (if any) equally between hotplug - * bridges below. This makes it possible to extend the hierarchy - * later without running out of resources. - */ - pci_bridge_distribute_available_resources(bridge, &add_list); + /* + * Distribute remaining resources (if any) equally between + * hotplug bridges below. This makes it possible to extend + * the hierarchy later without running out of resources. + */ + pci_bridge_distribute_available_resources(bridge, &add_list); - __pci_bridge_assign_resources(bridge, &add_list, &fail_head); - BUG_ON(!list_empty(&add_list)); - tried_times++; + __pci_bridge_assign_resources(bridge, &add_list, &fail_head); + BUG_ON(!list_empty(&add_list)); + tried_times++; - if (list_empty(&fail_head)) - goto enable_all; + if (list_empty(&fail_head)) + break; - if (tried_times >= 2) { - /* Still fail, don't need to try more */ - free_list(&fail_head); - goto enable_all; - } + if (tried_times >= 2) { + /* Still fail, don't need to try more */ + free_list(&fail_head); + break; + } - printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", - tried_times + 1); + printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", + tried_times + 1); - /* - * Try to release leaf bridge's resources that aren't big enough - * to contain child device resources. - */ - list_for_each_entry(fail_res, &fail_head, list) - pci_bus_release_bridge_resources(fail_res->dev->bus, - fail_res->flags & PCI_RES_TYPE_MASK, - whole_subtree); + /* + * Try to release leaf bridge's resources that aren't big + * enough to contain child device resources. + */ + list_for_each_entry(fail_res, &fail_head, list) { + pci_bus_release_bridge_resources(fail_res->dev->bus, + fail_res->flags & PCI_RES_TYPE_MASK, + whole_subtree); + } - /* Restore size and flags */ - list_for_each_entry(fail_res, &fail_head, list) { - struct resource *res = fail_res->res; - int idx; - - res->start = fail_res->start; - res->end = fail_res->end; - res->flags = fail_res->flags; - - if (pci_is_bridge(fail_res->dev)) { - idx = pci_resource_num(fail_res->dev, res); - if (idx >= PCI_BRIDGE_RESOURCES && - idx <= PCI_BRIDGE_RESOURCE_END) - res->flags = 0; + /* Restore size and flags */ + list_for_each_entry(fail_res, &fail_head, list) { + struct resource *res = fail_res->res; + int idx; + + res->start = fail_res->start; + res->end = fail_res->end; + res->flags = fail_res->flags; + + if (pci_is_bridge(fail_res->dev)) { + idx = pci_resource_num(fail_res->dev, res); + if (idx >= PCI_BRIDGE_RESOURCES && + idx <= PCI_BRIDGE_RESOURCE_END) + res->flags = 0; + } } + free_list(&fail_head); } - free_list(&fail_head); - - goto again; -enable_all: retval = pci_reenable_device(bridge); if (retval) pci_err(bridge, "Error reenabling bridge (%d)\n", retval); From patchwork Mon Dec 16 17:56:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910169 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F24CF212B24; Mon, 16 Dec 2024 17:58:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371934; cv=none; b=lsRr0qzQo2SWkxNX4VcDxQIPseuLxnr7K0qVBQE1rECJvqrs7hFjmyIbfdESElJH4XCKhKrGEFeb0fWRvqJLjQ56KULdSsDtgjssx5crp7cWslt02kYhuijdntb+op9I9P6qZNob/b0S0oFGVo26AMomNmuO0G9ngFjNNjSw2eg= ARC-Message-Signature: i=1; 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Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index bbe3472cfba9..38dbe8b99910 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2256,11 +2256,10 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) struct pci_bus *parent = bridge->subordinate; /* List of resources that want additional resources */ LIST_HEAD(add_list); - int tried_times = 0; LIST_HEAD(fail_head); struct pci_dev_resource *fail_res; - int retval; + int ret; while (1) { __pci_bus_size_bridges(parent, &add_list); @@ -2317,9 +2316,9 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) free_list(&fail_head); } - retval = pci_reenable_device(bridge); - if (retval) - pci_err(bridge, "Error reenabling bridge (%d)\n", retval); + ret = pci_reenable_device(bridge); + if (ret) + pci_err(bridge, "Error reenabling bridge (%d)\n", ret); pci_set_master(bridge); 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d="scan'208";a="101419184" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:58:51 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 16/25] PCI: Consolidate assignment loop next round preparation Date: Mon, 16 Dec 2024 19:56:23 +0200 Message-Id: <20241216175632.4175-17-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 pci_assign_unassigned_root_bus_resources() and pci_assign_unassigned_bridge_resources() have a loop that performs a number rounds to assign resources. The code to prepare for the next round is identical. Consolidate the code that prepares for the next assignment round into pci_prepare_next_assign_round(). Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 104 ++++++++++++++++------------------------ 1 file changed, 42 insertions(+), 62 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 38dbe8b99910..7e5985543734 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2135,6 +2135,45 @@ pci_root_bus_distribute_available_resources(struct pci_bus *bus, } } +static void pci_prepare_next_assign_round(struct list_head *fail_head, + int tried_times, + enum release_type rel_type) +{ + struct pci_dev_resource *fail_res; + + pr_info("PCI: No. %d try to assign unassigned res\n", tried_times + 1); + + /* + * Try to release leaf bridge's resources that aren't big + * enough to contain child device resources. + */ + list_for_each_entry(fail_res, fail_head, list) { + pci_bus_release_bridge_resources(fail_res->dev->bus, + fail_res->flags & PCI_RES_TYPE_MASK, + rel_type); + } + + /* Restore size and flags */ + list_for_each_entry(fail_res, fail_head, list) { + struct resource *res = fail_res->res; + struct pci_dev *dev = fail_res->dev; + int idx = pci_resource_num(dev, res); + + res->start = fail_res->start; + res->end = fail_res->end; + res->flags = fail_res->flags; + + if (!pci_is_bridge(dev)) + continue; + + if (idx >= PCI_BRIDGE_RESOURCES && + idx <= PCI_BRIDGE_RESOURCE_END) + res->flags = 0; + } + + free_list(fail_head); +} + /* * First try will not touch PCI bridge res. * Second and later try will clear small leaf bridge res. @@ -2148,7 +2187,6 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) int tried_times = 0; enum release_type rel_type = leaf_only; LIST_HEAD(fail_head); - struct pci_dev_resource *fail_res; int pci_try_num = 1; enum enable_type enable_local; @@ -2199,40 +2237,11 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) break; } - dev_info(&bus->dev, "No. %d try to assign unassigned res\n", - tried_times + 1); - /* Third times and later will not check if it is leaf */ if (tried_times + 1 > 2) rel_type = whole_subtree; - /* - * Try to release leaf bridge's resources that doesn't fit - * resource of child device under that bridge. - */ - list_for_each_entry(fail_res, &fail_head, list) { - pci_bus_release_bridge_resources(fail_res->dev->bus, - fail_res->flags & PCI_RES_TYPE_MASK, - rel_type); - } - - /* Restore size and flags */ - list_for_each_entry(fail_res, &fail_head, list) { - struct resource *res = fail_res->res; - int idx; - - res->start = fail_res->start; - res->end = fail_res->end; - res->flags = fail_res->flags; - - if (pci_is_bridge(fail_res->dev)) { - idx = pci_resource_num(fail_res->dev, res); - if (idx >= PCI_BRIDGE_RESOURCES && - idx <= PCI_BRIDGE_RESOURCE_END) - res->flags = 0; - } - } - free_list(&fail_head); + pci_prepare_next_assign_round(&fail_head, tried_times, rel_type); } pci_bus_dump_resources(bus); @@ -2258,7 +2267,6 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) LIST_HEAD(add_list); int tried_times = 0; LIST_HEAD(fail_head); - struct pci_dev_resource *fail_res; int ret; while (1) { @@ -2284,36 +2292,8 @@ void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) break; } - printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", - tried_times + 1); - - /* - * Try to release leaf bridge's resources that aren't big - * enough to contain child device resources. - */ - list_for_each_entry(fail_res, &fail_head, list) { - pci_bus_release_bridge_resources(fail_res->dev->bus, - fail_res->flags & PCI_RES_TYPE_MASK, - whole_subtree); - } - - /* Restore size and flags */ - list_for_each_entry(fail_res, &fail_head, list) { - struct resource *res = fail_res->res; - int idx; - - res->start = fail_res->start; - res->end = fail_res->end; - res->flags = fail_res->flags; - - if (pci_is_bridge(fail_res->dev)) { - idx = pci_resource_num(fail_res->dev, res); - if (idx >= PCI_BRIDGE_RESOURCES && - idx <= PCI_BRIDGE_RESOURCE_END) - res->flags = 0; - } - } - free_list(&fail_head); + pci_prepare_next_assign_round(&fail_head, tried_times, + whole_subtree); } ret = pci_reenable_device(bridge); From patchwork Mon Dec 16 17:56:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910171 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8731207A09; 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X-CSE-ConnectionGUID: S35s4FbcQI2zZpgiFBp3GQ== X-CSE-MsgGUID: S3gFA0DiS1K75cA3Z0bOWA== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="52183747" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="52183747" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:03 -0800 X-CSE-ConnectionGUID: DRYnoRS5QNOhGeU4zrhOBw== X-CSE-MsgGUID: r6vStFWIQIass9FssXzEKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="128075848" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:00 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= , Yinghai Lu Subject: [PATCH 17/25] PCI: Remove wrong comment from pci_reassign_resource() Date: Mon, 16 Dec 2024 19:56:24 +0200 Message-Id: <20241216175632.4175-18-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The commit a4ac9fea016f ("PCI : Calculate right add_size") removed including min_align into new_size in pci_reassign_resource() which is correct thing to do. However, it also added a snakeoil comment that the resource would already be aligned with min_align which is incorrect. A resource that is assigned earlier is aligned with the old alignment, NOT with the new requested alignment (min_align) until later deep within the reassignment callchain. Thus, remove the incorrect comment. Signed-off-by: Ilpo Järvinen Cc: Yinghai Lu --- drivers/pci/setup-res.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 79c7ef349856..a862b5d769dc 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -387,7 +387,6 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, return -EINVAL; } - /* already aligned with min_align */ new_size = resource_size(res) + addsize; ret = _pci_assign_resource(dev, resno, new_size, min_align); if (ret) { From patchwork Mon Dec 16 17:56:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910172 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89AAF208984; Mon, 16 Dec 2024 17:59:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371952; cv=none; b=WZIiV064DXEgEeHg1YCCadcnP/BL0R/xbiJNCdBwahMHrdwfjTJuETa1peJi364PID07srFrlvzzcLTFSXv7t56F0HMRaaLRN70vjd65ifiW0254T41WE+cFteWNgaTaQTC1PYXFJT2MEvG8uSZ4t5YsLnwB+TscTFSDuP3S7rc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371952; c=relaxed/simple; bh=eQtWuXJHJ9eWQ0mMHPPcvoBKYqVq+l+21AkCILaf4gg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=N72+wm0bcL/Sn+C6DaeHnbkJDyQBFFALDYDomk1QUh5yyI7JcO94AEYIhN1c9sBW8c10i+tH3fr8fdTK6W+x87W7lidKjF5YfPFX86RHgEEhJNEPrQHI8DlSbb6wogn0Uiw8XA8HrmxsSQuP7c/kUt99h5hZsWs3SoxrzWY82J0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ZIO0COi/; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZIO0COi/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734371952; x=1765907952; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eQtWuXJHJ9eWQ0mMHPPcvoBKYqVq+l+21AkCILaf4gg=; b=ZIO0COi/eGaU1jBE1ComSJgVbVJJZ6l3uvq2F/E68CcqaposGfzhfuDz paANuk7EFR5empEuPgjwNONsCvIGjXJQu3W5elxCsfIvplXIQZpnqmrhf 7KJ/z1kc+9vZ5ci1IzzdbY8KXU8CU8bFhxG/nbuFQCXRt9qiovSBLvKRm ygpXPwozAxTSPkwDjIjlULw2BmHp8Mt4v3CoKGo3pDg8Wx12yMqIZozbu cnyGjGQ2PS2EuCOJH82o6NBihcmQLPD7Mkbvc3WY+QR4ngrUYliXDret0 xGuwtqO9vHakNHJPvKUYC02z0z6yA4A2bvi0jQIQeY8paxrHwAn0ZykcL g==; X-CSE-ConnectionGUID: oa1GA7zCTsShKkUM54xqGQ== X-CSE-MsgGUID: I+aHWgxKTZ+arsdZlCpmJg== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="52183777" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="52183777" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:11 -0800 X-CSE-ConnectionGUID: pDCigzt4SMO0KYjQODDeIg== X-CSE-MsgGUID: 7sisdlSYRAa1YEbFeO1IQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="128075865" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:09 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 18/25] PCI: Add restore_dev_resource() Date: Mon, 16 Dec 2024 19:56:25 +0200 Message-Id: <20241216175632.4175-19-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Resource fitting needs to restore the saved dev resources in a few places. Add a restore_dev_resource() helper for that. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 7e5985543734..d30e8a5a0311 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -127,6 +127,15 @@ static resource_size_t get_res_add_align(struct list_head *head, return dev_res ? dev_res->min_align : 0; } +static void restore_dev_resource(struct pci_dev_resource *dev_res) +{ + struct resource *res = dev_res->res; + + res->start = dev_res->start; + res->end = dev_res->end; + res->flags = dev_res->flags; +} + static bool pdev_resources_assignable(struct pci_dev *dev) { u16 class = dev->class >> 8, command; @@ -473,13 +482,8 @@ static void __assign_resources_sorted(struct list_head *head, release_resource(res); } /* Restore start/end/flags from saved list */ - list_for_each_entry(save_res, &save_head, list) { - res = save_res->res; - - res->start = save_res->start; - res->end = save_res->end; - res->flags = save_res->flags; - } + list_for_each_entry(save_res, &save_head, list) + restore_dev_resource(save_res); free_list(&save_head); requested_and_reassign: @@ -2159,9 +2163,7 @@ static void pci_prepare_next_assign_round(struct list_head *fail_head, struct pci_dev *dev = fail_res->dev; int idx = pci_resource_num(dev, res); - res->start = fail_res->start; - res->end = fail_res->end; - res->flags = fail_res->flags; + restore_dev_resource(fail_res); if (!pci_is_bridge(dev)) continue; @@ -2378,13 +2380,8 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) cleanup: /* Restore size and flags */ - list_for_each_entry(dev_res, &failed, list) { - struct resource *res = dev_res->res; - - res->start = dev_res->start; - res->end = dev_res->end; - res->flags = dev_res->flags; - } + list_for_each_entry(dev_res, &failed, list) + restore_dev_resource(dev_res); free_list(&failed); /* Revert to the old configuration */ @@ -2394,9 +2391,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type) bridge = dev_res->dev; i = pci_resource_num(bridge, res); - res->start = dev_res->start; - res->end = dev_res->end; - res->flags = dev_res->flags; + restore_dev_resource(dev_res); pci_claim_resource(bridge, i); pci_setup_bridge(bridge->subordinate); From patchwork Mon Dec 16 17:56:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910173 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C028207663; Mon, 16 Dec 2024 17:59:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734371961; cv=none; b=jaGPi+I4Tk/CbkItSe3iDoT0tBRfHJr0FIp9WRn+JdJ7k3gtDb+e+07BYZ4+SqTOJqaE1V5dff3N9jyKFiRk+JrKxy46Abwlg1zgdNn+5qv1PCGY54+vLyh8Ld4IB4bNo9D7VpqUGb/dd1ogczCNmpbnnKmUwr/Kfhgf8i3n3Yc= ARC-Message-Signature: i=1; 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d="scan'208";a="128075881" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:17 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 19/25] PCI: Extend enable to check for any optional resource Date: Mon, 16 Dec 2024 19:56:26 +0200 Message-Id: <20241216175632.4175-20-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 pci_enable_resources() checks if device's io and mem resources are all assigned and disallows enable if any resource failed to assign (*) but makes an exception for the case of disabled extension ROM. There are other optional resources, however. Add pci_resource_is_optional() and use it instead of pci_resource_is_disabled_rom() to cover also IOV resources that are also optional as per pbus_size_mem(). As there will be more users of pci_resource_is_optional() inside setup-bus.c in changes coming up after this one, the function is placed there. (*) In practice, resource fitting code calls reset_resource() for any resource it fails to assign which clears resource's ->flags causing pci_enable_resources() to never detect failed resource assignments. This seems undesirable internal logic inconsistency, effectively reset_resource() prevents pci_enable_resources() from functioning as intended. This is one step of many that will be needed towards removing reset_resource(). Signed-off-by: Ilpo Järvinen --- drivers/pci/pci.h | 1 + drivers/pci/setup-bus.c | 12 ++++++++++++ drivers/pci/setup-res.c | 3 +-- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0b722d158b6a..efdb9af8e256 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -329,6 +329,7 @@ void pci_walk_bus_locked(struct pci_bus *top, void *userdata); const char *pci_resource_name(struct pci_dev *dev, unsigned int i); +bool pci_resource_is_optional(const struct pci_dev *dev, int resno); /** * pci_resource_num - Reverse lookup resource number from device resources diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index d30e8a5a0311..a4e40916e2fc 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -206,6 +206,18 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) } } +bool pci_resource_is_optional(const struct pci_dev *dev, int resno) +{ + const struct resource *res = pci_resource_n(dev, resno); + + if (pci_resource_is_iov(resno)) + return true; + if (resno == PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE)) + return true; + + return false; +} + static inline void reset_resource(struct resource *res) { res->start = 0; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index a862b5d769dc..041c881c3c9c 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -494,8 +494,7 @@ int pci_enable_resources(struct pci_dev *dev, int mask) if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) continue; - if ((i == PCI_ROM_RESOURCE) && - (!(r->flags & IORESOURCE_ROM_ENABLE))) + if (pci_resource_is_optional(dev, i)) continue; if (r->flags & IORESOURCE_UNSET) { From patchwork Mon Dec 16 17:56:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910174 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 633F1206F13; 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In future, it would be good to ensure all callers provide a valid realloc_head but that is relatively complex to do in practice and not necessary for the subsequent optional resource handling fix. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index a4e40916e2fc..a10acf4671ef 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -400,14 +400,18 @@ static void __assign_resources_sorted(struct list_head *head, */ LIST_HEAD(save_head); LIST_HEAD(local_fail_head); + LIST_HEAD(dummy_head); struct pci_dev_resource *save_res; struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; struct resource *res; unsigned long fail_type; resource_size_t add_align, align; + if (!realloc_head) + realloc_head = &dummy_head; + /* Check if optional add_size is there */ - if (!realloc_head || list_empty(realloc_head)) + if (list_empty(realloc_head)) goto requested_and_reassign; /* Save original start, end, flags etc at first */ @@ -503,7 +507,7 @@ static void __assign_resources_sorted(struct list_head *head, assign_requested_resources_sorted(head, fail_head); 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d="scan'208";a="120532048" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:32 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 21/25] PCI: Indicate optional resource assignment failures Date: Mon, 16 Dec 2024 19:56:28 +0200 Message-Id: <20241216175632.4175-22-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add pci_dbg() to tell the an assignment failure was for an optional resource and reword existing one about resource resize to tell the change was optional. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index a10acf4671ef..500652eef17b 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -273,13 +273,17 @@ static void reassign_resources_sorted(struct list_head *realloc_head, align = add_res->min_align; if (!resource_size(res)) { resource_set_range(res, align, add_size); - if (pci_assign_resource(dev, idx)) + if (pci_assign_resource(dev, idx)) { + pci_dbg(dev, + "%s %pR: ignoring failure in optional allocation\n", + res_name, res); reset_resource(res); + } } else { res->flags |= add_res->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); if (pci_reassign_resource(dev, idx, add_size, align)) - pci_info(dev, "%s %pR: failed to add %llx\n", + pci_info(dev, "%s %pR: failed to add optional %llx\n", res_name, res, (unsigned long long) add_size); } From patchwork Mon Dec 16 17:56:29 2024 Content-Type: text/plain; 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16 Dec 2024 09:59:41 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 22/25] PCI: Add debug print when releasing resources before retry Date: Mon, 16 Dec 2024 19:56:29 +0200 Message-Id: <20241216175632.4175-23-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 PCI resource fitting is somewhat hard to track because it performs many actions without logging them. In the case inside __assign_resources_sorted(), the resources are released before resource assignment is going to be retried in a different order. That is just one level of retries the resource fitting performs overall so tracking it through repeated assignments or failures of a resource gets messy rather quickly. Simply make the release announced explicitly using pci_dbg() so it is clear what is going on with each resource. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 500652eef17b..5a3b320f1511 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -408,6 +408,9 @@ static void __assign_resources_sorted(struct list_head *head, struct pci_dev_resource *save_res; struct pci_dev_resource *dev_res, *tmp_res, *dev_res2; struct resource *res; + struct pci_dev *dev; + const char *res_name; + int idx; unsigned long fail_type; resource_size_t add_align, align; @@ -497,9 +500,16 @@ static void __assign_resources_sorted(struct list_head *head, /* Release assigned resource */ list_for_each_entry(dev_res, head, list) { res = dev_res->res; + dev = dev_res->dev; + + if (!res->parent) + continue; + + idx = pci_resource_num(dev, res); + res_name = pci_resource_name(dev, idx); + pci_dbg(dev, "%s %pR: releasing\n", res_name, res); - if (res->parent) - release_resource(res); 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d="scan'208";a="120532103" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:49 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 23/25] PCI: Use res->parent to check is resource is assigned Date: Mon, 16 Dec 2024 19:56:30 +0200 Message-Id: <20241216175632.4175-24-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 reassign_resources_sorted() uses resource_size() to select between pci_assign_resource() and pci_reassign_resource(). Due to twisted way bridge window sizing in pbus_size_mem() sets resource sizes to 0, it works to match into IOV resources but that is going to be changed by an upcoming change. Replace resource_size() check with res->parent check that is the true dividing line in between whether assign or reassign function should be used for the resource. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 5a3b320f1511..fec7d68fb971 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -271,7 +271,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head, res_name = pci_resource_name(dev, idx); add_size = add_res->add_size; align = add_res->min_align; - if (!resource_size(res)) { + if (!res->parent) { resource_set_range(res, align, add_size); if (pci_assign_resource(dev, idx)) { pci_dbg(dev, From patchwork Mon Dec 16 17:56:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 13910178 X-Patchwork-Delegate: bhelgaas@google.com Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43732214A61; Mon, 16 Dec 2024 18:00:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734372001; cv=none; b=igW5AIDd14T6ZlH0zjwqyEZVfAnkZjjRaEsfvtdqfh9+g9irHk03GFbDH4GCuYRpqyQBMJbCOv822M1UE/t8c03omd1Au5sC4bfej1pAm9+qd47bV6eCGpQlu+GSXjJo6rgcjfAixUTXuq5/3XZLlba7evfMpvLKZMkCbRaa4yI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734372001; c=relaxed/simple; bh=eKJfIjZN13eMf8fXbPs9Jp7cYI+gqZLyEXdz30LMlk8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=AXmcIIir18+35dFXHtJGVoKtSP5rcoiaRfaNjPJRpeSYy0d62PFt4Wm+HTGm8FLcBKUzPtKHBMoldl1afh7qD1lRbsAfHRCIo2fUK+6NHkqMvLHQAi147SkmWZT7futH2WclO+7XAj1UPqUzo3fV+ZxUcqj1PzQlBpKIL9C69ZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MIddaSYR; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MIddaSYR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734372000; x=1765908000; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eKJfIjZN13eMf8fXbPs9Jp7cYI+gqZLyEXdz30LMlk8=; b=MIddaSYRVJkaNlBJUjWhEA2Rxs32xsTshdl3L/DNIp59ZtXlKeNbrV5L +MZFHYR2rbDNQPudl5VGLIyiPTTQt+f+NRR+PXNrXYWAZt/AKUiiWIG3T SQtv/7STFyKJMNOHCBD/63CQkhd76RpDvhnnRVy/3tBMz2T98GB81a1ol TKzhwb4jXnidIw5G2ND4NT8KkphmjQC8axoJRr5BwqaSp7NPXdIrNZAaS BVvl3HW/yyeOnt6bb2XfaGQgPTK34Do8QdbDeUMi5lZJYfE9FC9HXRQ91 xZFqqQ9aBsDASvbK55TM3w4R06EKvpbfFjI2Mwjeo1eXK/LTObzD9hk8J w==; X-CSE-ConnectionGUID: NVfZwmf3TSekXId2sHbXDw== X-CSE-MsgGUID: 8kCrqhp2T0+/5ohw2AUuUw== X-IronPort-AV: E=McAfee;i="6700,10204,11288"; a="52293372" X-IronPort-AV: E=Sophos;i="6.12,239,1728975600"; d="scan'208";a="52293372" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 10:00:00 -0800 X-CSE-ConnectionGUID: 8nGrb5QMRHqal77wOLZdrw== X-CSE-MsgGUID: AxcYsLYYT+2R+gT1sRgZtg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120532121" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 09:59:57 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= Subject: [PATCH 24/25] PCI: Perform reset_resource() and build fail list in sync Date: Mon, 16 Dec 2024 19:56:31 +0200 Message-Id: <20241216175632.4175-25-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Resetting resource is problematic as it prevent attempting to allocate the resource later, unless something in between restores the resource. Similarly, if fail_head does not contain all resources that were reset, those resource cannot be restored later. The entire reset/restore cycle adds complexity and leaving resources into reseted state causes issues to other code such as for checks done in pci_enable_resources(). Take a small step towards not resetting resources by delaying reset until the end of resource assignment and build failure list (fail_head) in sync with the reset to avoid leaving behind resources that cannot be restored (for the case where the caller provides fail_head in the first place to allow restore somewhere in the callchain, as is not all callers pass non-NULL fail_head). The Expansion ROM check is temporarily left in place while building the failure list until the upcoming change which reworks optional resource handling. Ideally, whole resource reset could be removed but doing that in a big step would make the impact non-tractable due to complexity of all related code. Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index fec7d68fb971..b61f24a5cfa5 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -252,9 +252,14 @@ static void reassign_resources_sorted(struct list_head *realloc_head, res = add_res->res; dev = add_res->dev; + idx = pci_resource_num(dev, res); - /* Skip resource that has been reset */ - if (!res->flags) + /* + * Skip resource that failed the earlier assignment and is + * not optional as it would just fail again. + */ + if (!res->parent && resource_size(res) && + !pci_resource_is_optional(dev, idx)) goto out; /* Skip this resource if not found in head list */ @@ -267,7 +272,6 @@ static void reassign_resources_sorted(struct list_head *realloc_head, if (!found_match) /* Just skip */ continue; - idx = pci_resource_num(dev, res); res_name = pci_resource_name(dev, idx); add_size = add_res->add_size; align = add_res->min_align; @@ -277,7 +281,6 @@ static void reassign_resources_sorted(struct list_head *realloc_head, pci_dbg(dev, "%s %pR: ignoring failure in optional allocation\n", res_name, res); - reset_resource(res); } } else { res->flags |= add_res->flags & @@ -332,7 +335,6 @@ static void assign_requested_resources_sorted(struct list_head *head, 0 /* don't care */, 0 /* don't care */); } - reset_resource(res); } } } @@ -518,13 +520,34 @@ static void __assign_resources_sorted(struct list_head *head, requested_and_reassign: /* Satisfy the must-have resource requests */ - assign_requested_resources_sorted(head, fail_head); + assign_requested_resources_sorted(head, NULL); /* Try to satisfy any additional optional resource requests */ if (!list_empty(realloc_head)) reassign_resources_sorted(realloc_head, head); out: + /* Reset any failed resource, cannot use fail_head as it can be NULL. */ + list_for_each_entry(dev_res, head, list) { + res = dev_res->res; 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d="scan'208";a="52293386" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 10:00:08 -0800 X-CSE-ConnectionGUID: ufQi/Xp/SGKWxgAcC0L7QQ== X-CSE-MsgGUID: 87AdKbF1Sx6RtXaNWRGc9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="120532312" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Dec 2024 10:00:05 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Bjorn Helgaas , linux-pci@vger.kernel.org, =?utf-8?q?Micha=C5=82_Winiarski?= , Igor Mammedov , linux-kernel@vger.kernel.org Cc: Mika Westerberg , =?utf-8?q?Ilpo_J?= =?utf-8?q?=C3=A4rvinen?= , Jia Yao Subject: [PATCH 25/25] PCI: Rework optional resource handling Date: Mon, 16 Dec 2024 19:56:32 +0200 Message-Id: <20241216175632.4175-26-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> References: <20241216175632.4175-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove and rescan cycle can result in not failure to assign a bridge windows if it becomes larger than before the remove. The bridge window size will include space for disabled Expansion ROM, which can causes the bridge window to not fit anymore into the same address space slot on rescan if the Expansion ROM resource was not assigned before the remove. In addition, the optional resource handling is not internally consistent. The resource fitting logic supports three main types of optional resources: - IOV BARs - Expansion ROMs - Bridge window size variation due to optional resources In addition to the above, resizable BARs beyond their current size will require handling optional variation in resource sizes within the resource fitting algorithm (not yet done by the resource fitting code). There are multiple inconsistencies related to optional resource handling: a) The allocation failure of disabled expansion ROM requires special case inside assign_requested_resources_sorted(). b) The optionality of disabled expansion ROM is not considered during bridge window sizing in pbus_size_mem(). c) Setting resource size to zero for optional resource in pbus_size_mem() is problematic because it makes also the alignment invalid, which is checked by pdev_sort_resources(). Optional IOV resources have their size set to zero by pbus_size_mem() but the information about size is stored externally into the struct pci_sriov and complex call-chain trickery in pci_resource_alignment() ensures IOV resources return a valid alignment despite having zero resource size. A solution that is specific to IOV resources makes it hard to use the same solution for other types of resources such as expansion ROM. Simply changing only pbus_size_mem() is not sufficient to fully address the main issue because it would introduce disparity between bridge window sizing and resource allocation. Due size based ordering of resource list during assignment loop, an Expansion ROM resource could steal space from some other resource and make the other resource not fit if the Expansion ROM is larger than the other resource. Thus, the resource assignment functions need to be changed as well. Make optional resource handling more straightforwards. Use pci_resource_is_optional() to determine if a resource is optional or not in both bridge window sizing and assignment failure classification to ensure they always align. Indicate with a parameter to assign_requested_resources_sorted() whether it should attempt to allocate optional resources or not. Always try first to assign all resources (also when realloc_head is not provided). This is required for calls from pci_assign_unassigned_root_bus_resources() that provides realloc_head only with some of its iterations. Non-bridge-window optional resources in realloc_head now have add_size 0. This condition has to be detected in reassign_resources_sorted() before reassigning them (which would fail as there is no size change). Removing add_size=0 optional resources entirely from realloc_head might eventually be doable but further rework in __assign_resources_sorted() is needed first to support such a change. Reported-by: Jia Yao Tested-by: Jia Yao Signed-off-by: Ilpo Järvinen --- drivers/pci/setup-bus.c | 89 +++++++++++++++++++++++++++-------------- 1 file changed, 58 insertions(+), 31 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index b61f24a5cfa5..802643a4de47 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -276,13 +276,14 @@ static void reassign_resources_sorted(struct list_head *realloc_head, add_size = add_res->add_size; align = add_res->min_align; if (!res->parent) { - resource_set_range(res, align, add_size); + resource_set_range(res, align, + resource_size(res) + add_size); if (pci_assign_resource(dev, idx)) { pci_dbg(dev, "%s %pR: ignoring failure in optional allocation\n", res_name, res); } - } else { + } else if (add_size > 0) { res->flags |= add_res->flags & (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); if (pci_reassign_resource(dev, idx, add_size, align)) @@ -302,38 +303,38 @@ static void reassign_resources_sorted(struct list_head *realloc_head, * @head: Head of the list tracking requests for resources * @fail_head: Head of the list tracking requests that could not be * allocated + * @optional: Assign also optional resources * * Satisfy resource requests of each element in the list. Add requests that * could not be satisfied to the failed_list. */ static void assign_requested_resources_sorted(struct list_head *head, - struct list_head *fail_head) + struct list_head *fail_head, + bool optional) { struct pci_dev_resource *dev_res; struct resource *res; struct pci_dev *dev; + bool optional_res; int idx; list_for_each_entry(dev_res, head, list) { res = dev_res->res; dev = dev_res->dev; idx = pci_resource_num(dev, res); + optional_res = pci_resource_is_optional(dev, idx); if (!resource_size(res)) continue; + if (!optional && optional_res) + continue; + if (pci_assign_resource(dev, idx)) { if (fail_head) { - /* - * If the failed resource is a ROM BAR and - * it will be enabled later, don't add it - * to the list. - */ - if (!((idx == PCI_ROM_RESOURCE) && - (!(res->flags & IORESOURCE_ROM_ENABLE)))) - add_to_list(fail_head, dev, res, - 0 /* don't care */, - 0 /* don't care */); + add_to_list(fail_head, dev, res, + 0 /* don't care */, + 0 /* don't care */); } } } @@ -379,6 +380,20 @@ static bool pci_need_to_release(unsigned long mask, struct resource *res) return false; /* Should not get here */ } +/* Return: @true if assignment of a required resource failed. */ +static bool pci_required_resource_failed(struct list_head *fail_head) +{ + struct pci_dev_resource *fail_res; + + list_for_each_entry(fail_res, fail_head, list) { + int idx = pci_resource_num(fail_res->dev, fail_res->res); + + if (!pci_resource_is_optional(fail_res->dev, idx)) + return true; + } + return false; +} + static void __assign_resources_sorted(struct list_head *head, struct list_head *realloc_head, struct list_head *fail_head) @@ -388,9 +403,11 @@ static void __assign_resources_sorted(struct list_head *head, * adjacent, so later reassign can not reallocate them one by one in * parent resource window. * - * Try to assign requested + add_size at beginning. If could do that, - * could get out early. If could not do that, we still try to assign - * requested at first, then try to reassign add_size for some resources. + * Try to assign required and any optional resources at beginning + * (add_size included). If all required resources were successfully + * assigned, get out early. If could not do that, we still try to + * assign required at first, then try to reassign some optional + * resources. * * Separate three resource type checking if we need to release * assigned resource after requested + add_size try. @@ -421,13 +438,13 @@ static void __assign_resources_sorted(struct list_head *head, /* Check if optional add_size is there */ if (list_empty(realloc_head)) - goto requested_and_reassign; + goto assign; /* Save original start, end, flags etc at first */ list_for_each_entry(dev_res, head, list) { if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { free_list(&save_head); - goto requested_and_reassign; + goto assign; } } @@ -471,10 +488,10 @@ static void __assign_resources_sorted(struct list_head *head, } - /* Try updated head list with add_size added */ - assign_requested_resources_sorted(head, &local_fail_head); +assign: + assign_requested_resources_sorted(head, &local_fail_head, true); - /* All assigned with add_size? */ + /* All non-optional resources assigned? */ if (list_empty(&local_fail_head)) { /* Remove head list from realloc_head list */ list_for_each_entry(dev_res, head, list) @@ -483,6 +500,22 @@ static void __assign_resources_sorted(struct list_head *head, goto out; } + /* Without realloc_head and only optional fails, nothing more to do. */ + if (!pci_required_resource_failed(&local_fail_head) && + list_empty(realloc_head)) { + list_for_each_entry(save_res, &save_head, list) { + struct resource *res = save_res->res; + + if (res->parent) + continue; + + restore_dev_resource(save_res); + } + free_list(&local_fail_head); + free_list(&save_head); + goto out; + } + /* Check failed type */ fail_type = pci_fail_res_type_mask(&local_fail_head); /* Remove not need to be released assigned res from head list etc */ @@ -518,9 +551,8 @@ static void __assign_resources_sorted(struct list_head *head, restore_dev_resource(save_res); free_list(&save_head); -requested_and_reassign: /* Satisfy the must-have resource requests */ - assign_requested_resources_sorted(head, NULL); + assign_requested_resources_sorted(head, NULL, false); /* Try to satisfy any additional optional resource requests */ if (!list_empty(realloc_head)) @@ -535,11 +567,7 @@ static void __assign_resources_sorted(struct list_head *head, if (res->parent) continue; - /* - * If the failed resource is a ROM BAR and it will - * be enabled later, don't add it to the list. - */ - if (fail_head && !pci_resource_is_disabled_rom(res, idx)) { + if (fail_head) { add_to_list(fail_head, dev, res, 0 /* don't care */, 0 /* don't care */); @@ -1166,10 +1194,9 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, r_size = resource_size(r); /* Put SRIOV requested res to the optional list */ - if (realloc_head && pci_resource_is_iov(i)) { + if (realloc_head && pci_resource_is_optional(dev, i)) { add_align = max(pci_resource_alignment(dev, r), add_align); - resource_set_size(r, 0); - add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */); + add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */); children_add_size += r_size; continue; }